1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright �� 2022 Intel Corporation
4 */
5
6#ifndef __VLV_DSI_PLL_REGS_H__
7#define __VLV_DSI_PLL_REGS_H__
8
9#include "vlv_dsi_regs.h"
10
11#define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
12#define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
13#define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
14#define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
15
16#define BXT_MAX_VAR_OUTPUT_KHZ			39500
17
18#define BXT_MIPI_CLOCK_CTL			_MMIO(0x46090)
19#define  BXT_MIPI1_DIV_SHIFT			26
20#define  BXT_MIPI2_DIV_SHIFT			10
21#define  BXT_MIPI_DIV_SHIFT(port)		\
22			_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
23					BXT_MIPI2_DIV_SHIFT)
24
25/* TX control divider to select actual TX clock output from (8x/var) */
26#define  BXT_MIPI1_TX_ESCLK_SHIFT		26
27#define  BXT_MIPI2_TX_ESCLK_SHIFT		10
28#define  BXT_MIPI_TX_ESCLK_SHIFT(port)		\
29			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
30					BXT_MIPI2_TX_ESCLK_SHIFT)
31#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(0x3F << 26)
32#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(0x3F << 10)
33#define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
34			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
35					BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
36#define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)	\
37		(((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
38/* RX upper control divider to select actual RX clock output from 8x */
39#define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT		21
40#define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT		5
41#define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)		\
42			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
43					BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
44#define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 21)
45#define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 5)
46#define  BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)	\
47			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
48					BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
49#define  BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val)	\
50		(((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
51/* 8/3X divider to select the actual 8/3X clock output from 8x */
52#define  BXT_MIPI1_8X_BY3_SHIFT                19
53#define  BXT_MIPI2_8X_BY3_SHIFT                3
54#define  BXT_MIPI_8X_BY3_SHIFT(port)          \
55			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
56					BXT_MIPI2_8X_BY3_SHIFT)
57#define  BXT_MIPI1_8X_BY3_DIVIDER_MASK         (3 << 19)
58#define  BXT_MIPI2_8X_BY3_DIVIDER_MASK         (3 << 3)
59#define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)    \
60			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
61						BXT_MIPI2_8X_BY3_DIVIDER_MASK)
62#define  BXT_MIPI_8X_BY3_DIVIDER(port, val)    \
63			(((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
64/* RX lower control divider to select actual RX clock output from 8x */
65#define  BXT_MIPI1_RX_ESCLK_LOWER_SHIFT		16
66#define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT		0
67#define  BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)		\
68			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
69					BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
70#define  BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 16)
71#define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 0)
72#define  BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)	\
73			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
74					BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
75#define  BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val)	\
76		(((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
77
78#define RX_DIVIDER_BIT_1_2                     0x3
79#define RX_DIVIDER_BIT_3_4                     0xC
80
81#define BXT_DSI_PLL_CTL			_MMIO(0x161000)
82#define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
83#define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
84#define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
85#define  BXT_DSIC_16X_BY1		(0 << 10)
86#define  BXT_DSIC_16X_BY2		(1 << 10)
87#define  BXT_DSIC_16X_BY3		(2 << 10)
88#define  BXT_DSIC_16X_BY4		(3 << 10)
89#define  BXT_DSIC_16X_MASK		(3 << 10)
90#define  BXT_DSIA_16X_BY1		(0 << 8)
91#define  BXT_DSIA_16X_BY2		(1 << 8)
92#define  BXT_DSIA_16X_BY3		(2 << 8)
93#define  BXT_DSIA_16X_BY4		(3 << 8)
94#define  BXT_DSIA_16X_MASK		(3 << 8)
95#define  BXT_DSI_FREQ_SEL_SHIFT		8
96#define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
97
98#define BXT_DSI_PLL_RATIO_MAX		0x7D
99#define BXT_DSI_PLL_RATIO_MIN		0x22
100#define GLK_DSI_PLL_RATIO_MAX		0x6F
101#define GLK_DSI_PLL_RATIO_MIN		0x22
102#define BXT_DSI_PLL_RATIO_MASK		0xFF
103#define BXT_REF_CLOCK_KHZ		19200
104
105#define BXT_DSI_PLL_ENABLE		_MMIO(0x46080)
106#define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
107#define  BXT_DSI_PLL_LOCKED		(1 << 30)
108
109#endif /* __VLV_DSI_PLL_REGS_H__ */
110