1/* SPDX-License-Identifier: MIT 2 * 3 * Copyright �� 2023 Intel Corporation 4 */ 5 6#ifndef __INTEL_CX0_PHY_REGS_H__ 7#define __INTEL_CX0_PHY_REGS_H__ 8 9#include "i915_reg_defs.h" 10#include "intel_display_limits.h" 11 12/* 13 * Wrapper macro to convert from port number to the index used in some of the 14 * registers. For Display version 20 and above it converts the port number to a 15 * single range, starting with the TC offsets. When used together with 16 * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second 17 * range. Example: 18 * 19 * PORT_TC1 -> PORT_TC1 20 * PORT_TC2 -> PORT_TC2 21 * PORT_TC3 -> PORT_TC3 22 * PORT_TC4 -> PORT_TC4 23 * PORT_A -> PORT_TC4 + 1 24 * PORT_B -> PORT_TC4 + 2 25 * ... 26 */ 27#define __xe2lpd_port_idx(port) \ 28 (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A) 29 30#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040 31#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140 32#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240 33#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440 34#define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 35 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ 36 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ 37 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ 38 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4) 39#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \ 40 (DISPLAY_VER(i915__) >= 20 ? \ 41 _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \ 42 _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)) 43#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31) 44#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27) 45#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1) 46#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2) 47#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3) 48#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16) 49#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val) 50#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15) 51#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0) 52#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) 53 54#define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 55 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ 56 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ 57 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ 58 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8) 59#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \ 60 (DISPLAY_VER(i915__) >= 20 ? \ 61 _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \ 62 _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) 63#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31) 64#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27) 65#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4 66#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5 67#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16) 68#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val) 69#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15) 70 71#define XELPDP_MSGBUS_TIMEOUT_SLOW 1 72#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2 73#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200 74#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20 75#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 76#define XELPDP_PORT_RESET_START_TIMEOUT_US 5 77#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100 78#define XELPDP_PORT_RESET_END_TIMEOUT 15 79#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1 80 81#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004 82#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104 83#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200 84#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400 85#define _XELPDP_PORT_BUF_CTL1(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 86 _XELPDP_PORT_BUF_CTL1_LN0_A, \ 87 _XELPDP_PORT_BUF_CTL1_LN0_B, \ 88 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ 89 _XELPDP_PORT_BUF_CTL1_LN0_USBC2)) 90#define XELPDP_PORT_BUF_CTL1(i915__, port) \ 91 (DISPLAY_VER(i915__) >= 20 ? \ 92 _XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) : \ 93 _XELPDP_PORT_BUF_CTL1(port)) 94#define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29) 95#define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28) 96#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24) 97#define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18) 98#define XELPDP_PORT_BUF_PORT_DATA_10BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0) 99#define XELPDP_PORT_BUF_PORT_DATA_20BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1) 100#define XELPDP_PORT_BUF_PORT_DATA_40BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2) 101#define XELPDP_PORT_REVERSAL REG_BIT(16) 102#define XELPDP_PORT_BUF_IO_SELECT_TBT REG_BIT(11) 103#define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7) 104#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6) 105#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5) 106#define XELPDP_TCSS_POWER_STATE REG_BIT(4) 107#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1) 108#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val) 109 110#define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 111 _XELPDP_PORT_BUF_CTL1_LN0_A, \ 112 _XELPDP_PORT_BUF_CTL1_LN0_B, \ 113 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ 114 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4) 115#define XELPDP_PORT_BUF_CTL2(i915__, port) \ 116 (DISPLAY_VER(i915__) >= 20 ? \ 117 _XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) : \ 118 _XELPDP_PORT_BUF_CTL2(port)) 119#define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) 120#define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) 121#define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) 122#define _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20) 123#define _XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val) 124#define _XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16) 125#define _XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val) 126#define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \ 127 _XELPDP_LANE0_POWERDOWN_NEW_STATE(val), \ 128 _XELPDP_LANE1_POWERDOWN_NEW_STATE(val)) 129#define XELPDP_LANE_POWERDOWN_NEW_STATE_MASK REG_GENMASK(3, 0) 130#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4) 131#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val) 132 133#define _XELPDP_PORT_BUF_CTL3(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 134 _XELPDP_PORT_BUF_CTL1_LN0_A, \ 135 _XELPDP_PORT_BUF_CTL1_LN0_B, \ 136 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ 137 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8) 138#define XELPDP_PORT_BUF_CTL3(i915__, port) \ 139 (DISPLAY_VER(i915__) >= 20 ? \ 140 _XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) : \ 141 _XELPDP_PORT_BUF_CTL3(port)) 142#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8) 143#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val) 144#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0) 145#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val) 146#define CX0_P0_STATE_ACTIVE 0x0 147#define CX0_P2_STATE_READY 0x2 148#define CX0_P2PG_STATE_DISABLE 0x9 149#define CX0_P4PG_STATE_DISABLE 0xC 150#define CX0_P2_STATE_RESET 0x2 151 152#define _XELPDP_PORT_MSGBUS_TIMER_LN0_A 0x640d8 153#define _XELPDP_PORT_MSGBUS_TIMER_LN0_B 0x641d8 154#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1 0x16f258 155#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2 0x16f458 156#define _XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ 157 _XELPDP_PORT_MSGBUS_TIMER_LN0_A, \ 158 _XELPDP_PORT_MSGBUS_TIMER_LN0_B, \ 159 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1, \ 160 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4) 161#define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane) \ 162 (DISPLAY_VER(i915__) >= 20 ? \ 163 _XELPDP_PORT_MSGBUS_TIMER(__xe2lpd_port_idx(port), lane) : \ 164 _XELPDP_PORT_MSGBUS_TIMER(port, lane)) 165#define XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT REG_BIT(31) 166#define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK REG_GENMASK(23, 0) 167#define XELPDP_PORT_MSGBUS_TIMER_VAL REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 0xa000) 168 169#define _XELPDP_PORT_CLOCK_CTL_A 0x640E0 170#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0 171#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260 172#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460 173#define _XELPDP_PORT_CLOCK_CTL(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 174 _XELPDP_PORT_CLOCK_CTL_A, \ 175 _XELPDP_PORT_CLOCK_CTL_B, \ 176 _XELPDP_PORT_CLOCK_CTL_USBC1, \ 177 _XELPDP_PORT_CLOCK_CTL_USBC2)) 178#define XELPDP_PORT_CLOCK_CTL(i915__, port) \ 179 (DISPLAY_VER(i915__) >= 20 ? \ 180 _XELPDP_PORT_CLOCK_CTL(__xe2lpd_port_idx(port)) : \ 181 _XELPDP_PORT_CLOCK_CTL(port)) 182#define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4)) 183#define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4)) 184#define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4)) 185#define XELPDP_LANE_PCLK_REFCLK_ACK(lane) REG_BIT(28 - ((lane) * 4)) 186 187#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19) 188#define XELPDP_TBT_CLOCK_ACK REG_BIT(18) 189#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12) 190#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val) 191#define XELPDP_DDI_CLOCK_SELECT_NONE 0x0 192#define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8 193#define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9 194#define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc 195#define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd 196#define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe 197#define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf 198#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10) 199#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8) 200#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1) 201#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0) 202 203/* C10 Vendor Registers */ 204#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx)) 205#define C10_PLL0_FRACEN REG_BIT8(4) 206#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0) 207#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0) 208#define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3) 209 210#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx)) 211#define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1) 212#define C10_CMN0_REF_CLK_MPLLB_DIV REG_FIELD_PREP(REG_GENMASK(7, 5), 1) 213#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5) 214#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val) 215#define PHY_C10_VDR_TX(idx) (0xC30 + (idx)) 216#define C10_TX0_TX_MPLLB_SEL REG_BIT(4) 217#define C10_TX1_TERMCTL_MASK REG_GENMASK8(7, 5) 218#define C10_TX1_TERMCTL(val) REG_FIELD_PREP8(C10_TX1_TERMCTL_MASK, val) 219#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1) 220#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2) 221#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1) 222#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0) 223#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02 224#define C10_VDR_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) 225#define C10_VDR_CUSTOM_WIDTH_8_10 REG_FIELD_PREP(C10_VDR_CUSTOM_WIDTH_MASK, 0) 226#define PHY_C10_VDR_OVRD 0xD71 227#define PHY_C10_VDR_OVRD_TX1 REG_BIT8(0) 228#define PHY_C10_VDR_OVRD_TX2 REG_BIT8(2) 229#define PHY_C10_VDR_PRE_OVRD_TX1 0xD80 230#define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0) 231#define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val) 232#define PHY_CX0_VDROVRD_CTL(lane, tx, control) \ 233 (PHY_C10_VDR_PRE_OVRD_TX1 + \ 234 ((lane) ^ (tx)) * 0x10 + (control)) 235 236/* PIPE SPEC Defined Registers */ 237#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control)) 238#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6) 239 240/* C20 Registers */ 241#define PHY_C20_WR_ADDRESS_L 0xC02 242#define PHY_C20_WR_ADDRESS_H 0xC03 243#define PHY_C20_WR_DATA_L 0xC04 244#define PHY_C20_WR_DATA_H 0xC05 245#define PHY_C20_RD_ADDRESS_L 0xC06 246#define PHY_C20_RD_ADDRESS_H 0xC07 247#define PHY_C20_RD_DATA_L 0xC08 248#define PHY_C20_RD_DATA_H 0xC09 249#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00 250#define PHY_C20_VDR_HDMI_RATE 0xD01 251#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0) 252#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1) 253#define PHY_C20_CUSTOM_SERDES(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val) 254#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02 255#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) 256#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val) 257#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx)) 258#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx)) 259#define C20_PHY_TX_RATE REG_GENMASK(2, 0) 260#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx)) 261#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx)) 262#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx)) 263#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx)) 264#define C20_MPLLA_FRACEN REG_BIT(14) 265#define C20_FB_CLK_DIV4_EN REG_BIT(13) 266#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) 267#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx)) 268#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx)) 269#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) 270#define C20_MPLLB_FRACEN REG_BIT(13) 271#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10) 272#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0) 273#define C20_PHY_USE_MPLLB REG_BIT(7) 274 275/* C20 Phy VSwing Masks */ 276#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0) 277#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val) 278 279#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx)) 280 281/* C20 HDMI computed pll definitions */ 282#define REFCLK_38_4_MHZ 38400000 283#define CLOCK_4999MHZ 4999999999 284#define CLOCK_9999MHZ 9999999999 285#define DATARATE_3000000000 3000000000 286#define DATARATE_3500000000 3500000000 287#define DATARATE_4000000000 4000000000 288#define MPLL_FRACN_DEN 0xFFFF 289 290#define SSC_UP_SPREAD REG_BIT16(9) 291#define WORD_CLK_DIV REG_BIT16(8) 292 293#define MPLL_TX_CLK_DIV(val) REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val) 294#define MPLL_MULTIPLIER(val) REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val) 295 296#define MPLLB_ANA_FREQ_VCO_0 0 297#define MPLLB_ANA_FREQ_VCO_1 1 298#define MPLLB_ANA_FREQ_VCO_2 2 299#define MPLLB_ANA_FREQ_VCO_3 3 300#define MPLLB_ANA_FREQ_VCO_MASK REG_GENMASK16(15, 14) 301#define MPLLB_ANA_FREQ_VCO(val) REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val) 302 303#define MPLL_DIV_MULTIPLIER_MASK REG_GENMASK16(7, 0) 304#define MPLL_DIV_MULTIPLIER(val) REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val) 305 306#define CAL_DAC_CODE_31 31 307#define CAL_DAC_CODE_MASK REG_GENMASK16(14, 10) 308#define CAL_DAC_CODE(val) REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val) 309 310#define CP_INT_GS_28 28 311#define CP_INT_GS_MASK REG_GENMASK16(6, 0) 312#define CP_INT_GS(val) REG_FIELD_PREP16(CP_INT_GS_MASK, val) 313 314#define CP_PROP_GS_30 30 315#define CP_PROP_GS_MASK REG_GENMASK16(13, 7) 316#define CP_PROP_GS(val) REG_FIELD_PREP16(CP_PROP_GS_MASK, val) 317 318#define CP_INT_6 6 319#define CP_INT_MASK REG_GENMASK16(6, 0) 320#define CP_INT(val) REG_FIELD_PREP16(CP_INT_MASK, val) 321 322#define CP_PROP_20 20 323#define CP_PROP_MASK REG_GENMASK16(13, 7) 324#define CP_PROP(val) REG_FIELD_PREP16(CP_PROP_MASK, val) 325 326#define V2I_2 2 327#define V2I_MASK REG_GENMASK16(15, 14) 328#define V2I(val) REG_FIELD_PREP16(V2I_MASK, val) 329 330#define HDMI_DIV_1 1 331#define HDMI_DIV_MASK REG_GENMASK16(2, 0) 332#define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val) 333 334#endif /* __INTEL_CX0_REG_DEFS_H__ */ 335