1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24#ifndef _thm_13_0_2_SH_MASK_HEADER 25#define _thm_13_0_2_SH_MASK_HEADER 26 27 28// addressBlock: thm_thm_SmuThmDec 29//THM_TCON_CUR_TMP 30#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 31#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 32#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 33#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 34#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 35#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 36#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 37#define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 38#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 39#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL 40#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L 41#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L 42#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L 43#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L 44#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L 45#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L 46#define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L 47#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L 48//THM_TCON_HTC 49#define THM_TCON_HTC__HTC_EN__SHIFT 0x0 50#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 51#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 52#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 53#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 54#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 55#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT__SHIFT 0x9 56#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa 57#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb 58#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc 59#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN__SHIFT 0xf 60#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 61#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 62#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b 63#define THM_TCON_HTC__HTC_EN_MASK 0x00000001L 64#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L 65#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L 66#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L 67#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L 68#define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L 69#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT_MASK 0x00000200L 70#define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L 71#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L 72#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L 73#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN_MASK 0x00008000L 74#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L 75#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L 76#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L 77//THM_TCON_THERM_TRIP 78#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 79#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 80#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 81#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 82#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 83#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 84#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 85#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe 86#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f 87#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L 88#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L 89#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L 90#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L 91#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L 92#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L 93#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L 94#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L 95#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L 96//THM_CTF_DELAY 97#define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT 0x0 98#define THM_CTF_DELAY__CTF_DELAY_CNT_MASK 0x000FFFFFL 99//THM_GPIO_PROCHOT_CTRL 100#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 101#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 102#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 103#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 104#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 105#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 106#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 107#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 108#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 109#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 110#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 111#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 112#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 113#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f 114#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L 115#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L 116#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L 117#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L 118#define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L 119#define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L 120#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L 121#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L 122#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L 123#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L 124#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L 125#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L 126#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L 127#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L 128//THM_GPIO_THERMTRIP_CTRL 129#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT 0x0 130#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1 131#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2 132#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3 133#define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT 0x4 134#define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT 0x5 135#define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT 0x6 136#define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT 0x7 137#define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT 0x8 138#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x10 139#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x11 140#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0x12 141#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0x13 142#define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT 0x14 143#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0x1f 144#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK 0x00000001L 145#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x00000002L 146#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x00000004L 147#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x00000008L 148#define THM_GPIO_THERMTRIP_CTRL__S0_MASK 0x00000010L 149#define THM_GPIO_THERMTRIP_CTRL__S1_MASK 0x00000020L 150#define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK 0x00000040L 151#define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK 0x00000080L 152#define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK 0x00000100L 153#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x00010000L 154#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x00020000L 155#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x00040000L 156#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x00080000L 157#define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK 0x00100000L 158#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x80000000L 159//THM_GPIO_PWM_CTRL 160#define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT 0x0 161#define THM_GPIO_PWM_CTRL__PD__SHIFT 0x1 162#define THM_GPIO_PWM_CTRL__PU__SHIFT 0x2 163#define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT 0x3 164#define THM_GPIO_PWM_CTRL__S0__SHIFT 0x4 165#define THM_GPIO_PWM_CTRL__S1__SHIFT 0x5 166#define THM_GPIO_PWM_CTRL__RXEN__SHIFT 0x6 167#define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT 0x7 168#define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT 0x8 169#define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT 0x10 170#define THM_GPIO_PWM_CTRL__OE__SHIFT 0x11 171#define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT 0x12 172#define THM_GPIO_PWM_CTRL__A__SHIFT 0x13 173#define THM_GPIO_PWM_CTRL__Y__SHIFT 0x1f 174#define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK 0x00000001L 175#define THM_GPIO_PWM_CTRL__PD_MASK 0x00000002L 176#define THM_GPIO_PWM_CTRL__PU_MASK 0x00000004L 177#define THM_GPIO_PWM_CTRL__SCHMEN_MASK 0x00000008L 178#define THM_GPIO_PWM_CTRL__S0_MASK 0x00000010L 179#define THM_GPIO_PWM_CTRL__S1_MASK 0x00000020L 180#define THM_GPIO_PWM_CTRL__RXEN_MASK 0x00000040L 181#define THM_GPIO_PWM_CTRL__RXSEL0_MASK 0x00000080L 182#define THM_GPIO_PWM_CTRL__RXSEL1_MASK 0x00000100L 183#define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK 0x00010000L 184#define THM_GPIO_PWM_CTRL__OE_MASK 0x00020000L 185#define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK 0x00040000L 186#define THM_GPIO_PWM_CTRL__A_MASK 0x00080000L 187#define THM_GPIO_PWM_CTRL__Y_MASK 0x80000000L 188//THM_GPIO_TACHIN_CTRL 189#define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT 0x0 190#define THM_GPIO_TACHIN_CTRL__PD__SHIFT 0x1 191#define THM_GPIO_TACHIN_CTRL__PU__SHIFT 0x2 192#define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT 0x3 193#define THM_GPIO_TACHIN_CTRL__S0__SHIFT 0x4 194#define THM_GPIO_TACHIN_CTRL__S1__SHIFT 0x5 195#define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT 0x6 196#define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT 0x7 197#define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT 0x8 198#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT 0x10 199#define THM_GPIO_TACHIN_CTRL__OE__SHIFT 0x11 200#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT 0x12 201#define THM_GPIO_TACHIN_CTRL__A__SHIFT 0x13 202#define THM_GPIO_TACHIN_CTRL__Y__SHIFT 0x1f 203#define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK 0x00000001L 204#define THM_GPIO_TACHIN_CTRL__PD_MASK 0x00000002L 205#define THM_GPIO_TACHIN_CTRL__PU_MASK 0x00000004L 206#define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK 0x00000008L 207#define THM_GPIO_TACHIN_CTRL__S0_MASK 0x00000010L 208#define THM_GPIO_TACHIN_CTRL__S1_MASK 0x00000020L 209#define THM_GPIO_TACHIN_CTRL__RXEN_MASK 0x00000040L 210#define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK 0x00000080L 211#define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK 0x00000100L 212#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK 0x00010000L 213#define THM_GPIO_TACHIN_CTRL__OE_MASK 0x00020000L 214#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK 0x00040000L 215#define THM_GPIO_TACHIN_CTRL__A_MASK 0x00080000L 216#define THM_GPIO_TACHIN_CTRL__Y_MASK 0x80000000L 217//THM_GPIO_PUMPOUT_CTRL 218#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT 0x0 219#define THM_GPIO_PUMPOUT_CTRL__PD__SHIFT 0x1 220#define THM_GPIO_PUMPOUT_CTRL__PU__SHIFT 0x2 221#define THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT 0x3 222#define THM_GPIO_PUMPOUT_CTRL__S0__SHIFT 0x4 223#define THM_GPIO_PUMPOUT_CTRL__S1__SHIFT 0x5 224#define THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT 0x6 225#define THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT 0x7 226#define THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT 0x8 227#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT 0x10 228#define THM_GPIO_PUMPOUT_CTRL__OE__SHIFT 0x11 229#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT 0x12 230#define THM_GPIO_PUMPOUT_CTRL__A__SHIFT 0x13 231#define THM_GPIO_PUMPOUT_CTRL__Y__SHIFT 0x1f 232#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK 0x00000001L 233#define THM_GPIO_PUMPOUT_CTRL__PD_MASK 0x00000002L 234#define THM_GPIO_PUMPOUT_CTRL__PU_MASK 0x00000004L 235#define THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK 0x00000008L 236#define THM_GPIO_PUMPOUT_CTRL__S0_MASK 0x00000010L 237#define THM_GPIO_PUMPOUT_CTRL__S1_MASK 0x00000020L 238#define THM_GPIO_PUMPOUT_CTRL__RXEN_MASK 0x00000040L 239#define THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK 0x00000080L 240#define THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK 0x00000100L 241#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK 0x00010000L 242#define THM_GPIO_PUMPOUT_CTRL__OE_MASK 0x00020000L 243#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK 0x00040000L 244#define THM_GPIO_PUMPOUT_CTRL__A_MASK 0x00080000L 245#define THM_GPIO_PUMPOUT_CTRL__Y_MASK 0x80000000L 246//THM_GPIO_PUMPIN_CTRL 247#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT 0x0 248#define THM_GPIO_PUMPIN_CTRL__PD__SHIFT 0x1 249#define THM_GPIO_PUMPIN_CTRL__PU__SHIFT 0x2 250#define THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT 0x3 251#define THM_GPIO_PUMPIN_CTRL__S0__SHIFT 0x4 252#define THM_GPIO_PUMPIN_CTRL__S1__SHIFT 0x5 253#define THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT 0x6 254#define THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT 0x7 255#define THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT 0x8 256#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT 0x10 257#define THM_GPIO_PUMPIN_CTRL__OE__SHIFT 0x11 258#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT 0x12 259#define THM_GPIO_PUMPIN_CTRL__A__SHIFT 0x13 260#define THM_GPIO_PUMPIN_CTRL__Y__SHIFT 0x1f 261#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK 0x00000001L 262#define THM_GPIO_PUMPIN_CTRL__PD_MASK 0x00000002L 263#define THM_GPIO_PUMPIN_CTRL__PU_MASK 0x00000004L 264#define THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK 0x00000008L 265#define THM_GPIO_PUMPIN_CTRL__S0_MASK 0x00000010L 266#define THM_GPIO_PUMPIN_CTRL__S1_MASK 0x00000020L 267#define THM_GPIO_PUMPIN_CTRL__RXEN_MASK 0x00000040L 268#define THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK 0x00000080L 269#define THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK 0x00000100L 270#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK 0x00010000L 271#define THM_GPIO_PUMPIN_CTRL__OE_MASK 0x00020000L 272#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK 0x00040000L 273#define THM_GPIO_PUMPIN_CTRL__A_MASK 0x00080000L 274#define THM_GPIO_PUMPIN_CTRL__Y_MASK 0x80000000L 275//THM_THERMAL_INT_ENA 276#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 277#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 278#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 279#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 280#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 281#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 282#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L 283#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L 284#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L 285#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L 286#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L 287#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L 288//THM_THERMAL_INT_CTRL 289#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 290#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 291#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10 292#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 293#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 294#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 295#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b 296#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c 297#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d 298#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL 299#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L 300#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L 301#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L 302#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L 303#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L 304#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L 305#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L 306#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L 307//THM_THERMAL_INT_STATUS 308#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 309#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 310#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 311#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3 312#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L 313#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L 314#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L 315#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L 316//THM_TMON0_RDIL0_DATA 317#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 318#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb 319#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc 320#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007FFL 321#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L 322#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00FFF000L 323//THM_TMON0_RDIL1_DATA 324#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 325#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb 326#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc 327#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007FFL 328#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L 329#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00FFF000L 330//THM_TMON0_RDIL2_DATA 331#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 332#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb 333#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc 334#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007FFL 335#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L 336#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00FFF000L 337//THM_TMON0_RDIL3_DATA 338#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 339#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb 340#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc 341#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007FFL 342#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L 343#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00FFF000L 344//THM_TMON0_RDIL4_DATA 345#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 346#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb 347#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc 348#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007FFL 349#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L 350#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00FFF000L 351//THM_TMON0_RDIL5_DATA 352#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 353#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb 354#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc 355#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007FFL 356#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L 357#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00FFF000L 358//THM_TMON0_RDIL6_DATA 359#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 360#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb 361#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc 362#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007FFL 363#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L 364#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00FFF000L 365//THM_TMON0_RDIL7_DATA 366#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 367#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb 368#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc 369#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007FFL 370#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L 371#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00FFF000L 372//THM_TMON0_RDIL8_DATA 373#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 374#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb 375#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc 376#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007FFL 377#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L 378#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00FFF000L 379//THM_TMON0_RDIL9_DATA 380#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 381#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb 382#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc 383#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007FFL 384#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L 385#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00FFF000L 386//THM_TMON0_RDIL10_DATA 387#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 388#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb 389#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc 390#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007FFL 391#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L 392#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00FFF000L 393//THM_TMON0_RDIL11_DATA 394#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 395#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb 396#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc 397#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007FFL 398#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L 399#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00FFF000L 400//THM_TMON0_RDIL12_DATA 401#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 402#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb 403#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc 404#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007FFL 405#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L 406#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00FFF000L 407//THM_TMON0_RDIL13_DATA 408#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 409#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb 410#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc 411#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007FFL 412#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L 413#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00FFF000L 414//THM_TMON0_RDIL14_DATA 415#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 416#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb 417#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc 418#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007FFL 419#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L 420#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00FFF000L 421//THM_TMON0_RDIL15_DATA 422#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 423#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb 424#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc 425#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007FFL 426#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L 427#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00FFF000L 428//THM_TMON0_RDIR0_DATA 429#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 430#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb 431#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc 432#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007FFL 433#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L 434#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00FFF000L 435//THM_TMON0_RDIR1_DATA 436#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 437#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb 438#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc 439#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007FFL 440#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L 441#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00FFF000L 442//THM_TMON0_RDIR2_DATA 443#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 444#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb 445#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc 446#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007FFL 447#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L 448#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00FFF000L 449//THM_TMON0_RDIR3_DATA 450#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 451#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb 452#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc 453#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007FFL 454#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L 455#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00FFF000L 456//THM_TMON0_RDIR4_DATA 457#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 458#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb 459#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc 460#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007FFL 461#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L 462#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00FFF000L 463//THM_TMON0_RDIR5_DATA 464#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 465#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb 466#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc 467#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007FFL 468#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L 469#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00FFF000L 470//THM_TMON0_RDIR6_DATA 471#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 472#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb 473#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc 474#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007FFL 475#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L 476#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00FFF000L 477//THM_TMON0_RDIR7_DATA 478#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 479#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb 480#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc 481#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007FFL 482#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L 483#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00FFF000L 484//THM_TMON0_RDIR8_DATA 485#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 486#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb 487#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc 488#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007FFL 489#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L 490#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00FFF000L 491//THM_TMON0_RDIR9_DATA 492#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 493#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb 494#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc 495#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007FFL 496#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L 497#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00FFF000L 498//THM_TMON0_RDIR10_DATA 499#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 500#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb 501#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc 502#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007FFL 503#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L 504#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00FFF000L 505//THM_TMON0_RDIR11_DATA 506#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 507#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb 508#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc 509#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007FFL 510#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L 511#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00FFF000L 512//THM_TMON0_RDIR12_DATA 513#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 514#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb 515#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc 516#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007FFL 517#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L 518#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00FFF000L 519//THM_TMON0_RDIR13_DATA 520#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 521#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb 522#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc 523#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007FFL 524#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L 525#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00FFF000L 526//THM_TMON0_RDIR14_DATA 527#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 528#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb 529#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc 530#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007FFL 531#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L 532#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00FFF000L 533//THM_TMON0_RDIR15_DATA 534#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 535#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb 536#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc 537#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007FFL 538#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L 539#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00FFF000L 540//THM_TMON0_INT_DATA 541#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 542#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb 543#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc 544#define THM_TMON0_INT_DATA__Z_MASK 0x000007FFL 545#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L 546#define THM_TMON0_INT_DATA__TEMP_MASK 0x00FFF000L 547//THM_TMON0_CTRL 548#define THM_TMON0_CTRL__POWER_DOWN__SHIFT 0x0 549#define THM_TMON0_CTRL__BGADJ__SHIFT 0x1 550#define THM_TMON0_CTRL__BGADJ_MODE__SHIFT 0x9 551#define THM_TMON0_CTRL__TMON_PAUSE__SHIFT 0xa 552#define THM_TMON0_CTRL__INT_MEAS_EN__SHIFT 0xb 553#define THM_TMON0_CTRL__EN_CFG_SERDES__SHIFT 0xd 554#define THM_TMON0_CTRL__POWER_DOWN_MASK 0x00000001L 555#define THM_TMON0_CTRL__BGADJ_MASK 0x000001FEL 556#define THM_TMON0_CTRL__BGADJ_MODE_MASK 0x00000200L 557#define THM_TMON0_CTRL__TMON_PAUSE_MASK 0x00000400L 558#define THM_TMON0_CTRL__INT_MEAS_EN_MASK 0x00000800L 559#define THM_TMON0_CTRL__EN_CFG_SERDES_MASK 0x00002000L 560//THM_TMON0_CTRL2 561#define THM_TMON0_CTRL2__RDIL_PRESENT__SHIFT 0x0 562#define THM_TMON0_CTRL2__RDIR_PRESENT__SHIFT 0x10 563#define THM_TMON0_CTRL2__RDIL_PRESENT_MASK 0x0000FFFFL 564#define THM_TMON0_CTRL2__RDIR_PRESENT_MASK 0xFFFF0000L 565//THM_TMON1_RDIL0_DATA 566#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 567#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb 568#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc 569#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007FFL 570#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L 571#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00FFF000L 572//THM_TMON1_RDIL1_DATA 573#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 574#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb 575#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc 576#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007FFL 577#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L 578#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00FFF000L 579//THM_TMON1_RDIL2_DATA 580#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 581#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb 582#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc 583#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007FFL 584#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L 585#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00FFF000L 586//THM_TMON1_RDIL3_DATA 587#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 588#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb 589#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc 590#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007FFL 591#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L 592#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00FFF000L 593//THM_TMON1_RDIL4_DATA 594#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 595#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb 596#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc 597#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007FFL 598#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L 599#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00FFF000L 600//THM_TMON1_RDIL5_DATA 601#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 602#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb 603#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc 604#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007FFL 605#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L 606#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00FFF000L 607//THM_TMON1_RDIL6_DATA 608#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 609#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb 610#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc 611#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007FFL 612#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L 613#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00FFF000L 614//THM_TMON1_RDIL7_DATA 615#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 616#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb 617#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc 618#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007FFL 619#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L 620#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00FFF000L 621//THM_TMON1_RDIL8_DATA 622#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 623#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb 624#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc 625#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007FFL 626#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L 627#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00FFF000L 628//THM_TMON1_RDIL9_DATA 629#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 630#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb 631#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc 632#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007FFL 633#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L 634#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00FFF000L 635//THM_TMON1_RDIL10_DATA 636#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 637#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb 638#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc 639#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007FFL 640#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L 641#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00FFF000L 642//THM_TMON1_RDIL11_DATA 643#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 644#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb 645#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc 646#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007FFL 647#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L 648#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00FFF000L 649//THM_TMON1_RDIL12_DATA 650#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 651#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb 652#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc 653#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007FFL 654#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L 655#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00FFF000L 656//THM_TMON1_RDIL13_DATA 657#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 658#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb 659#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc 660#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007FFL 661#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L 662#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00FFF000L 663//THM_TMON1_RDIL14_DATA 664#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 665#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb 666#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc 667#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007FFL 668#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L 669#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00FFF000L 670//THM_TMON1_RDIL15_DATA 671#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 672#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb 673#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc 674#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007FFL 675#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L 676#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00FFF000L 677//THM_TMON1_RDIR0_DATA 678#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 679#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb 680#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc 681#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007FFL 682#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L 683#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00FFF000L 684//THM_TMON1_RDIR1_DATA 685#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 686#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb 687#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc 688#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007FFL 689#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L 690#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00FFF000L 691//THM_TMON1_RDIR2_DATA 692#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 693#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb 694#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc 695#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007FFL 696#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L 697#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00FFF000L 698//THM_TMON1_RDIR3_DATA 699#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 700#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb 701#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc 702#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007FFL 703#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L 704#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00FFF000L 705//THM_TMON1_RDIR4_DATA 706#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 707#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb 708#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc 709#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007FFL 710#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L 711#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00FFF000L 712//THM_TMON1_RDIR5_DATA 713#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 714#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb 715#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc 716#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007FFL 717#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L 718#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00FFF000L 719//THM_TMON1_RDIR6_DATA 720#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 721#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb 722#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc 723#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007FFL 724#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L 725#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00FFF000L 726//THM_TMON1_RDIR7_DATA 727#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 728#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb 729#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc 730#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007FFL 731#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L 732#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00FFF000L 733//THM_TMON1_RDIR8_DATA 734#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 735#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb 736#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc 737#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007FFL 738#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L 739#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00FFF000L 740//THM_TMON1_RDIR9_DATA 741#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 742#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb 743#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc 744#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007FFL 745#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L 746#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00FFF000L 747//THM_TMON1_RDIR10_DATA 748#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 749#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb 750#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc 751#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007FFL 752#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L 753#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00FFF000L 754//THM_TMON1_RDIR11_DATA 755#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 756#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb 757#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc 758#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007FFL 759#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L 760#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00FFF000L 761//THM_TMON1_RDIR12_DATA 762#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 763#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb 764#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc 765#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007FFL 766#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L 767#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00FFF000L 768//THM_TMON1_RDIR13_DATA 769#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 770#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb 771#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc 772#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007FFL 773#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L 774#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00FFF000L 775//THM_TMON1_RDIR14_DATA 776#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 777#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb 778#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc 779#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007FFL 780#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L 781#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00FFF000L 782//THM_TMON1_RDIR15_DATA 783#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 784#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb 785#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc 786#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007FFL 787#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L 788#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00FFF000L 789//THM_TMON1_INT_DATA 790#define THM_TMON1_INT_DATA__Z__SHIFT 0x0 791#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb 792#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc 793#define THM_TMON1_INT_DATA__Z_MASK 0x000007FFL 794#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L 795#define THM_TMON1_INT_DATA__TEMP_MASK 0x00FFF000L 796//THM_DIE1_TEMP 797#define THM_DIE1_TEMP__TEMP__SHIFT 0x0 798#define THM_DIE1_TEMP__VALID__SHIFT 0xb 799#define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL 800#define THM_DIE1_TEMP__VALID_MASK 0x00000800L 801//THM_DIE2_TEMP 802#define THM_DIE2_TEMP__TEMP__SHIFT 0x0 803#define THM_DIE2_TEMP__VALID__SHIFT 0xb 804#define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL 805#define THM_DIE2_TEMP__VALID_MASK 0x00000800L 806//THM_DIE3_TEMP 807#define THM_DIE3_TEMP__TEMP__SHIFT 0x0 808#define THM_DIE3_TEMP__VALID__SHIFT 0xb 809#define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL 810#define THM_DIE3_TEMP__VALID_MASK 0x00000800L 811//THM_SW_TEMP 812#define THM_SW_TEMP__SW_TEMP__SHIFT 0x0 813#define THM_SW_TEMP__SW_TEMP_MASK 0x000001FFL 814//CG_MULT_THERMAL_CTRL 815#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 816#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 817#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 818#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 819#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL 820#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L 821#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L 822#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L 823//CG_MULT_THERMAL_STATUS 824#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 825#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 826#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL 827#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L 828//CG_THERMAL_RANGE 829#define CG_THERMAL_RANGE__ASIC_T_MAX__SHIFT 0x0 830#define CG_THERMAL_RANGE__ASIC_T_MIN__SHIFT 0x10 831#define CG_THERMAL_RANGE__ASIC_T_MAX_MASK 0x000001FFL 832#define CG_THERMAL_RANGE__ASIC_T_MIN_MASK 0x01FF0000L 833//THM_TMON_CONFIG 834#define THM_TMON_CONFIG__NUM_ACQ__SHIFT 0x0 835#define THM_TMON_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 836#define THM_TMON_CONFIG__TSEN_TMON_MODE__SHIFT 0x4 837#define THM_TMON_CONFIG__CONFIG_SOURCE__SHIFT 0x5 838#define THM_TMON_CONFIG__RE_CALIB_EN__SHIFT 0x6 839#define THM_TMON_CONFIG__Z__SHIFT 0x15 840#define THM_TMON_CONFIG__NUM_ACQ_MASK 0x00000007L 841#define THM_TMON_CONFIG__FORCE_MAX_ACQ_MASK 0x00000008L 842#define THM_TMON_CONFIG__TSEN_TMON_MODE_MASK 0x00000010L 843#define THM_TMON_CONFIG__CONFIG_SOURCE_MASK 0x00000020L 844#define THM_TMON_CONFIG__RE_CALIB_EN_MASK 0x00000040L 845#define THM_TMON_CONFIG__Z_MASK 0xFFE00000L 846//THM_TMON_CONFIG2 847#define THM_TMON_CONFIG2__A__SHIFT 0x0 848#define THM_TMON_CONFIG2__B__SHIFT 0xc 849#define THM_TMON_CONFIG2__C__SHIFT 0x12 850#define THM_TMON_CONFIG2__K__SHIFT 0x1d 851#define THM_TMON_CONFIG2__A_MASK 0x00000FFFL 852#define THM_TMON_CONFIG2__B_MASK 0x0003F000L 853#define THM_TMON_CONFIG2__C_MASK 0x1FFC0000L 854#define THM_TMON_CONFIG2__K_MASK 0x20000000L 855//THM_TMON0_COEFF 856#define THM_TMON0_COEFF__C_OFFSET__SHIFT 0x0 857#define THM_TMON0_COEFF__D__SHIFT 0xb 858#define THM_TMON0_COEFF__C_OFFSET_MASK 0x000007FFL 859#define THM_TMON0_COEFF__D_MASK 0x0003F800L 860//THM_TMON1_COEFF 861#define THM_TMON1_COEFF__C_OFFSET__SHIFT 0x0 862#define THM_TMON1_COEFF__D__SHIFT 0xb 863#define THM_TMON1_COEFF__C_OFFSET_MASK 0x000007FFL 864#define THM_TMON1_COEFF__D_MASK 0x0003F800L 865//CG_FDO_CTRL0 866#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 867#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 868#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 869#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 870#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 871#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 872#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL 873#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0x0000FF00L 874#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x00010000L 875#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x007E0000L 876#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x00800000L 877#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xFF000000L 878//CG_FDO_CTRL1 879#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 880#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 881#define CG_FDO_CTRL1__M__SHIFT 0x10 882#define CG_FDO_CTRL1__TACH_IN_MAX__SHIFT 0x18 883#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL 884#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L 885#define CG_FDO_CTRL1__M_MASK 0x00FF0000L 886#define CG_FDO_CTRL1__TACH_IN_MAX_MASK 0xFF000000L 887//CG_FDO_CTRL2 888#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 889#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 890#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb 891#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe 892#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 893#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 894#define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL 895#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x00000700L 896#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L 897#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x0001C000L 898#define CG_FDO_CTRL2__TMAX_MASK 0x01FE0000L 899#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L 900//CG_TACH_CTRL 901#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 902#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 903#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L 904#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 905//CG_TACH_STATUS 906#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 907#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL 908//CG_THERMAL_STATUS 909#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 910#define CG_THERMAL_STATUS__TACH_IN_H_DEGLITCH_CNT__SHIFT 0x11 911#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L 912#define CG_THERMAL_STATUS__TACH_IN_H_DEGLITCH_CNT_MASK 0xFFFE0000L 913//CG_PUMP_CTRL0 914#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY__SHIFT 0x0 915#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY__SHIFT 0x8 916#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL__SHIFT 0x10 917#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER__SHIFT 0x11 918#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN__SHIFT 0x17 919#define CG_PUMP_CTRL0__PUMP_PWM_RAMP__SHIFT 0x18 920#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY_MASK 0x000000FFL 921#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY_MASK 0x0000FF00L 922#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL_MASK 0x00010000L 923#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER_MASK 0x007E0000L 924#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN_MASK 0x00800000L 925#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_MASK 0xFF000000L 926//CG_PUMP_CTRL1 927#define CG_PUMP_CTRL1__PMAX_DUTY100__SHIFT 0x0 928#define CG_PUMP_CTRL1__PMIN_DUTY__SHIFT 0x8 929#define CG_PUMP_CTRL1__M__SHIFT 0x10 930#define CG_PUMP_CTRL1__TACH_IN_MAX__SHIFT 0x18 931#define CG_PUMP_CTRL1__PMAX_DUTY100_MASK 0x000000FFL 932#define CG_PUMP_CTRL1__PMIN_DUTY_MASK 0x0000FF00L 933#define CG_PUMP_CTRL1__M_MASK 0x00FF0000L 934#define CG_PUMP_CTRL1__TACH_IN_MAX_MASK 0xFF000000L 935//CG_PUMP_CTRL2 936#define CG_PUMP_CTRL2__TMIN__SHIFT 0x0 937#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME__SHIFT 0x8 938#define CG_PUMP_CTRL2__PUMP_PWM_MODE__SHIFT 0xb 939#define CG_PUMP_CTRL2__TMIN_HYSTER__SHIFT 0xe 940#define CG_PUMP_CTRL2__TMAX__SHIFT 0x11 941#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 942#define CG_PUMP_CTRL2__TMIN_MASK 0x000000FFL 943#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME_MASK 0x00000700L 944#define CG_PUMP_CTRL2__PUMP_PWM_MODE_MASK 0x00003800L 945#define CG_PUMP_CTRL2__TMIN_HYSTER_MASK 0x0001C000L 946#define CG_PUMP_CTRL2__TMAX_MASK 0x01FE0000L 947#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L 948//CG_PUMP_TACH_CTRL 949#define CG_PUMP_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 950#define CG_PUMP_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 951#define CG_PUMP_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L 952#define CG_PUMP_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 953//CG_PUMP_TACH_STATUS 954#define CG_PUMP_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 955#define CG_PUMP_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL 956//CG_PUMP_STATUS 957#define CG_PUMP_STATUS__PUMP_PWM_DUTY__SHIFT 0x9 958#define CG_PUMP_STATUS__PUMP_IN_H_DEGLITCH_CNT__SHIFT 0x11 959#define CG_PUMP_STATUS__PUMP_PWM_DUTY_MASK 0x0001FE00L 960#define CG_PUMP_STATUS__PUMP_IN_H_DEGLITCH_CNT_MASK 0xFFFE0000L 961//THM_TCON_LOCAL0 962#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 963#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 964#define THM_TCON_LOCAL0__TMON2_PwrDn_Dis__SHIFT 0x3 965#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x00000002L 966#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x00000004L 967#define THM_TCON_LOCAL0__TMON2_PwrDn_Dis_MASK 0x00000008L 968//THM_TCON_LOCAL1 969#define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT 0x0 970#define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT 0x1 971#define THM_TCON_LOCAL1__Turn_Off_TMON2__SHIFT 0x2 972#define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT 0x4 973#define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT 0x5 974#define THM_TCON_LOCAL1__PowerDownTmon2__SHIFT 0x6 975#define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK 0x00000001L 976#define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK 0x00000002L 977#define THM_TCON_LOCAL1__Turn_Off_TMON2_MASK 0x00000004L 978#define THM_TCON_LOCAL1__PowerDownTmon0_MASK 0x00000010L 979#define THM_TCON_LOCAL1__PowerDownTmon1_MASK 0x00000020L 980#define THM_TCON_LOCAL1__PowerDownTmon2_MASK 0x00000040L 981//THM_TCON_LOCAL2 982#define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0 983#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2 984#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 985#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 986#define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa 987#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb 988#define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L 989#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL 990#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L 991#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L 992#define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L 993#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L 994//THM_TCON_LOCAL3 995#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 996#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL 997//THM_TCON_LOCAL4 998#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 999#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL 1000//THM_TCON_LOCAL5 1001#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 1002#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL 1003//THM_TCON_LOCAL6 1004#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 1005#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL 1006//THM_TCON_LOCAL7 1007#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 1008#define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL 1009//THM_TCON_LOCAL8 1010#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 1011#define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL 1012//THM_TCON_LOCAL9 1013#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 1014#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x000007FFL 1015//THM_TCON_LOCAL10 1016#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 1017#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0x000000FFL 1018//THM_TCON_LOCAL11 1019#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 1020#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x000007FFL 1021//THM_TCON_LOCAL12 1022#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 1023#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0x000000FFL 1024//THM_TCON_LOCAL14 1025#define THM_TCON_LOCAL14__Tj_Max_TMON2__SHIFT 0x0 1026#define THM_TCON_LOCAL14__Tj_Max_TMON2_MASK 0x000007FFL 1027//THM_TCON_LOCAL15 1028#define THM_TCON_LOCAL15__TMON2_Tj_Max_RS_ID__SHIFT 0x0 1029#define THM_TCON_LOCAL15__TMON2_Tj_Max_RS_ID_MASK 0x000000FFL 1030//THM_TCON_LOCAL13 1031#define THM_TCON_LOCAL13__boot_done__SHIFT 0x0 1032#define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L 1033//XTAL_CNTL 1034#define XTAL_CNTL__PCIE_REFCLK_SWITCH__SHIFT 0x0 1035#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN__SHIFT 0x4 1036#define XTAL_CNTL__CORE_XTAL_PWDN__SHIFT 0x8 1037#define XTAL_CNTL__OSC_GAIN_EN__SHIFT 0xc 1038#define XTAL_CNTL__PCIE_REFCLK_SWITCH_MASK 0x00000001L 1039#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN_MASK 0x00000010L 1040#define XTAL_CNTL__CORE_XTAL_PWDN_MASK 0x00000100L 1041#define XTAL_CNTL__OSC_GAIN_EN_MASK 0x00007000L 1042//THM_PWRMGT 1043#define THM_PWRMGT__CLK_GATE_EN__SHIFT 0x0 1044#define THM_PWRMGT__CLK_GATE_ST__SHIFT 0x1 1045#define THM_PWRMGT__PUMP_CTL_GATE_EN__SHIFT 0x6 1046#define THM_PWRMGT__FAN_CTL_GATE_EN__SHIFT 0x7 1047#define THM_PWRMGT__CLK_GATE_MAX_CNT__SHIFT 0x8 1048#define THM_PWRMGT__PROTOTYPE_TSEN_CLK_TOGGLE_EN__SHIFT 0x18 1049#define THM_PWRMGT__CLK_GATE_EN_MASK 0x00000001L 1050#define THM_PWRMGT__CLK_GATE_ST_MASK 0x00000002L 1051#define THM_PWRMGT__PUMP_CTL_GATE_EN_MASK 0x00000040L 1052#define THM_PWRMGT__FAN_CTL_GATE_EN_MASK 0x00000080L 1053#define THM_PWRMGT__CLK_GATE_MAX_CNT_MASK 0x00FFFF00L 1054#define THM_PWRMGT__PROTOTYPE_TSEN_CLK_TOGGLE_EN_MASK 0x01000000L 1055//THM_GPIO_MACO_EN_CTRL 1056#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL__SHIFT 0x0 1057#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD__SHIFT 0x1 1058#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU__SHIFT 0x2 1059#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN__SHIFT 0x3 1060#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0__SHIFT 0x4 1061#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1__SHIFT 0x5 1062#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN__SHIFT 0x6 1063#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0__SHIFT 0x7 1064#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1__SHIFT 0x8 1065#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE__SHIFT 0x10 1066#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE__SHIFT 0x11 1067#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE__SHIFT 0x12 1068#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A__SHIFT 0x13 1069#define THM_GPIO_MACO_EN_CTRL__Y__SHIFT 0x1f 1070#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL_MASK 0x00000001L 1071#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD_MASK 0x00000002L 1072#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU_MASK 0x00000004L 1073#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN_MASK 0x00000008L 1074#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0_MASK 0x00000010L 1075#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1_MASK 0x00000020L 1076#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN_MASK 0x00000040L 1077#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0_MASK 0x00000080L 1078#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1_MASK 0x00000100L 1079#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE_MASK 0x00010000L 1080#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_MASK 0x00020000L 1081#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE_MASK 0x00040000L 1082#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_MASK 0x00080000L 1083#define THM_GPIO_MACO_EN_CTRL__Y_MASK 0x80000000L 1084//SBTSI_REMOTE_TEMP 1085#define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0 1086#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb 1087#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13 1088#define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL 1089#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L 1090#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L 1091//SBRMI_CONTROL 1092#define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0 1093#define SBRMI_CONTROL__DPD__SHIFT 0x1 1094#define SBRMI_CONTROL__DbrdySts__SHIFT 0x2 1095#define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L 1096#define SBRMI_CONTROL__DPD_MASK 0x00000002L 1097#define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L 1098//SBRMI_COMMAND 1099#define SBRMI_COMMAND__Command__SHIFT 0x0 1100#define SBRMI_COMMAND__WrDataLen__SHIFT 0x8 1101#define SBRMI_COMMAND__RdDataLen__SHIFT 0x10 1102#define SBRMI_COMMAND__CommandSent__SHIFT 0x18 1103#define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19 1104#define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a 1105#define SBRMI_COMMAND__Status__SHIFT 0x1c 1106#define SBRMI_COMMAND__Command_MASK 0x000000FFL 1107#define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L 1108#define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L 1109#define SBRMI_COMMAND__CommandSent_MASK 0x01000000L 1110#define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L 1111#define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L 1112#define SBRMI_COMMAND__Status_MASK 0xF0000000L 1113//SBRMI_WRITE_DATA0 1114#define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0 1115#define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8 1116#define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10 1117#define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18 1118#define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL 1119#define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L 1120#define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L 1121#define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L 1122//SBRMI_WRITE_DATA1 1123#define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0 1124#define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8 1125#define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10 1126#define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18 1127#define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL 1128#define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L 1129#define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L 1130#define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L 1131//SBRMI_WRITE_DATA2 1132#define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0 1133#define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8 1134#define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10 1135#define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18 1136#define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL 1137#define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L 1138#define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L 1139#define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L 1140//SBRMI_READ_DATA0 1141#define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0 1142#define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8 1143#define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10 1144#define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18 1145#define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL 1146#define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L 1147#define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L 1148#define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L 1149//SBRMI_READ_DATA1 1150#define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0 1151#define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8 1152#define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10 1153#define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18 1154#define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL 1155#define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L 1156#define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L 1157#define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L 1158//SBRMI_CORE_EN_NUMBER 1159#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0 1160#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL 1161//SBRMI_CORE_EN_STATUS0 1162#define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0 1163#define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL 1164//SBRMI_CORE_EN_STATUS1 1165#define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0 1166#define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL 1167//SBRMI_APIC_STATUS0 1168#define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0 1169#define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL 1170//SBRMI_APIC_STATUS1 1171#define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0 1172#define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL 1173//SBRMI_MCE_STATUS0 1174#define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0 1175#define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL 1176//SBRMI_MCE_STATUS1 1177#define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0 1178#define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL 1179//SMBUS_CNTL0 1180#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0 1181#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1 1182#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8 1183#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10 1184#define SMBUS_CNTL0__THM_READY__SHIFT 0x14 1185#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L 1186#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL 1187#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L 1188#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L 1189#define SMBUS_CNTL0__THM_READY_MASK 0x00100000L 1190//SMBUS_CNTL1 1191#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0 1192#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1 1193#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9 1194#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L 1195#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL 1196#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L 1197//SMBUS_BLKWR_CMD_CTRL0 1198#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0 1199#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8 1200#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10 1201#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18 1202#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL 1203#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L 1204#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L 1205#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L 1206//SMBUS_BLKWR_CMD_CTRL1 1207#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0 1208#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8 1209#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10 1210#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18 1211#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL 1212#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L 1213#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L 1214#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L 1215//SMBUS_BLKRD_CMD_CTRL0 1216#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0 1217#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8 1218#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10 1219#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18 1220#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL 1221#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L 1222#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L 1223#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L 1224//SMBUS_BLKRD_CMD_CTRL1 1225#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0 1226#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8 1227#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10 1228#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18 1229#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL 1230#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L 1231#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L 1232#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L 1233//SMBUS_TIMING_CNTL0 1234#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0 1235#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16 1236#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL 1237#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L 1238//SMBUS_TIMING_CNTL1 1239#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0 1240#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5 1241#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb 1242#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14 1243#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL 1244#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L 1245#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L 1246#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L 1247//SMBUS_TIMING_CNTL2 1248#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0 1249#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd 1250#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL 1251#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L 1252//SMBUS_TRIGGER_CNTL 1253#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0 1254#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8 1255#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L 1256#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L 1257//SMBUS_UDID_CNTL0 1258#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0 1259#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f 1260#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL 1261#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L 1262//SMBUS_UDID_CNTL1 1263#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0 1264#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL 1265//SMBUS_UDID_CNTL2 1266#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0 1267#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1 1268#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4 1269#define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8 1270#define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9 1271#define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa 1272#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L 1273#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL 1274#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L 1275#define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L 1276#define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L 1277#define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L 1278//THM_TMON0_REMOTE_START 1279#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 1280#define THM_TMON0_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1281//THM_TMON0_REMOTE_END 1282#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 1283#define THM_TMON0_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1284//THM_TMON1_REMOTE_START 1285#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 1286#define THM_TMON1_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1287//THM_TMON1_REMOTE_END 1288#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 1289#define THM_TMON1_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1290//THM_TMON2_REMOTE_START 1291#define THM_TMON2_REMOTE_START__DATA__SHIFT 0x0 1292#define THM_TMON2_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1293//THM_TMON2_REMOTE_END 1294#define THM_TMON2_REMOTE_END__DATA__SHIFT 0x0 1295#define THM_TMON2_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1296 1297#endif 1298