1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _mmhub_3_0_2_SH_MASK_HEADER 24#define _mmhub_3_0_2_SH_MASK_HEADER 25 26 27// addressBlock: mmhub_dagbdec 28//DAGB0_RDCLI0 29#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 30#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 32#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 33#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 35#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 36#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 37#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 39#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 40#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 41#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 42#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 43#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 44#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 45#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 46#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 47#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 48#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 49//DAGB0_RDCLI1 50#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 51#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 52#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 53#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 54#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 55#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 56#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 57#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 58#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 59#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 60#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 61#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 62#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 63#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 64#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 65#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 66#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 67#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 68#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 69#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 70//DAGB0_RDCLI2 71#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 72#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 73#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 74#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 75#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 76#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 77#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 78#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 79#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 80#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 81#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 82#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 83#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 84#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 85#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 86#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 87#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 88#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 89#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 90#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 91//DAGB0_RDCLI3 92#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 93#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 94#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 95#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 96#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 97#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 98#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 99#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 100#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 101#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 102#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 103#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 104#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 105#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 106#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 107#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 108#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 109#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 110#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 111#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 112//DAGB0_RDCLI4 113#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 114#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 115#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 116#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 117#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 118#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 119#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 120#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 121#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 123#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 124#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 125#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 126#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 127#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 128#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 129#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 130#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 131#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 132#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 133//DAGB0_RDCLI5 134#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 135#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 136#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 137#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 138#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 139#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 140#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 141#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 142#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 143#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 144#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 145#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 146#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 147#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 148#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 149#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 150#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 151#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 152#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 153#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 154//DAGB0_RDCLI6 155#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 156#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 157#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 158#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 159#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 160#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 161#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 162#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 163#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 164#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 165#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 166#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 167#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 168#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 169#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 170#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 171#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 172#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 173#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 174#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 175//DAGB0_RDCLI7 176#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 177#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 178#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 179#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 180#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 181#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 182#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 183#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 184#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 185#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 186#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 187#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 188#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 189#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 190#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 191#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 192#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 193#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 194#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 195#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 196//DAGB0_RDCLI8 197#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 198#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 199#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 200#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 201#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 202#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 203#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 204#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 205#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 206#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 207#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 208#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 209#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 210#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 211#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 212#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 213#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 214#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 215#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 216#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 217//DAGB0_RDCLI9 218#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 219#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 220#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 221#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 222#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 223#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 224#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 225#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 226#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 227#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 228#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 229#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 230#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 231#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 232#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 233#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 234#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 235#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 236#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 237#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 238//DAGB0_RDCLI10 239#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 240#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 241#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 242#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 243#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 244#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 245#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 246#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 247#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 248#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 249#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 250#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 251#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 252#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 253#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 254#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 255#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 256#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 257#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 258#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 259//DAGB0_RDCLI11 260#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 261#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 262#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 263#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 264#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 265#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 266#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 267#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 268#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 269#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 270#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 271#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 272#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 273#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 274#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 275#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 276#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 277#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 278#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 279#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 280//DAGB0_RDCLI12 281#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 282#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 283#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 284#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 285#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 286#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 287#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 288#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 289#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 290#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 291#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 292#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 293#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 294#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 295#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 296#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 297#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 298#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 299#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 300#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 301//DAGB0_RDCLI13 302#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 303#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 304#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 305#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 306#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 307#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 308#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 309#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 310#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 311#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 312#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 313#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 314#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 315#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 316#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 317#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 318#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 319#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 320#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 321#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 322//DAGB0_RDCLI14 323#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 324#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 325#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 326#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 327#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 328#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 329#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 330#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 331#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 332#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 333#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 334#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 335#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 336#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 337#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 338#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 339#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 340#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 341#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 342#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 343//DAGB0_RDCLI15 344#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 345#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 346#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 347#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 348#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 349#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 350#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 351#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 352#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 353#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 354#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 355#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 356#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 357#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 358#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 359#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 360#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 361#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 362#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 363#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 364//DAGB0_RDCLI16 365#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 366#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 367#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 368#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 369#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 370#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 371#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 372#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 373#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 374#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 375#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 376#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 377#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 378#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 379#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 380#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 381#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 382#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 383#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 384#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 385//DAGB0_RDCLI17 386#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 387#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 388#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 389#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 390#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 391#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 392#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 393#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 394#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 395#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 396#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 397#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 398#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 399#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 400#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 401#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 402#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 403#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 404#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 405#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 406//DAGB0_RDCLI18 407#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 408#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 409#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 410#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 411#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 412#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 413#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 414#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 415#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 416#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 417#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 418#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 419#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 420#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 421#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 422#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 423#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 424#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 425#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 426#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 427//DAGB0_RDCLI19 428#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 429#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 430#define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 431#define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 432#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 433#define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd 434#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 435#define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 436#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 437#define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a 438#define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L 439#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 440#define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L 441#define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L 442#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 443#define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L 444#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 445#define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L 446#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 447#define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L 448//DAGB0_RDCLI20 449#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 450#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 451#define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 452#define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 453#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 454#define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd 455#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 456#define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 457#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 458#define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a 459#define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L 460#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 461#define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L 462#define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L 463#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 464#define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L 465#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 466#define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L 467#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 468#define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L 469//DAGB0_RDCLI21 470#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 471#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 472#define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 473#define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 474#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 475#define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd 476#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 477#define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 478#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 479#define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a 480#define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L 481#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 482#define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L 483#define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L 484#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 485#define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L 486#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 487#define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L 488#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 489#define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L 490//DAGB0_RDCLI22 491#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 492#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 493#define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 494#define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 495#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 496#define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd 497#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 498#define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 499#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 500#define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a 501#define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L 502#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 503#define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L 504#define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L 505#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 506#define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L 507#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 508#define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L 509#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 510#define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L 511//DAGB0_RDCLI23 512#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 513#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 514#define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 515#define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 516#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 517#define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd 518#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 519#define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 520#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 521#define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a 522#define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L 523#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 524#define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L 525#define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L 526#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 527#define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L 528#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 529#define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L 530#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 531#define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L 532//DAGB0_RD_CNTL 533#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 534#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 535#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc 536#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf 537#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 538#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 539#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L 540#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L 541//DAGB0_RD_IO_CNTL 542#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 543#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 544#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 545#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 546#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 547#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 548#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 549#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 550#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 551#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 552#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 553#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 554#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 555#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 556//DAGB0_RD_GMI_CNTL 557#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 558#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 559#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 560#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 561#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 562#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 563#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 564#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 565#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 566#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 567#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 568#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 569#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 570#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 571//DAGB0_RD_ADDR_DAGB 572#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 573#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 574#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 575#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 576#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 577#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 578#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 579#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 580#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 581#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 582//DAGB0_RD_CGTT_CLK_CTRL 583#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 584#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 585#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 586#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 587#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 588#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 589#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 590#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 591#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 592#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 593//DAGB0_L1TLB_RD_CGTT_CLK_CTRL 594#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 595#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 596#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 597#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 598#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 599#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 600#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 601#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 602#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 603#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 604//DAGB0_RD_ADDR_DAGB_MAX_BURST0 605#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 606#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 607#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 608#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 609#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 610#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 611#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 612#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 613#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 614#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 615#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 616#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 617#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 618#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 619#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 620#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 621//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 622#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 623#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 624#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 625#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 626#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 627#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 628#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 629#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 630#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 631#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 632#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 633#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 634#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 635#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 636#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 637#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 638//DAGB0_RD_ADDR_DAGB_MAX_BURST1 639#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 640#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 641#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 642#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 643#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 644#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 645#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 646#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 647#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 648#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 649#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 650#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 651#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 652#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 653#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 654#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 655//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 656#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 657#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 658#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 659#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 660#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 661#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 662#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 663#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 664#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 665#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 666#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 667#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 668#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 669#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 670#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 671#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 672//DAGB0_RD_ADDR_DAGB_MAX_BURST2 673#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 674#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 675#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 676#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 677#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 678#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 679#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 680#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 681#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 682#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 683#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 684#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 685#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 686#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 687#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 688#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 689//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 690#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 691#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 692#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 693#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 694#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 695#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 696#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 697#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 698#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 699#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 700#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 701#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 702#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 703#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 704#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 705#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 706//DAGB0_RD_VC0_CNTL 707#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 708#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 709#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 710#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 711#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 712#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 713#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 714#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 715#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 716#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 717#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 718#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 719#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 720#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 721//DAGB0_RD_VC1_CNTL 722#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 723#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 724#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 725#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 726#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 727#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 728#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 729#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 730#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 731#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 732#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 733#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 734#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 735#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 736//DAGB0_RD_VC2_CNTL 737#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 738#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 739#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 740#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 741#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 742#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 743#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 744#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 745#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 746#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 747#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 748#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 749#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 750#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 751//DAGB0_RD_VC3_CNTL 752#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 753#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 754#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 755#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 756#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 757#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 758#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 759#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 760#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 761#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 762#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 763#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 764#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 765#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 766//DAGB0_RD_VC4_CNTL 767#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 768#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 769#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 770#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 771#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 772#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 773#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 774#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 775#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 776#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 777#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 778#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 779#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 780#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 781//DAGB0_RD_VC5_CNTL 782#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 783#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 784#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 785#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 786#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 787#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 788#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 789#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 790#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 791#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 792#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 793#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 794#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 795#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 796//DAGB0_RD_IO_VC_CNTL 797#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 798#define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc 799#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 800#define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 801#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 802#define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 803#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 804#define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 805#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 806#define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 807#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 808#define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 809//DAGB0_RD_GMI_VC_CNTL 810#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 811#define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 812#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 813#define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 814#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 815#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 816#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 817#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 818#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 819#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 820#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 821#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 822//DAGB0_RD_CNTL_MISC 823#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 824#define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 825#define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 826#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 827#define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L 828#define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L 829//DAGB0_RD_TLB_CREDIT 830#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 831#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 832#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 833#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 834#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 835#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 836#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 837#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 838#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 839#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 840#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 841#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 842//DAGB0_RD_RDRET_CREDIT_CNTL 843#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 844#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x5 845#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xa 846#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0xf 847#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x14 848#define DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT 0x19 849#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 850#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 851#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000001FL 852#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x000003E0L 853#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x00007C00L 854#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x000F8000L 855#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x01F00000L 856#define DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK 0x3E000000L 857#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 858#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 859//DAGB0_RD_RDRET_CREDIT_CNTL2 860#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0x0 861#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0000003FL 862//DAGB0_RDCLI_ASK_PENDING 863#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 864#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 865//DAGB0_RDCLI_GO_PENDING 866#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 867#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 868//DAGB0_RDCLI_GBLSEND_PENDING 869#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 870#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 871//DAGB0_RDCLI_TLB_PENDING 872#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 873#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 874//DAGB0_RDCLI_OARB_PENDING 875#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 876#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 877//DAGB0_RDCLI_ASK2ARB_PENDING 878#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 879#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 880//DAGB0_RDCLI_ASK2DF_PENDING 881#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 882#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 883//DAGB0_RDCLI_OSD_PENDING 884#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 885#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 886//DAGB0_RDCLI_ASK_OSD_PENDING 887#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 888#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 889//DAGB0_RDCLI_NOALLOC_OVERRIDE 890#define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 891#define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 892//DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE 893#define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 894#define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL 895//DAGB0_WRCLI0 896#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 897#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 898#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 899#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 900#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 901#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 902#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 903#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 904#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 905#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 906#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 907#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 908#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 909#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 910#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 911#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 912#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 913#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 914#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 915#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 916//DAGB0_WRCLI1 917#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 918#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 919#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 920#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 921#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 922#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 923#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 924#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 925#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 926#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 927#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 928#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 929#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 930#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 931#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 932#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 933#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 934#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 935#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 936#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 937//DAGB0_WRCLI2 938#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 939#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 940#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 941#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 942#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 943#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 944#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 945#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 946#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 947#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 948#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 949#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 950#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 951#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 952#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 953#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 954#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 955#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 956#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 957#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 958//DAGB0_WRCLI3 959#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 960#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 961#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 962#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 963#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 964#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 965#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 966#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 967#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 968#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 969#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 970#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 971#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 972#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 973#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 974#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 975#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 976#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 977#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 978#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 979//DAGB0_WRCLI4 980#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 981#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 982#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 983#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 984#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 985#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 986#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 987#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 988#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 989#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 990#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 991#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 992#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 993#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 994#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 995#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 996#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 997#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 998#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 999#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 1000//DAGB0_WRCLI5 1001#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 1002#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1003#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 1004#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 1005#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 1006#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 1007#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 1008#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 1009#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1010#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 1011#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 1012#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1013#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 1014#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 1015#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1016#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 1017#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1018#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 1019#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1020#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 1021//DAGB0_WRCLI6 1022#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 1023#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1024#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 1025#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 1026#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 1027#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 1028#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 1029#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 1030#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1031#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 1032#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 1033#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1034#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 1035#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 1036#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1037#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 1038#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1039#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 1040#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1041#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 1042//DAGB0_WRCLI7 1043#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 1044#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1045#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 1046#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 1047#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 1048#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 1049#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 1050#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 1051#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1052#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 1053#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 1054#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1055#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 1056#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 1057#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1058#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 1059#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1060#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 1061#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1062#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 1063//DAGB0_WRCLI8 1064#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 1065#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1066#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 1067#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 1068#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 1069#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 1070#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 1071#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 1072#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1073#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 1074#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 1075#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1076#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 1077#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 1078#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1079#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 1080#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1081#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 1082#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1083#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 1084//DAGB0_WRCLI9 1085#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 1086#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1087#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 1088#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 1089#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 1090#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 1091#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 1092#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 1093#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1094#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 1095#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 1096#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1097#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 1098#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 1099#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1100#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 1101#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1102#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 1103#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1104#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 1105//DAGB0_WRCLI10 1106#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 1107#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1108#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 1109#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 1110#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 1111#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 1112#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 1113#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 1114#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1115#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 1116#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 1117#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1118#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 1119#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 1120#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1121#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 1122#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1123#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 1124#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1125#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 1126//DAGB0_WRCLI11 1127#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 1128#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1129#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 1130#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 1131#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 1132#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 1133#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 1134#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 1135#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1136#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1137#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1138#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1139#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1140#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1141#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1142#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1143#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1144#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1145#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1146#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1147//DAGB0_WRCLI12 1148#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1149#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1150#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1151#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1152#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1153#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1154#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1155#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1156#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1157#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1158#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1159#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1160#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1161#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1162#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1163#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1164#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1165#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1166#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1167#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1168//DAGB0_WRCLI13 1169#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1170#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1171#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1172#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1173#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1174#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1175#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1176#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1177#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1178#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1179#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1180#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1181#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1182#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1183#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1184#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1185#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1186#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1187#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1188#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1189//DAGB0_WRCLI14 1190#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1191#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1192#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1193#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1194#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1195#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1196#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1197#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1198#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1199#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1200#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1201#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1202#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1203#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1204#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1205#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1206#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1207#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1208#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1209#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1210//DAGB0_WRCLI15 1211#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1212#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1213#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1214#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1215#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1216#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1217#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1218#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1219#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1220#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1221#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1222#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1223#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1224#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1225#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1226#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1227#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1228#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1229#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1230#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1231//DAGB0_WRCLI16 1232#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 1233#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 1234#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 1235#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 1236#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 1237#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 1238#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 1239#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 1240#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 1241#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 1242#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 1243#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 1244#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 1245#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 1246#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 1247#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 1248#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 1249#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 1250#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 1251#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 1252//DAGB0_WRCLI17 1253#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 1254#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 1255#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 1256#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 1257#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 1258#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 1259#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 1260#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 1261#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 1262#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 1263#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 1264#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 1265#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 1266#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 1267#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 1268#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 1269#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 1270#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 1271#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 1272#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 1273//DAGB0_WRCLI18 1274#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 1275#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 1276#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 1277#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 1278#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 1279#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 1280#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 1281#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 1282#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 1283#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 1284#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 1285#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 1286#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 1287#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 1288#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 1289#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 1290#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 1291#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 1292#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 1293#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 1294//DAGB0_WRCLI19 1295#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 1296#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 1297#define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 1298#define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 1299#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc 1300#define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd 1301#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 1302#define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 1303#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 1304#define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a 1305#define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L 1306#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 1307#define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L 1308#define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L 1309#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L 1310#define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L 1311#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L 1312#define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L 1313#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 1314#define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L 1315//DAGB0_WRCLI20 1316#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 1317#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 1318#define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 1319#define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 1320#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc 1321#define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd 1322#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 1323#define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 1324#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 1325#define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a 1326#define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L 1327#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 1328#define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L 1329#define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L 1330#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L 1331#define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L 1332#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L 1333#define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L 1334#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 1335#define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L 1336//DAGB0_WRCLI21 1337#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 1338#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 1339#define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 1340#define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 1341#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc 1342#define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd 1343#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 1344#define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 1345#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 1346#define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a 1347#define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L 1348#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 1349#define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L 1350#define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L 1351#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L 1352#define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L 1353#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L 1354#define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L 1355#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 1356#define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L 1357//DAGB0_WRCLI22 1358#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 1359#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 1360#define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 1361#define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 1362#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc 1363#define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd 1364#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 1365#define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 1366#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 1367#define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a 1368#define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L 1369#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 1370#define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L 1371#define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L 1372#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L 1373#define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L 1374#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L 1375#define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L 1376#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 1377#define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L 1378//DAGB0_WRCLI23 1379#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 1380#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 1381#define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 1382#define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 1383#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc 1384#define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd 1385#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 1386#define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 1387#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 1388#define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a 1389#define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L 1390#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 1391#define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L 1392#define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L 1393#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L 1394#define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L 1395#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L 1396#define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L 1397#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 1398#define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L 1399//DAGB0_WR_CNTL 1400#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 1401#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 1402#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xc 1403#define DAGB0_WR_CNTL__UPDATE_FED__SHIFT 0xd 1404#define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT 0xe 1405#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 1406#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 1407#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK 0x00001000L 1408#define DAGB0_WR_CNTL__UPDATE_FED_MASK 0x00002000L 1409#define DAGB0_WR_CNTL__UPDATE_NACK_MASK 0x00004000L 1410//DAGB0_WR_IO_CNTL 1411#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1412#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1413#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1414#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1415#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1416#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1417#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 1418#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1419#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1420#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1421#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1422#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1423#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1424#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1425//DAGB0_WR_GMI_CNTL 1426#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1427#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1428#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1429#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1430#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1431#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1432#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 1433#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1434#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1435#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1436#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1437#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1438#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1439#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1440//DAGB0_WR_ADDR_DAGB 1441#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1442#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1443#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1444#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1445#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 1446#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1447#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1448#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1449#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1450#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 1451//DAGB0_WR_CGTT_CLK_CTRL 1452#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1453#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1454#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1455#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1456#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1457#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1458#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1459#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 1460#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1461#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1462//DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1463#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1464#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1465#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1466#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1467#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1468#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1469#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1470#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 1471#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1472#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1473//DAGB0_WR_ADDR_DAGB_MAX_BURST0 1474#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1475#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1476#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1477#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1478#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1479#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1480#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1481#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1482#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1483#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1484#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1485#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1486#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1487#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1488#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1489#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1490//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1491#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1492#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1493#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1494#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1495#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1496#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1497#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1498#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1499#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1500#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1501#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1502#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1503#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1504#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1505#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1506#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1507//DAGB0_WR_ADDR_DAGB_MAX_BURST1 1508#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1509#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1510#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1511#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1512#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1513#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1514#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1515#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1516#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1517#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1518#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1519#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1520#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1521#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1522#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1523#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1524//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1525#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1526#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1527#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1528#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1529#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1530#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1531#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1532#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1533#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1534#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1535#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1536#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1537#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1538#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1539#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1540#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1541//DAGB0_WR_ADDR_DAGB_MAX_BURST2 1542#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1543#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1544#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1545#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1546#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1547#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1548#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1549#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1550#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1551#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1552#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1553#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1554#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1555#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1556#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1557#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1558//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 1559#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1560#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1561#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1562#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1563#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1564#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1565#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1566#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1567#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1568#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1569#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1570#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1571#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1572#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1573#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1574#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1575//DAGB0_WR_DATA_DAGB 1576#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1577#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1578#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1579#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1580#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1581#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1582#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1583#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1584//DAGB0_WR_DATA_DAGB_MAX_BURST0 1585#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1586#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1587#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1588#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1589#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1590#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1591#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1592#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1593#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1594#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1595#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1596#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1597#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1598#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1599#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1600#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1601//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1602#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1603#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1604#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1605#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1606#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1607#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1608#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1609#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1610#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1611#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1612#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1613#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1614#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1615#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1616#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1617#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1618//DAGB0_WR_DATA_DAGB_MAX_BURST1 1619#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1620#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1621#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1622#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1623#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1624#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1625#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1626#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1627#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1628#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1629#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1630#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1631#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1632#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1633#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1634#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1635//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1636#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1637#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1638#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1639#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1640#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1641#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1642#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1643#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1644#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1645#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1646#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1647#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1648#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1649#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1650#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1651#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1652//DAGB0_WR_DATA_DAGB_MAX_BURST2 1653#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1654#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1655#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1656#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1657#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1658#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1659#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1660#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1661#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1662#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1663#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1664#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1665#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1666#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1667#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1668#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1669//DAGB0_WR_DATA_DAGB_LAZY_TIMER2 1670#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1671#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1672#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1673#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1674#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1675#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1676#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1677#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1678#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1679#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1680#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1681#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1682#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1683#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1684#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1685#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1686//DAGB0_WR_VC0_CNTL 1687#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 1688#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1689#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 1690#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1691#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 1692#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1693#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 1694#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 1695#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1696#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 1697#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1698#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 1699#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1700#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 1701//DAGB0_WR_VC1_CNTL 1702#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 1703#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1704#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 1705#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1706#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 1707#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1708#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 1709#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 1710#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1711#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 1712#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1713#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 1714#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1715#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 1716//DAGB0_WR_VC2_CNTL 1717#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 1718#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1719#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 1720#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1721#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 1722#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1723#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 1724#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 1725#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1726#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1727#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1728#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1729#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1730#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1731//DAGB0_WR_VC3_CNTL 1732#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1733#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1734#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 1735#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1736#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 1737#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1738#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 1739#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1740#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1741#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1742#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1743#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1744#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1745#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1746//DAGB0_WR_VC4_CNTL 1747#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1748#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1749#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 1750#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1751#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 1752#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1753#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 1754#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1755#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1756#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1757#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1758#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1759#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1760#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1761//DAGB0_WR_VC5_CNTL 1762#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1763#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1764#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 1765#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1766#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 1767#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1768#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 1769#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1770#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1771#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1772#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1773#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1774#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1775#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1776//DAGB0_WR_IO_VC_CNTL 1777#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 1778#define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT 0xc 1779#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1780#define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT 0x15 1781#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1782#define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 1783#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 1784#define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 1785#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1786#define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 1787#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1788#define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 1789//DAGB0_WR_GMI_VC_CNTL 1790#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 1791#define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 1792#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1793#define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 1794#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1795#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 1796#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 1797#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 1798#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1799#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 1800#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1801#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 1802//DAGB0_WR_CNTL_MISC 1803#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1804#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x6 1805#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1806#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L 1807//DAGB0_WR_TLB_CREDIT 1808#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 1809#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 1810#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1811#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 1812#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 1813#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 1814#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 1815#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 1816#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 1817#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 1818#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 1819#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 1820//DAGB0_WR_DATA_CREDIT 1821#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 1822#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 1823#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 1824#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 1825#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 1826#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 1827#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 1828#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 1829//DAGB0_WR_MISC_CREDIT 1830#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 1831#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 1832#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 1833#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 1834//DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 1835#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 1836#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 1837#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 1838#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 1839#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 1840#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 1841#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 1842#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 1843#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 1844#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 1845#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 1846#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 1847#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 1848#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 1849#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 1850#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 1851//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 1852#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 1853#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 1854#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 1855#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 1856#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 1857#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x1a 1858#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1b 1859#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1c 1860#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 1861#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 1862#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 1863#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 1864#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L 1865#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x04000000L 1866#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x08000000L 1867#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x10000000L 1868//DAGB0_WRCLI_ASK_PENDING 1869#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 1870#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1871//DAGB0_WRCLI_GO_PENDING 1872#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 1873#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1874//DAGB0_WRCLI_GBLSEND_PENDING 1875#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1876#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1877//DAGB0_WRCLI_TLB_PENDING 1878#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 1879#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1880//DAGB0_WRCLI_OARB_PENDING 1881#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 1882#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1883//DAGB0_WRCLI_ASK2ARB_PENDING 1884#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 1885#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1886//DAGB0_WRCLI_ASK2DF_PENDING 1887#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 1888#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 1889//DAGB0_WRCLI_OSD_PENDING 1890#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 1891#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1892//DAGB0_WRCLI_ASK_OSD_PENDING 1893#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 1894#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1895//DAGB0_WRCLI_DBUS_ASK_PENDING 1896#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 1897#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1898//DAGB0_WRCLI_DBUS_GO_PENDING 1899#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 1900#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1901//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE 1902#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 1903#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 1904//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 1905#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 1906#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 1907//DAGB0_WRCLI_NOALLOC_OVERRIDE 1908#define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 1909#define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 1910//DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE 1911#define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 1912#define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL 1913//DAGB0_DAGB_DLY 1914#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 1915#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 1916#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 1917#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 1918#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 1919#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 1920//DAGB0_CNTL_MISC 1921#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 1922#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL 1923//DAGB0_CNTL_MISC2 1924#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 1925#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 1926#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 1927#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 1928#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 1929#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 1930#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 1931#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 1932#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 1933#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 1934#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa 1935#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb 1936#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L 1937#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L 1938#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L 1939#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L 1940#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L 1941#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L 1942#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L 1943#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L 1944#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L 1945#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L 1946#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L 1947#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L 1948//DAGB0_FIFO_EMPTY 1949#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 1950#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL 1951//DAGB0_FIFO_FULL 1952#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 1953#define DAGB0_FIFO_FULL__FULL_MASK 0x0000FFFFL 1954//DAGB0_RD_CREDITS_FULL 1955#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 1956#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL 1957//DAGB0_WR_CREDITS_FULL 1958#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 1959#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL 1960//DAGB0_PERFCOUNTER_LO 1961#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1962#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1963//DAGB0_PERFCOUNTER_HI 1964#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1965#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1966#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1967#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1968//DAGB0_PERFCOUNTER0_CFG 1969#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1970#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1971#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1972#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1973#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1974#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1975#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1976#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1977#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1978#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1979//DAGB0_PERFCOUNTER1_CFG 1980#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1981#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1982#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1983#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1984#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1985#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1986#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1987#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1988#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1989#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1990//DAGB0_PERFCOUNTER2_CFG 1991#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1992#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1993#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1994#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1995#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1996#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1997#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1998#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1999#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 2000#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 2001//DAGB0_PERFCOUNTER_RSLT_CNTL 2002#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 2003#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 2004#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 2005#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 2006#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 2007#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 2008#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 2009#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 2010#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 2011#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 2012#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 2013#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 2014//DAGB0_L1TLB_REG_RW 2015#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 2016#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 2017#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x2 2018#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 2019#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 2020#define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL 2021//DAGB0_RESERVE1 2022#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 2023#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 2024//DAGB0_RESERVE2 2025#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 2026#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 2027//DAGB0_RESERVE3 2028#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 2029#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 2030//DAGB0_RESERVE4 2031#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 2032#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 2033//DAGB0_SDP_RD_BW_CNTL 2034#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 2035#define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 2036#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 2037#define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa 2038#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd 2039#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 2040#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL 2041#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L 2042#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L 2043#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L 2044//DAGB0_SDP_PRIORITY_OVERRIDE 2045#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 2046#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2047#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 2048#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa 2049#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb 2050#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc 2051#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd 2052#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe 2053#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 2054#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 2055#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 2056#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a 2057#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b 2058#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c 2059#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d 2060#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e 2061#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL 2062#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2063#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L 2064#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L 2065#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L 2066#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L 2067#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L 2068#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L 2069#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L 2070#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L 2071#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L 2072#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L 2073#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L 2074#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L 2075#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L 2076#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L 2077//DAGB0_SDP_RD_PRIORITY 2078#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 2079#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 2080#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 2081#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc 2082#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 2083#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 2084#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL 2085#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L 2086#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L 2087#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L 2088#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L 2089#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L 2090//DAGB0_SDP_WR_PRIORITY 2091#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT 0x0 2092#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT 0x4 2093#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT 0x8 2094#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT 0xc 2095#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT 0x10 2096#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT 0x14 2097#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK 0x0000000FL 2098#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK 0x000000F0L 2099#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK 0x00000F00L 2100#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK 0x0000F000L 2101#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK 0x000F0000L 2102#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK 0x00F00000L 2103//DAGB0_SDP_RD_CLI2SDP_VC_MAP 2104#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2105#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2106#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2107#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2108#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2109#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2110#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2111#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2112#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2113#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2114#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2115#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2116//DAGB0_SDP_WR_CLI2SDP_VC_MAP 2117#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2118#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2119#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2120#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2121#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2122#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2123#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2124#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2125#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2126#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2127#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2128#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2129//DAGB0_SDP_ENABLE 2130#define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0 2131#define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L 2132//DAGB0_SDP_CREDITS 2133#define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 2134#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 2135#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 2136#define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 2137#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 2138#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L 2139//DAGB0_SDP_TAG_RESERVE0 2140#define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 2141#define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 2142#define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 2143#define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 2144#define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 2145#define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 2146#define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 2147#define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 2148//DAGB0_SDP_TAG_RESERVE1 2149#define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 2150#define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 2151#define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 2152#define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 2153#define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 2154#define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 2155#define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 2156#define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 2157//DAGB0_SDP_VCC_RESERVE0 2158#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 2159#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 2160#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 2161#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 2162#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 2163#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2164#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2165#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2166#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2167#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2168//DAGB0_SDP_VCC_RESERVE1 2169#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 2170#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 2171#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 2172#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 2173#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2174#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2175#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2176#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 2177//DAGB0_SDP_ERR_STATUS 2178#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 2179#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 2180#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 2181#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 2182#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 2183#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 2184#define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd 2185#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 2186#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 2187#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 2188#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 2189#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 2190#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 2191#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 2192#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 2193#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 2194#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 2195#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 2196#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 2197#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 2198#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 2199#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 2200#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 2201#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 2202//DAGB0_SDP_REQ_CNTL 2203#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 2204#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 2205#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 2206#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 2207#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 2208#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 2209#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 2210#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 2211#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 2212#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 2213#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 2214#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 2215#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 2216#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 2217#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 2218#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 2219#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 2220#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 2221//DAGB0_SDP_MISC_AON 2222#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 2223#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 2224#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 2225#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 2226//DAGB0_SDP_MISC 2227#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 2228#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 2229#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 2230#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 2231#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 2232#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 2233#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 2234#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 2235#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 2236#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 2237#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb 2238#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd 2239#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf 2240#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 2241#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 2242#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L 2243#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L 2244#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L 2245#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L 2246#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L 2247#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L 2248#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L 2249#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L 2250#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L 2251#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L 2252#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L 2253#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L 2254#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L 2255#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L 2256#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L 2257//DAGB0_SDP_MISC2 2258#define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 2259#define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 2260#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 2261#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 2262#define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L 2263#define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L 2264#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L 2265#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L 2266//DAGB0_SDP_VCD_RESERVE0 2267#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 2268#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 2269#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 2270#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 2271#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 2272#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2273#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2274#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2275#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2276#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2277//DAGB0_SDP_VCD_RESERVE1 2278#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 2279#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 2280#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 2281#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x12 2282#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2283#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2284#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2285#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x00040000L 2286//DAGB0_SDP_ARB_CNTL0 2287#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 2288#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 2289#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 2290#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 2291#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 2292#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 2293#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 2294#define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 2295#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L 2296#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L 2297#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L 2298#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L 2299#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L 2300#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L 2301#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L 2302#define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L 2303//DAGB0_SDP_ARB_CNTL1 2304#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 2305#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 2306#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 2307#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 2308#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL 2309#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L 2310#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L 2311#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L 2312//DAGB0_FATAL_ERROR_CNTL 2313#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 2314#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL 2315//DAGB0_FATAL_ERROR_CLEAR 2316#define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 2317#define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L 2318//DAGB0_FATAL_ERROR_STATUS0 2319#define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 2320#define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 2321#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 2322#define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L 2323#define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL 2324#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L 2325//DAGB0_FATAL_ERROR_STATUS1 2326#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 2327#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL 2328//DAGB0_FATAL_ERROR_STATUS2 2329#define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT 0x0 2330#define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT 0x10 2331#define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x18 2332#define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x1c 2333#define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x1d 2334#define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT 0x1e 2335#define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x1f 2336#define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK 0x0000FFFFL 2337#define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK 0x00FF0000L 2338#define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x0F000000L 2339#define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x10000000L 2340#define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK 0x20000000L 2341#define DAGB0_FATAL_ERROR_STATUS2__IO_MASK 0x40000000L 2342#define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK 0x80000000L 2343//DAGB0_FATAL_ERROR_STATUS3 2344#define DAGB0_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x0 2345#define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 2346#define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xd 2347#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 2348#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 2349#define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 2350#define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 2351#define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 2352#define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 2353#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 2354#define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT 0x18 2355#define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT 0x19 2356#define DAGB0_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000003FL 2357#define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L 2358#define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0000E000L 2359#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L 2360#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L 2361#define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L 2362#define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L 2363#define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L 2364#define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L 2365#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L 2366#define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK 0x01000000L 2367#define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK 0x02000000L 2368//DAGB0_FATAL_ERROR_STATUS4 2369#define DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT 0x0 2370#define DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT 0x4 2371#define DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT 0x5 2372#define DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT 0x6 2373#define DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE__SHIFT 0x7 2374#define DAGB0_FATAL_ERROR_STATUS4__NOALLOC__SHIFT 0x8 2375#define DAGB0_FATAL_ERROR_STATUS4__PRI_MASK 0x0000000FL 2376#define DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK 0x00000010L 2377#define DAGB0_FATAL_ERROR_STATUS4__FULL_MASK 0x00000020L 2378#define DAGB0_FATAL_ERROR_STATUS4__DROP_MASK 0x00000040L 2379#define DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE_MASK 0x00000080L 2380#define DAGB0_FATAL_ERROR_STATUS4__NOALLOC_MASK 0x00000100L 2381//DAGB0_SDP_CGTT_CLK_CTRL 2382#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2383#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2384#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2385#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2386#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2387#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2388#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2389#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 2390#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2391#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2392//DAGB0_SDP_LATENCY_SAMPLING 2393#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 2394#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 2395#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 2396#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 2397#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 2398#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 2399#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 2400#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 2401#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 2402#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 2403#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 2404#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 2405#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 2406#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 2407#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 2408#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 2409#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 2410#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 2411#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 2412#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 2413#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 2414#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 2415#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 2416#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 2417#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 2418#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 2419#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 2420#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 2421#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 2422#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 2423#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 2424#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 2425//DAGB1_RDCLI0 2426#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 2427#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 2428#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 2429#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 2430#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 2431#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd 2432#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 2433#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 2434#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 2435#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a 2436#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L 2437#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 2438#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L 2439#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L 2440#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 2441#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L 2442#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 2443#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L 2444#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 2445#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L 2446//DAGB1_RDCLI1 2447#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 2448#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 2449#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 2450#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 2451#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 2452#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd 2453#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 2454#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 2455#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 2456#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a 2457#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L 2458#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 2459#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L 2460#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L 2461#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 2462#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L 2463#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 2464#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L 2465#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 2466#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L 2467//DAGB1_RDCLI2 2468#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 2469#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 2470#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 2471#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 2472#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 2473#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd 2474#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 2475#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 2476#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 2477#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a 2478#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L 2479#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 2480#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L 2481#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L 2482#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 2483#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L 2484#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 2485#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L 2486#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 2487#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L 2488//DAGB1_RDCLI3 2489#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 2490#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 2491#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 2492#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 2493#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 2494#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd 2495#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 2496#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 2497#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 2498#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a 2499#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L 2500#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 2501#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L 2502#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L 2503#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 2504#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L 2505#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 2506#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L 2507#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 2508#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L 2509//DAGB1_RDCLI4 2510#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 2511#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 2512#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 2513#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 2514#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 2515#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd 2516#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 2517#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 2518#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 2519#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a 2520#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L 2521#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 2522#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L 2523#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L 2524#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 2525#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L 2526#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 2527#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L 2528#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 2529#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L 2530//DAGB1_RDCLI5 2531#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 2532#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 2533#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 2534#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 2535#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 2536#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd 2537#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 2538#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 2539#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 2540#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a 2541#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L 2542#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 2543#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L 2544#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L 2545#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 2546#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L 2547#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 2548#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L 2549#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 2550#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L 2551//DAGB1_RDCLI6 2552#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 2553#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 2554#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 2555#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 2556#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 2557#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd 2558#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 2559#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 2560#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 2561#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a 2562#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L 2563#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 2564#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L 2565#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L 2566#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 2567#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L 2568#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 2569#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L 2570#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 2571#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L 2572//DAGB1_RDCLI7 2573#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 2574#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 2575#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 2576#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 2577#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 2578#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd 2579#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 2580#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 2581#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 2582#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a 2583#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L 2584#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 2585#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L 2586#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L 2587#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 2588#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L 2589#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 2590#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L 2591#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 2592#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L 2593//DAGB1_RDCLI8 2594#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 2595#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 2596#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 2597#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 2598#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 2599#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd 2600#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 2601#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 2602#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 2603#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a 2604#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L 2605#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 2606#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L 2607#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L 2608#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 2609#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L 2610#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 2611#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L 2612#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 2613#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L 2614//DAGB1_RDCLI9 2615#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 2616#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 2617#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 2618#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 2619#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 2620#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd 2621#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 2622#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 2623#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 2624#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a 2625#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L 2626#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 2627#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L 2628#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L 2629#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 2630#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L 2631#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 2632#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L 2633#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 2634#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L 2635//DAGB1_RDCLI10 2636#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 2637#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 2638#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 2639#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 2640#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 2641#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd 2642#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 2643#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 2644#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 2645#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a 2646#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L 2647#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 2648#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L 2649#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L 2650#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 2651#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L 2652#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 2653#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L 2654#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 2655#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L 2656//DAGB1_RDCLI11 2657#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 2658#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 2659#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 2660#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 2661#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 2662#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd 2663#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 2664#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 2665#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 2666#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a 2667#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L 2668#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 2669#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L 2670#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L 2671#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 2672#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L 2673#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 2674#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L 2675#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 2676#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L 2677//DAGB1_RDCLI12 2678#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 2679#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 2680#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 2681#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 2682#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 2683#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd 2684#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 2685#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 2686#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 2687#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a 2688#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L 2689#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 2690#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L 2691#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L 2692#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 2693#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L 2694#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 2695#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L 2696#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 2697#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L 2698//DAGB1_RDCLI13 2699#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 2700#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 2701#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 2702#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 2703#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 2704#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd 2705#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 2706#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 2707#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 2708#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a 2709#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L 2710#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 2711#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L 2712#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L 2713#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 2714#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L 2715#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 2716#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L 2717#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 2718#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L 2719//DAGB1_RDCLI14 2720#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 2721#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 2722#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 2723#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 2724#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 2725#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd 2726#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 2727#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 2728#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2729#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a 2730#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L 2731#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2732#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L 2733#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L 2734#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2735#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L 2736#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2737#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L 2738#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2739#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L 2740//DAGB1_RDCLI15 2741#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 2742#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2743#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 2744#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 2745#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 2746#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd 2747#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 2748#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 2749#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2750#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a 2751#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L 2752#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2753#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L 2754#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L 2755#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2756#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L 2757#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2758#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L 2759#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2760#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L 2761//DAGB1_RDCLI16 2762#define DAGB1_RDCLI16__VIRT_CHAN__SHIFT 0x0 2763#define DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 2764#define DAGB1_RDCLI16__URG_HIGH__SHIFT 0x4 2765#define DAGB1_RDCLI16__URG_LOW__SHIFT 0x8 2766#define DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 2767#define DAGB1_RDCLI16__MAX_BW__SHIFT 0xd 2768#define DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 2769#define DAGB1_RDCLI16__MIN_BW__SHIFT 0x16 2770#define DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 2771#define DAGB1_RDCLI16__MAX_OSD__SHIFT 0x1a 2772#define DAGB1_RDCLI16__VIRT_CHAN_MASK 0x00000007L 2773#define DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 2774#define DAGB1_RDCLI16__URG_HIGH_MASK 0x000000F0L 2775#define DAGB1_RDCLI16__URG_LOW_MASK 0x00000F00L 2776#define DAGB1_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 2777#define DAGB1_RDCLI16__MAX_BW_MASK 0x001FE000L 2778#define DAGB1_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 2779#define DAGB1_RDCLI16__MIN_BW_MASK 0x01C00000L 2780#define DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 2781#define DAGB1_RDCLI16__MAX_OSD_MASK 0xFC000000L 2782//DAGB1_RDCLI17 2783#define DAGB1_RDCLI17__VIRT_CHAN__SHIFT 0x0 2784#define DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 2785#define DAGB1_RDCLI17__URG_HIGH__SHIFT 0x4 2786#define DAGB1_RDCLI17__URG_LOW__SHIFT 0x8 2787#define DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 2788#define DAGB1_RDCLI17__MAX_BW__SHIFT 0xd 2789#define DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 2790#define DAGB1_RDCLI17__MIN_BW__SHIFT 0x16 2791#define DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 2792#define DAGB1_RDCLI17__MAX_OSD__SHIFT 0x1a 2793#define DAGB1_RDCLI17__VIRT_CHAN_MASK 0x00000007L 2794#define DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 2795#define DAGB1_RDCLI17__URG_HIGH_MASK 0x000000F0L 2796#define DAGB1_RDCLI17__URG_LOW_MASK 0x00000F00L 2797#define DAGB1_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 2798#define DAGB1_RDCLI17__MAX_BW_MASK 0x001FE000L 2799#define DAGB1_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 2800#define DAGB1_RDCLI17__MIN_BW_MASK 0x01C00000L 2801#define DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 2802#define DAGB1_RDCLI17__MAX_OSD_MASK 0xFC000000L 2803//DAGB1_RDCLI18 2804#define DAGB1_RDCLI18__VIRT_CHAN__SHIFT 0x0 2805#define DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 2806#define DAGB1_RDCLI18__URG_HIGH__SHIFT 0x4 2807#define DAGB1_RDCLI18__URG_LOW__SHIFT 0x8 2808#define DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 2809#define DAGB1_RDCLI18__MAX_BW__SHIFT 0xd 2810#define DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 2811#define DAGB1_RDCLI18__MIN_BW__SHIFT 0x16 2812#define DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 2813#define DAGB1_RDCLI18__MAX_OSD__SHIFT 0x1a 2814#define DAGB1_RDCLI18__VIRT_CHAN_MASK 0x00000007L 2815#define DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 2816#define DAGB1_RDCLI18__URG_HIGH_MASK 0x000000F0L 2817#define DAGB1_RDCLI18__URG_LOW_MASK 0x00000F00L 2818#define DAGB1_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 2819#define DAGB1_RDCLI18__MAX_BW_MASK 0x001FE000L 2820#define DAGB1_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 2821#define DAGB1_RDCLI18__MIN_BW_MASK 0x01C00000L 2822#define DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 2823#define DAGB1_RDCLI18__MAX_OSD_MASK 0xFC000000L 2824//DAGB1_RDCLI19 2825#define DAGB1_RDCLI19__VIRT_CHAN__SHIFT 0x0 2826#define DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 2827#define DAGB1_RDCLI19__URG_HIGH__SHIFT 0x4 2828#define DAGB1_RDCLI19__URG_LOW__SHIFT 0x8 2829#define DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 2830#define DAGB1_RDCLI19__MAX_BW__SHIFT 0xd 2831#define DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 2832#define DAGB1_RDCLI19__MIN_BW__SHIFT 0x16 2833#define DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 2834#define DAGB1_RDCLI19__MAX_OSD__SHIFT 0x1a 2835#define DAGB1_RDCLI19__VIRT_CHAN_MASK 0x00000007L 2836#define DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 2837#define DAGB1_RDCLI19__URG_HIGH_MASK 0x000000F0L 2838#define DAGB1_RDCLI19__URG_LOW_MASK 0x00000F00L 2839#define DAGB1_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 2840#define DAGB1_RDCLI19__MAX_BW_MASK 0x001FE000L 2841#define DAGB1_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 2842#define DAGB1_RDCLI19__MIN_BW_MASK 0x01C00000L 2843#define DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 2844#define DAGB1_RDCLI19__MAX_OSD_MASK 0xFC000000L 2845//DAGB1_RDCLI20 2846#define DAGB1_RDCLI20__VIRT_CHAN__SHIFT 0x0 2847#define DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 2848#define DAGB1_RDCLI20__URG_HIGH__SHIFT 0x4 2849#define DAGB1_RDCLI20__URG_LOW__SHIFT 0x8 2850#define DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 2851#define DAGB1_RDCLI20__MAX_BW__SHIFT 0xd 2852#define DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 2853#define DAGB1_RDCLI20__MIN_BW__SHIFT 0x16 2854#define DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 2855#define DAGB1_RDCLI20__MAX_OSD__SHIFT 0x1a 2856#define DAGB1_RDCLI20__VIRT_CHAN_MASK 0x00000007L 2857#define DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 2858#define DAGB1_RDCLI20__URG_HIGH_MASK 0x000000F0L 2859#define DAGB1_RDCLI20__URG_LOW_MASK 0x00000F00L 2860#define DAGB1_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 2861#define DAGB1_RDCLI20__MAX_BW_MASK 0x001FE000L 2862#define DAGB1_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 2863#define DAGB1_RDCLI20__MIN_BW_MASK 0x01C00000L 2864#define DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 2865#define DAGB1_RDCLI20__MAX_OSD_MASK 0xFC000000L 2866//DAGB1_RDCLI21 2867#define DAGB1_RDCLI21__VIRT_CHAN__SHIFT 0x0 2868#define DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 2869#define DAGB1_RDCLI21__URG_HIGH__SHIFT 0x4 2870#define DAGB1_RDCLI21__URG_LOW__SHIFT 0x8 2871#define DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 2872#define DAGB1_RDCLI21__MAX_BW__SHIFT 0xd 2873#define DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 2874#define DAGB1_RDCLI21__MIN_BW__SHIFT 0x16 2875#define DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 2876#define DAGB1_RDCLI21__MAX_OSD__SHIFT 0x1a 2877#define DAGB1_RDCLI21__VIRT_CHAN_MASK 0x00000007L 2878#define DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 2879#define DAGB1_RDCLI21__URG_HIGH_MASK 0x000000F0L 2880#define DAGB1_RDCLI21__URG_LOW_MASK 0x00000F00L 2881#define DAGB1_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 2882#define DAGB1_RDCLI21__MAX_BW_MASK 0x001FE000L 2883#define DAGB1_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 2884#define DAGB1_RDCLI21__MIN_BW_MASK 0x01C00000L 2885#define DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 2886#define DAGB1_RDCLI21__MAX_OSD_MASK 0xFC000000L 2887//DAGB1_RDCLI22 2888#define DAGB1_RDCLI22__VIRT_CHAN__SHIFT 0x0 2889#define DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 2890#define DAGB1_RDCLI22__URG_HIGH__SHIFT 0x4 2891#define DAGB1_RDCLI22__URG_LOW__SHIFT 0x8 2892#define DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 2893#define DAGB1_RDCLI22__MAX_BW__SHIFT 0xd 2894#define DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 2895#define DAGB1_RDCLI22__MIN_BW__SHIFT 0x16 2896#define DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 2897#define DAGB1_RDCLI22__MAX_OSD__SHIFT 0x1a 2898#define DAGB1_RDCLI22__VIRT_CHAN_MASK 0x00000007L 2899#define DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 2900#define DAGB1_RDCLI22__URG_HIGH_MASK 0x000000F0L 2901#define DAGB1_RDCLI22__URG_LOW_MASK 0x00000F00L 2902#define DAGB1_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 2903#define DAGB1_RDCLI22__MAX_BW_MASK 0x001FE000L 2904#define DAGB1_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 2905#define DAGB1_RDCLI22__MIN_BW_MASK 0x01C00000L 2906#define DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 2907#define DAGB1_RDCLI22__MAX_OSD_MASK 0xFC000000L 2908//DAGB1_RDCLI23 2909#define DAGB1_RDCLI23__VIRT_CHAN__SHIFT 0x0 2910#define DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 2911#define DAGB1_RDCLI23__URG_HIGH__SHIFT 0x4 2912#define DAGB1_RDCLI23__URG_LOW__SHIFT 0x8 2913#define DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 2914#define DAGB1_RDCLI23__MAX_BW__SHIFT 0xd 2915#define DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 2916#define DAGB1_RDCLI23__MIN_BW__SHIFT 0x16 2917#define DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 2918#define DAGB1_RDCLI23__MAX_OSD__SHIFT 0x1a 2919#define DAGB1_RDCLI23__VIRT_CHAN_MASK 0x00000007L 2920#define DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 2921#define DAGB1_RDCLI23__URG_HIGH_MASK 0x000000F0L 2922#define DAGB1_RDCLI23__URG_LOW_MASK 0x00000F00L 2923#define DAGB1_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 2924#define DAGB1_RDCLI23__MAX_BW_MASK 0x001FE000L 2925#define DAGB1_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 2926#define DAGB1_RDCLI23__MIN_BW_MASK 0x01C00000L 2927#define DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 2928#define DAGB1_RDCLI23__MAX_OSD_MASK 0xFC000000L 2929//DAGB1_RD_CNTL 2930#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 2931#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 2932#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc 2933#define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf 2934#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 2935#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 2936#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L 2937#define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L 2938//DAGB1_RD_IO_CNTL 2939#define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 2940#define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 2941#define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2942#define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 2943#define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 2944#define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 2945#define DAGB1_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 2946#define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 2947#define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 2948#define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2949#define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 2950#define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 2951#define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 2952#define DAGB1_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 2953//DAGB1_RD_GMI_CNTL 2954#define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 2955#define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 2956#define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2957#define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 2958#define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 2959#define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 2960#define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 2961#define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 2962#define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 2963#define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2964#define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 2965#define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 2966#define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 2967#define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 2968//DAGB1_RD_ADDR_DAGB 2969#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2970#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2971#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2972#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 2973#define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 2974#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2975#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2976#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2977#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2978#define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 2979//DAGB1_RD_CGTT_CLK_CTRL 2980#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2981#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2982#define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2983#define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2984#define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2985#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2986#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2987#define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 2988#define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2989#define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2990//DAGB1_L1TLB_RD_CGTT_CLK_CTRL 2991#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2992#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2993#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2994#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2995#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2996#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2997#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2998#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 2999#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 3000#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 3001//DAGB1_RD_ADDR_DAGB_MAX_BURST0 3002#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 3003#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 3004#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 3005#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 3006#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 3007#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 3008#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 3009#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 3010#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 3011#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 3012#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 3013#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 3014#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 3015#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 3016#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 3017#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 3018//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 3019#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 3020#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 3021#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 3022#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 3023#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 3024#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 3025#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 3026#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 3027#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 3028#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 3029#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 3030#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 3031#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 3032#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 3033#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 3034#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 3035//DAGB1_RD_ADDR_DAGB_MAX_BURST1 3036#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 3037#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 3038#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 3039#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 3040#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 3041#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 3042#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 3043#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 3044#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 3045#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 3046#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 3047#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 3048#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 3049#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 3050#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 3051#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 3052//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 3053#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 3054#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 3055#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 3056#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 3057#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 3058#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 3059#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 3060#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 3061#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 3062#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 3063#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 3064#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 3065#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 3066#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 3067#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 3068#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 3069//DAGB1_RD_ADDR_DAGB_MAX_BURST2 3070#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 3071#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 3072#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 3073#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 3074#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 3075#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 3076#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 3077#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 3078#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 3079#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 3080#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 3081#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 3082#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 3083#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 3084#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 3085#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 3086//DAGB1_RD_ADDR_DAGB_LAZY_TIMER2 3087#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 3088#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 3089#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 3090#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 3091#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 3092#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 3093#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 3094#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 3095#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 3096#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 3097#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 3098#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 3099#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 3100#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 3101#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 3102#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 3103//DAGB1_RD_VC0_CNTL 3104#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 3105#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3106#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 3107#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3108#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 3109#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3110#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 3111#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 3112#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3113#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 3114#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3115#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 3116#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3117#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 3118//DAGB1_RD_VC1_CNTL 3119#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 3120#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3121#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 3122#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3123#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 3124#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3125#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 3126#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 3127#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3128#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 3129#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3130#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 3131#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3132#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 3133//DAGB1_RD_VC2_CNTL 3134#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 3135#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3136#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 3137#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3138#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 3139#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3140#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 3141#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 3142#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3143#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 3144#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3145#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 3146#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3147#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 3148//DAGB1_RD_VC3_CNTL 3149#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 3150#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3151#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 3152#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3153#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 3154#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3155#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 3156#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 3157#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3158#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 3159#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3160#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 3161#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3162#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 3163//DAGB1_RD_VC4_CNTL 3164#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 3165#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3166#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 3167#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3168#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 3169#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3170#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 3171#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 3172#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3173#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 3174#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3175#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 3176#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3177#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 3178//DAGB1_RD_VC5_CNTL 3179#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 3180#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3181#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 3182#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3183#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 3184#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3185#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 3186#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 3187#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3188#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 3189#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3190#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 3191#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3192#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 3193//DAGB1_RD_IO_VC_CNTL 3194#define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 3195#define DAGB1_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc 3196#define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3197#define DAGB1_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 3198#define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3199#define DAGB1_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 3200#define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 3201#define DAGB1_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 3202#define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3203#define DAGB1_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 3204#define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3205#define DAGB1_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 3206//DAGB1_RD_GMI_VC_CNTL 3207#define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 3208#define DAGB1_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 3209#define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3210#define DAGB1_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 3211#define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3212#define DAGB1_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 3213#define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 3214#define DAGB1_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 3215#define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3216#define DAGB1_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 3217#define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3218#define DAGB1_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 3219//DAGB1_RD_CNTL_MISC 3220#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 3221#define DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 3222#define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 3223#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 3224#define DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L 3225#define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L 3226//DAGB1_RD_TLB_CREDIT 3227#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 3228#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 3229#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa 3230#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf 3231#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 3232#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 3233#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 3234#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 3235#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 3236#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 3237#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 3238#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 3239//DAGB1_RD_RDRET_CREDIT_CNTL 3240#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 3241#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x5 3242#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xa 3243#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0xf 3244#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x14 3245#define DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT 0x19 3246#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 3247#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 3248#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000001FL 3249#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x000003E0L 3250#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x00007C00L 3251#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x000F8000L 3252#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x01F00000L 3253#define DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK 0x3E000000L 3254#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 3255#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 3256//DAGB1_RD_RDRET_CREDIT_CNTL2 3257#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0x0 3258#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0000003FL 3259//DAGB1_RDCLI_ASK_PENDING 3260#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 3261#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3262//DAGB1_RDCLI_GO_PENDING 3263#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 3264#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3265//DAGB1_RDCLI_GBLSEND_PENDING 3266#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 3267#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 3268//DAGB1_RDCLI_TLB_PENDING 3269#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 3270#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 3271//DAGB1_RDCLI_OARB_PENDING 3272#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 3273#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 3274//DAGB1_RDCLI_ASK2ARB_PENDING 3275#define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 3276#define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 3277//DAGB1_RDCLI_ASK2DF_PENDING 3278#define DAGB1_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 3279#define DAGB1_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 3280//DAGB1_RDCLI_OSD_PENDING 3281#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 3282#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 3283//DAGB1_RDCLI_ASK_OSD_PENDING 3284#define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 3285#define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 3286//DAGB1_RDCLI_NOALLOC_OVERRIDE 3287#define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 3288#define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 3289//DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE 3290#define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 3291#define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL 3292//DAGB1_DAGB_DLY 3293#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 3294#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 3295#define DAGB1_DAGB_DLY__POS__SHIFT 0x10 3296#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL 3297#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L 3298#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L 3299//DAGB1_CNTL_MISC 3300#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 3301#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL 3302//DAGB1_CNTL_MISC2 3303#define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 3304#define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 3305#define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 3306#define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 3307#define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 3308#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 3309#define DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 3310#define DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 3311#define DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 3312#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 3313#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa 3314#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb 3315#define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L 3316#define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L 3317#define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L 3318#define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L 3319#define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L 3320#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L 3321#define DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L 3322#define DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L 3323#define DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L 3324#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L 3325#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L 3326#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L 3327//DAGB1_FIFO_EMPTY 3328#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 3329#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x0000007FL 3330//DAGB1_FIFO_FULL 3331#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 3332#define DAGB1_FIFO_FULL__FULL_MASK 0x0000007FL 3333//DAGB1_RD_CREDITS_FULL 3334#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 3335#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0000007FL 3336//DAGB1_PERFCOUNTER_LO 3337#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3338#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3339//DAGB1_PERFCOUNTER_HI 3340#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3341#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3342#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3343#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3344//DAGB1_PERFCOUNTER0_CFG 3345#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3346#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3347#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3348#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3349#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3350#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3351#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3352#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3353#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3354#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3355//DAGB1_PERFCOUNTER1_CFG 3356#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3357#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3358#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3359#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3360#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3361#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3362#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3363#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3364#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3365#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3366//DAGB1_PERFCOUNTER2_CFG 3367#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 3368#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 3369#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 3370#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 3371#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 3372#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 3373#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 3374#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 3375#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 3376#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 3377//DAGB1_PERFCOUNTER_RSLT_CNTL 3378#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3379#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3380#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3381#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3382#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3383#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3384#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 3385#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3386#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3387#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3388#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3389#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3390//DAGB1_L1TLB_REG_RW 3391#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 3392#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 3393#define DAGB1_L1TLB_REG_RW__RESERVE__SHIFT 0x2 3394#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 3395#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 3396#define DAGB1_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL 3397//DAGB1_RESERVE1 3398#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 3399#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 3400//DAGB1_RESERVE2 3401#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 3402#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 3403//DAGB1_RESERVE3 3404#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 3405#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 3406//DAGB1_RESERVE4 3407#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 3408#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 3409//DAGB1_SDP_RD_BW_CNTL 3410#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 3411#define DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 3412#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 3413#define DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa 3414#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd 3415#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 3416#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL 3417#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L 3418#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L 3419#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L 3420//DAGB1_SDP_PRIORITY_OVERRIDE 3421#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 3422#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 3423#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 3424#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa 3425#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb 3426#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc 3427#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd 3428#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe 3429#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 3430#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 3431#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 3432#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a 3433#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b 3434#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c 3435#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d 3436#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e 3437#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL 3438#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 3439#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L 3440#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L 3441#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L 3442#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L 3443#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L 3444#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L 3445#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L 3446#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L 3447#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L 3448#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L 3449#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L 3450#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L 3451#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L 3452#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L 3453//DAGB1_SDP_RD_PRIORITY 3454#define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 3455#define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 3456#define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 3457#define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc 3458#define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 3459#define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 3460#define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL 3461#define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L 3462#define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L 3463#define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L 3464#define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L 3465#define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L 3466//DAGB1_SDP_RD_CLI2SDP_VC_MAP 3467#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 3468#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 3469#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 3470#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 3471#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 3472#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 3473#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 3474#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 3475#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 3476#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 3477#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 3478#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 3479//DAGB1_SDP_ENABLE 3480#define DAGB1_SDP_ENABLE__ENABLE__SHIFT 0x0 3481#define DAGB1_SDP_ENABLE__ENABLE_MASK 0x00000001L 3482//DAGB1_SDP_CREDITS 3483#define DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 3484#define DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 3485#define DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 3486#define DAGB1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 3487#define DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 3488#define DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L 3489//DAGB1_SDP_TAG_RESERVE0 3490#define DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 3491#define DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 3492#define DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 3493#define DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 3494#define DAGB1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 3495#define DAGB1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 3496#define DAGB1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 3497#define DAGB1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 3498//DAGB1_SDP_TAG_RESERVE1 3499#define DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 3500#define DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 3501#define DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 3502#define DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 3503#define DAGB1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 3504#define DAGB1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 3505#define DAGB1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 3506#define DAGB1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 3507//DAGB1_SDP_VCC_RESERVE0 3508#define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 3509#define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 3510#define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 3511#define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 3512#define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 3513#define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 3514#define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 3515#define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 3516#define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 3517#define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 3518//DAGB1_SDP_VCC_RESERVE1 3519#define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 3520#define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 3521#define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 3522#define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 3523#define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 3524#define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 3525#define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 3526#define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 3527//DAGB1_SDP_ERR_STATUS 3528#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 3529#define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 3530#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 3531#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 3532#define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 3533#define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 3534#define DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd 3535#define DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 3536#define DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 3537#define DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 3538#define DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 3539#define DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 3540#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 3541#define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 3542#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 3543#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 3544#define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 3545#define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 3546#define DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 3547#define DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 3548#define DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 3549#define DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 3550#define DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 3551#define DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 3552//DAGB1_SDP_REQ_CNTL 3553#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 3554#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 3555#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 3556#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 3557#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 3558#define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 3559#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 3560#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 3561#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 3562#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 3563#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 3564#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 3565#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 3566#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 3567#define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 3568#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 3569#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 3570#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 3571//DAGB1_SDP_MISC_AON 3572#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 3573#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 3574#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 3575#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 3576//DAGB1_SDP_MISC 3577#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 3578#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 3579#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 3580#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 3581#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 3582#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 3583#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 3584#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 3585#define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 3586#define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 3587#define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb 3588#define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd 3589#define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf 3590#define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 3591#define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 3592#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L 3593#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L 3594#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L 3595#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L 3596#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L 3597#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L 3598#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L 3599#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L 3600#define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L 3601#define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L 3602#define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L 3603#define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L 3604#define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L 3605#define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L 3606#define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L 3607//DAGB1_SDP_MISC2 3608#define DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 3609#define DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 3610#define DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 3611#define DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 3612#define DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L 3613#define DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L 3614#define DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L 3615#define DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L 3616//DAGB1_SDP_ARB_CNTL0 3617#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 3618#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 3619#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 3620#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 3621#define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 3622#define DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 3623#define DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 3624#define DAGB1_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 3625#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L 3626#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L 3627#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L 3628#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L 3629#define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L 3630#define DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L 3631#define DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L 3632#define DAGB1_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L 3633//DAGB1_SDP_ARB_CNTL1 3634#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 3635#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 3636#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 3637#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 3638#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL 3639#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L 3640#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L 3641#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L 3642//DAGB1_SDP_CGTT_CLK_CTRL 3643#define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 3644#define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 3645#define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 3646#define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 3647#define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 3648#define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 3649#define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 3650#define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 3651#define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 3652#define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 3653//DAGB1_SDP_LATENCY_SAMPLING 3654#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 3655#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 3656#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 3657#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 3658#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 3659#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 3660#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 3661#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 3662#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 3663#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 3664#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 3665#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 3666#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 3667#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 3668#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 3669#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 3670#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 3671#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 3672#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 3673#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 3674#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 3675#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 3676#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 3677#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 3678#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 3679#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 3680#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 3681#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 3682#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 3683#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 3684#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 3685#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 3686 3687 3688// addressBlock: mmhub_pctldec 3689//PCTL_CTRL 3690#define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 3691#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 3692#define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT 0x4 3693#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT 0x5 3694#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x7 3695#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe 3696#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 3697#define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 3698#define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 3699#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16 3700#define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b 3701#define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c 3702#define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d 3703#define PCTL_CTRL__SNR_DISABLE__SHIFT 0x1e 3704#define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f 3705#define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L 3706#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL 3707#define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK 0x00000010L 3708#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK 0x00000060L 3709#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00003F80L 3710#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L 3711#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L 3712#define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L 3713#define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L 3714#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L 3715#define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L 3716#define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L 3717#define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L 3718#define PCTL_CTRL__SNR_DISABLE_MASK 0x40000000L 3719#define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L 3720//PCTL_MMHUB_DEEPSLEEP_IB 3721#define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 3722#define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 3723#define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 3724#define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 3725#define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 3726#define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 3727#define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 3728#define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 3729#define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 3730#define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 3731#define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa 3732#define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb 3733#define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc 3734#define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd 3735#define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe 3736#define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf 3737#define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 3738#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f 3739#define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L 3740#define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L 3741#define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L 3742#define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L 3743#define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L 3744#define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L 3745#define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L 3746#define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L 3747#define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L 3748#define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L 3749#define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L 3750#define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L 3751#define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L 3752#define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L 3753#define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L 3754#define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L 3755#define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L 3756#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L 3757//PCTL_MMHUB_DEEPSLEEP_OVERRIDE 3758#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 3759#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 3760#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 3761#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 3762#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 3763#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 3764#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 3765#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 3766#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 3767#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 3768#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 3769#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 3770#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 3771#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 3772#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 3773#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 3774#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 3775#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 3776#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 3777#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 3778#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 3779#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 3780#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 3781#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 3782#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 3783#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 3784#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 3785#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 3786#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 3787#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 3788#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 3789#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 3790#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 3791#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 3792#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 3793#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L 3794//PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 3795#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 3796#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 3797#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 3798#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 3799#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 3800#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 3801#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 3802#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 3803#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 3804#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 3805#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa 3806#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb 3807#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc 3808#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd 3809#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe 3810#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf 3811#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 3812#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L 3813#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L 3814#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L 3815#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L 3816#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L 3817#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L 3818#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L 3819#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L 3820#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L 3821#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L 3822#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L 3823#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L 3824#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L 3825#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L 3826#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L 3827#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L 3828#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L 3829//PCTL_PG_IGNORE_DEEPSLEEP 3830#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 3831#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 3832#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 3833#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 3834#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 3835#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 3836#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 3837#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 3838#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 3839#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 3840#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa 3841#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb 3842#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc 3843#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd 3844#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe 3845#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf 3846#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 3847#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 3848#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 3849#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L 3850#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L 3851#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L 3852#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L 3853#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L 3854#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L 3855#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L 3856#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L 3857#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L 3858#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L 3859#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L 3860#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L 3861#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L 3862#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L 3863#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L 3864#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L 3865#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L 3866#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L 3867#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L 3868//PCTL_PG_IGNORE_DEEPSLEEP_IB 3869#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 3870#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 3871#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 3872#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 3873#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 3874#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 3875#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 3876#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 3877#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 3878#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 3879#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa 3880#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb 3881#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc 3882#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd 3883#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe 3884#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf 3885#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 3886#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 3887#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L 3888#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L 3889#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L 3890#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L 3891#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L 3892#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L 3893#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L 3894#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L 3895#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L 3896#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L 3897#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L 3898#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L 3899#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L 3900#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L 3901#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L 3902#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L 3903#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L 3904#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L 3905//PCTL_SLICE0_CFG_DAGB_WRBUSY 3906#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 3907#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3908//PCTL_SLICE0_CFG_DAGB_RDBUSY 3909#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 3910#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3911//PCTL_SLICE0_CFG_DS_ALLOW 3912#define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 3913#define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 3914#define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 3915#define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 3916#define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 3917#define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 3918#define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 3919#define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 3920#define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 3921#define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 3922#define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa 3923#define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb 3924#define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc 3925#define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd 3926#define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe 3927#define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf 3928#define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 3929#define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L 3930#define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L 3931#define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L 3932#define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L 3933#define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L 3934#define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L 3935#define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L 3936#define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L 3937#define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L 3938#define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L 3939#define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L 3940#define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L 3941#define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L 3942#define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L 3943#define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L 3944#define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L 3945#define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L 3946//PCTL_SLICE0_CFG_DS_ALLOW_IB 3947#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 3948#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 3949#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 3950#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 3951#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 3952#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 3953#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 3954#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 3955#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 3956#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 3957#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 3958#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 3959#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 3960#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 3961#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 3962#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 3963#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 3964#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 3965#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 3966#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 3967#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 3968#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 3969#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 3970#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 3971#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 3972#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 3973#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 3974#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 3975#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 3976#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 3977#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 3978#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 3979#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 3980#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 3981//PCTL_SLICE1_CFG_DAGB_WRBUSY 3982#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 3983#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3984//PCTL_SLICE1_CFG_DAGB_RDBUSY 3985#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 3986#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3987//PCTL_SLICE1_CFG_DS_ALLOW 3988#define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 3989#define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 3990#define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 3991#define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 3992#define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 3993#define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 3994#define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 3995#define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 3996#define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 3997#define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 3998#define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa 3999#define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb 4000#define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc 4001#define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd 4002#define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe 4003#define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf 4004#define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 4005#define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L 4006#define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L 4007#define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L 4008#define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L 4009#define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L 4010#define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L 4011#define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L 4012#define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L 4013#define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L 4014#define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L 4015#define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L 4016#define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L 4017#define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L 4018#define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L 4019#define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L 4020#define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L 4021#define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L 4022//PCTL_SLICE1_CFG_DS_ALLOW_IB 4023#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 4024#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 4025#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 4026#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 4027#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 4028#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 4029#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 4030#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 4031#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 4032#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 4033#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 4034#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 4035#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 4036#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 4037#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 4038#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 4039#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 4040#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 4041#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 4042#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 4043#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 4044#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 4045#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 4046#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 4047#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 4048#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 4049#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 4050#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 4051#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 4052#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 4053#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 4054#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 4055#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 4056#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 4057//PCTL_UTCL2_MISC 4058#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 4059#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 4060#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 4061#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 4062#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 4063#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 4064#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 4065#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 4066#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 4067#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 4068#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000007FFL 4069#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 4070#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 4071#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 4072#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 4073#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 4074#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 4075#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 4076#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 4077#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 4078//PCTL_SLICE0_MISC 4079#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 4080#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 4081#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 4082#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 4083#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 4084#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 4085#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 4086#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 4087#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 4088#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 4089#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 4090#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e 4091#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f 4092#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL 4093#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 4094#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 4095#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 4096#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 4097#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 4098#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 4099#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 4100#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 4101#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 4102#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 4103#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L 4104#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L 4105//PCTL_SLICE1_MISC 4106#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 4107#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 4108#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 4109#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 4110#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 4111#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 4112#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 4113#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 4114#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 4115#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 4116#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 4117#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e 4118#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f 4119#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL 4120#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 4121#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 4122#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 4123#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 4124#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 4125#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 4126#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 4127#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 4128#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 4129#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 4130#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L 4131#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L 4132//PCTL_RENG_CTRL 4133#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 4134#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4135#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L 4136#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4137//PCTL_UTCL2_RENG_EXECUTE 4138#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4139#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4140#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4141#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 4142#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4143#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4144#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 4145#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 4146//PCTL_SLICE0_RENG_EXECUTE 4147#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4148#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4149#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4150#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4151#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4152#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4153#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4154#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4155//PCTL_SLICE1_RENG_EXECUTE 4156#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4157#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4158#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4159#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4160#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4161#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4162#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4163#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4164//PCTL_UTCL2_RENG_RAM_INDEX 4165#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4166#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 4167//PCTL_UTCL2_RENG_RAM_DATA 4168#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4169#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4170//PCTL_SLICE0_RENG_RAM_INDEX 4171#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4172#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4173//PCTL_SLICE0_RENG_RAM_DATA 4174#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4175#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4176//PCTL_SLICE1_RENG_RAM_INDEX 4177#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4178#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4179//PCTL_SLICE1_RENG_RAM_DATA 4180#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4181#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4182//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 4183#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4184#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4185#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4186#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4187//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 4188#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4189#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4190#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4191#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4192//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 4193#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4194#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4195#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4196#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4197//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 4198#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4199#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4200#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4201#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4202//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 4203#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4204#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4205#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4206#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4207//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 4208#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4209#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4210#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4211#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4212//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 4213#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4214#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4215#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4216#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4217//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 4218#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4219#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4220#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4221#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4222//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 4223#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4224#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4225#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4226#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4227//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 4228#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4229#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4230#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4231#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4232//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 4233#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4234#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4235#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4236#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4237//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 4238#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4239#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4240#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4241#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4242//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 4243#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4244#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4245#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4246#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4247//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 4248#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4249#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4250#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4251#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4252//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 4253#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4254#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4255#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4256#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4257//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 4258#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4259#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4260#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4261#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4262//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 4263#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4264#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4265#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4266#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4267//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 4268#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4269#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4270#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4271#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4272//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 4273#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4274#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4275#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4276#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4277//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 4278#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4279#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4280#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4281#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4282//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 4283#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4284#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4285#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4286#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4287//PCTL_STATUS 4288#define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x0 4289#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1 4290#define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2 4291#define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3 4292#define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4 4293#define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5 4294#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT 0x7 4295#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT 0xf 4296#define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10 4297#define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11 4298#define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12 4299#define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13 4300#define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14 4301#define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00000001L 4302#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L 4303#define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L 4304#define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L 4305#define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L 4306#define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L 4307#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK 0x00007F80L 4308#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK 0x00008000L 4309#define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L 4310#define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L 4311#define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L 4312#define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L 4313#define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L 4314//PCTL_PERFCOUNTER_LO 4315#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4316#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4317//PCTL_PERFCOUNTER_HI 4318#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4319#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4320#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4321#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4322//PCTL_PERFCOUNTER0_CFG 4323#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4324#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4325#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4326#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4327#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4328#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4329#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4330#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4331#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4332#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4333//PCTL_PERFCOUNTER1_CFG 4334#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4335#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4336#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4337#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4338#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4339#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4340#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4341#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4342#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4343#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4344//PCTL_PERFCOUNTER_RSLT_CNTL 4345#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4346#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4347#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4348#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4349#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4350#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4351#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4352#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4353#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4354#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4355#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4356#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4357//PCTL_RESERVED_0 4358#define PCTL_RESERVED_0__WORD__SHIFT 0x0 4359#define PCTL_RESERVED_0__BYTE__SHIFT 0x10 4360#define PCTL_RESERVED_0__BIT7__SHIFT 0x18 4361#define PCTL_RESERVED_0__BIT6__SHIFT 0x19 4362#define PCTL_RESERVED_0__BIT5__SHIFT 0x1a 4363#define PCTL_RESERVED_0__BIT4__SHIFT 0x1b 4364#define PCTL_RESERVED_0__BIT3__SHIFT 0x1c 4365#define PCTL_RESERVED_0__BIT2__SHIFT 0x1d 4366#define PCTL_RESERVED_0__BIT1__SHIFT 0x1e 4367#define PCTL_RESERVED_0__BIT0__SHIFT 0x1f 4368#define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL 4369#define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L 4370#define PCTL_RESERVED_0__BIT7_MASK 0x01000000L 4371#define PCTL_RESERVED_0__BIT6_MASK 0x02000000L 4372#define PCTL_RESERVED_0__BIT5_MASK 0x04000000L 4373#define PCTL_RESERVED_0__BIT4_MASK 0x08000000L 4374#define PCTL_RESERVED_0__BIT3_MASK 0x10000000L 4375#define PCTL_RESERVED_0__BIT2_MASK 0x20000000L 4376#define PCTL_RESERVED_0__BIT1_MASK 0x40000000L 4377#define PCTL_RESERVED_0__BIT0_MASK 0x80000000L 4378//PCTL_RESERVED_1 4379#define PCTL_RESERVED_1__WORD__SHIFT 0x0 4380#define PCTL_RESERVED_1__BYTE__SHIFT 0x10 4381#define PCTL_RESERVED_1__BIT7__SHIFT 0x18 4382#define PCTL_RESERVED_1__BIT6__SHIFT 0x19 4383#define PCTL_RESERVED_1__BIT5__SHIFT 0x1a 4384#define PCTL_RESERVED_1__BIT4__SHIFT 0x1b 4385#define PCTL_RESERVED_1__BIT3__SHIFT 0x1c 4386#define PCTL_RESERVED_1__BIT2__SHIFT 0x1d 4387#define PCTL_RESERVED_1__BIT1__SHIFT 0x1e 4388#define PCTL_RESERVED_1__BIT0__SHIFT 0x1f 4389#define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL 4390#define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L 4391#define PCTL_RESERVED_1__BIT7_MASK 0x01000000L 4392#define PCTL_RESERVED_1__BIT6_MASK 0x02000000L 4393#define PCTL_RESERVED_1__BIT5_MASK 0x04000000L 4394#define PCTL_RESERVED_1__BIT4_MASK 0x08000000L 4395#define PCTL_RESERVED_1__BIT3_MASK 0x10000000L 4396#define PCTL_RESERVED_1__BIT2_MASK 0x20000000L 4397#define PCTL_RESERVED_1__BIT1_MASK 0x40000000L 4398#define PCTL_RESERVED_1__BIT0_MASK 0x80000000L 4399//PCTL_RESERVED_2 4400#define PCTL_RESERVED_2__WORD__SHIFT 0x0 4401#define PCTL_RESERVED_2__BYTE__SHIFT 0x10 4402#define PCTL_RESERVED_2__BIT7__SHIFT 0x18 4403#define PCTL_RESERVED_2__BIT6__SHIFT 0x19 4404#define PCTL_RESERVED_2__BIT5__SHIFT 0x1a 4405#define PCTL_RESERVED_2__BIT4__SHIFT 0x1b 4406#define PCTL_RESERVED_2__BIT3__SHIFT 0x1c 4407#define PCTL_RESERVED_2__BIT2__SHIFT 0x1d 4408#define PCTL_RESERVED_2__BIT1__SHIFT 0x1e 4409#define PCTL_RESERVED_2__BIT0__SHIFT 0x1f 4410#define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL 4411#define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L 4412#define PCTL_RESERVED_2__BIT7_MASK 0x01000000L 4413#define PCTL_RESERVED_2__BIT6_MASK 0x02000000L 4414#define PCTL_RESERVED_2__BIT5_MASK 0x04000000L 4415#define PCTL_RESERVED_2__BIT4_MASK 0x08000000L 4416#define PCTL_RESERVED_2__BIT3_MASK 0x10000000L 4417#define PCTL_RESERVED_2__BIT2_MASK 0x20000000L 4418#define PCTL_RESERVED_2__BIT1_MASK 0x40000000L 4419#define PCTL_RESERVED_2__BIT0_MASK 0x80000000L 4420//PCTL_RESERVED_3 4421#define PCTL_RESERVED_3__WORD__SHIFT 0x0 4422#define PCTL_RESERVED_3__BYTE__SHIFT 0x10 4423#define PCTL_RESERVED_3__BIT7__SHIFT 0x18 4424#define PCTL_RESERVED_3__BIT6__SHIFT 0x19 4425#define PCTL_RESERVED_3__BIT5__SHIFT 0x1a 4426#define PCTL_RESERVED_3__BIT4__SHIFT 0x1b 4427#define PCTL_RESERVED_3__BIT3__SHIFT 0x1c 4428#define PCTL_RESERVED_3__BIT2__SHIFT 0x1d 4429#define PCTL_RESERVED_3__BIT1__SHIFT 0x1e 4430#define PCTL_RESERVED_3__BIT0__SHIFT 0x1f 4431#define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL 4432#define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L 4433#define PCTL_RESERVED_3__BIT7_MASK 0x01000000L 4434#define PCTL_RESERVED_3__BIT6_MASK 0x02000000L 4435#define PCTL_RESERVED_3__BIT5_MASK 0x04000000L 4436#define PCTL_RESERVED_3__BIT4_MASK 0x08000000L 4437#define PCTL_RESERVED_3__BIT3_MASK 0x10000000L 4438#define PCTL_RESERVED_3__BIT2_MASK 0x20000000L 4439#define PCTL_RESERVED_3__BIT1_MASK 0x40000000L 4440#define PCTL_RESERVED_3__BIT0_MASK 0x80000000L 4441 4442 4443// addressBlock: mmhub_l1tlb_mmvml1pfdec 4444//MMMC_VM_MX_L1_TLB0_STATUS 4445#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 4446#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4447#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 4448#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4449//MMMC_VM_MX_L1_TLB1_STATUS 4450#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 4451#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4452#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 4453#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4454//MMMC_VM_MX_L1_TLB2_STATUS 4455#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 4456#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4457#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 4458#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4459//MMMC_VM_MX_L1_TLB3_STATUS 4460#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 4461#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4462#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 4463#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4464//MMMC_VM_MX_L1_TLB4_STATUS 4465#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 4466#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4467#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 4468#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4469//MMMC_VM_MX_L1_TLB5_STATUS 4470#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 4471#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4472#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 4473#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4474 4475 4476// addressBlock: mmhub_l1tlb_mmvml1pldec 4477//MMMC_VM_MX_L1_PERFCOUNTER0_CFG 4478#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4479#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4480#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4481#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4482#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4483#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4484#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4485#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4486#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4487#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4488//MMMC_VM_MX_L1_PERFCOUNTER1_CFG 4489#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4490#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4491#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4492#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4493#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4494#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4495#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4496#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4497#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4498#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4499//MMMC_VM_MX_L1_PERFCOUNTER2_CFG 4500#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 4501#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 4502#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 4503#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 4504#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4505#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 4506#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 4507#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 4508#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 4509#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 4510//MMMC_VM_MX_L1_PERFCOUNTER3_CFG 4511#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 4512#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 4513#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 4514#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 4515#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4516#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 4517#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 4518#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 4519#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 4520#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 4521//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 4522#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4523#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4524#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4525#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4526#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4527#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4528#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4529#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4530#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4531#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4532#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4533#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4534 4535 4536// addressBlock: mmhub_l1tlb_mmvml1prdec 4537//MMMC_VM_MX_L1_PERFCOUNTER_LO 4538#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4539#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4540//MMMC_VM_MX_L1_PERFCOUNTER_HI 4541#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4542#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4543#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4544#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4545 4546 4547// addressBlock: mmhub_mmutcl2_mmvml2pfdec 4548//MMVM_L2_CNTL 4549#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 4550#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 4551#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 4552#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 4553#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 4554#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 4555#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 4556#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4557#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 4558#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 4559#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 4560#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 4561#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 4562#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 4563#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 4564#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 4565#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 4566#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 4567#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 4568#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 4569#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 4570#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4571#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 4572#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 4573#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 4574#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 4575#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 4576#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 4577//MMVM_L2_CNTL2 4578#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 4579#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 4580#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 4581#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 4582#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 4583#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 4584#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 4585#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 4586#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 4587#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 4588#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 4589#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 4590#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 4591#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 4592//MMVM_L2_CNTL3 4593#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 4594#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4595#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 4596#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 4597#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 4598#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 4599#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 4600#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 4601#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 4602#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 4603#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 4604#define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 4605#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4606#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 4607#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 4608#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 4609#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 4610#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 4611#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 4612#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 4613#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 4614#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 4615//MMVM_L2_STATUS 4616#define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 4617#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 4618#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 4619#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 4620#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 4621#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 4622#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 4623#define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L 4624#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 4625#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 4626#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 4627#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 4628#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 4629#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 4630//MMVM_DUMMY_PAGE_FAULT_CNTL 4631#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 4632#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 4633#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 4634#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 4635#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 4636#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 4637//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 4638#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 4639#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4640//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 4641#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 4642#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 4643//MMVM_INVALIDATE_CNTL 4644#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 4645#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 4646#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL 4647#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L 4648//MMVM_L2_PROTECTION_FAULT_CNTL 4649#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 4650#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 4651#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 4652#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 4653#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 4654#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 4655#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 4656#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 4657#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 4658#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 4659#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4660#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 4661#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4662#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 4663#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 4664#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 4665#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 4666#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 4667#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 4668#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 4669#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 4670#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 4671#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 4672#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 4673#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 4674#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 4675#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 4676#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4677#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 4678#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4679#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 4680#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 4681#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 4682#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 4683//MMVM_L2_PROTECTION_FAULT_CNTL2 4684#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 4685#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 4686#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 4687#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 4688#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 4689#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 4690#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 4691#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 4692#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 4693#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 4694//MMVM_L2_PROTECTION_FAULT_MM_CNTL3 4695#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4696#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4697//MMVM_L2_PROTECTION_FAULT_MM_CNTL4 4698#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4699#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4700//MMVM_L2_PROTECTION_FAULT_STATUS 4701#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 4702#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 4703#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 4704#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 4705#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 4706#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 4707#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 4708#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 4709#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 4710#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 4711#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d 4712#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 4713#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 4714#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 4715#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 4716#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 4717#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 4718#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 4719#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 4720#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 4721#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 4722#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L 4723//MMVM_L2_PROTECTION_FAULT_ADDR_LO32 4724#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 4725#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4726//MMVM_L2_PROTECTION_FAULT_ADDR_HI32 4727#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 4728#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4729//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 4730#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 4731#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4732//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 4733#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 4734#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4735//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 4736#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4737#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4738//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 4739#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4740#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4741//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 4742#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4743#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4744//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 4745#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4746#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4747//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 4748#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 4749#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 4750//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 4751#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 4752#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 4753//MMVM_L2_CNTL4 4754#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 4755#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 4756#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 4757#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 4758#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 4759#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 4760#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d 4761#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e 4762#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f 4763#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 4764#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 4765#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 4766#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 4767#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 4768#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 4769#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L 4770#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L 4771#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L 4772//MMVM_L2_MM_GROUP_RT_CLASSES 4773#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 4774#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 4775#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 4776#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 4777#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 4778#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 4779#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 4780#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 4781#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 4782#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 4783#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 4784#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 4785#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 4786#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 4787#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 4788#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 4789#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 4790#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 4791#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 4792#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 4793#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 4794#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 4795#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 4796#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 4797#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 4798#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 4799#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 4800#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 4801#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 4802#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 4803#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 4804#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 4805#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 4806#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 4807#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 4808#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 4809#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 4810#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 4811#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 4812#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 4813#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 4814#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 4815#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 4816#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 4817#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 4818#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 4819#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 4820#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 4821#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 4822#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 4823#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 4824#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 4825#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 4826#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 4827#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 4828#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 4829#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 4830#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 4831#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 4832#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 4833#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 4834#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 4835#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 4836#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 4837//MMVM_L2_BANK_SELECT_RESERVED_CID 4838#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 4839#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 4840#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 4841#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 4842#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 4843#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 4844#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 4845#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 4846#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 4847#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 4848#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 4849#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 4850//MMVM_L2_BANK_SELECT_RESERVED_CID2 4851#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 4852#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 4853#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 4854#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 4855#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 4856#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 4857#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 4858#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 4859#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 4860#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 4861#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 4862#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 4863//MMVM_L2_CACHE_PARITY_CNTL 4864#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 4865#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 4866#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 4867#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 4868#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 4869#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 4870#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 4871#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 4872#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 4873#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 4874#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 4875#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 4876#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 4877#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 4878#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 4879#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 4880#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 4881#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 4882//MMVM_L2_CGTT_CLK_CTRL 4883#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4884#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 4885#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 4886#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 4887#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 4888#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 4889#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 4890#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 4891#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 4892#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 4893//MMVM_L2_CNTL5 4894#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 4895#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 4896#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe 4897#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf 4898#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10 4899#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11 4900#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 4901#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L 4902#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L 4903#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L 4904#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L 4905#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L 4906//MMVM_L2_GCR_CNTL 4907#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 4908#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 4909#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L 4910#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL 4911//MMVM_L2_CGTT_BUSY_CTRL 4912#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 4913#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 4914#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 4915#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 4916//MMVM_L2_PTE_CACHE_DUMP_CNTL 4917#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 4918#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 4919#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 4920#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 4921#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc 4922#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 4923#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L 4924#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L 4925#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L 4926#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L 4927#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L 4928#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L 4929//MMVM_L2_PTE_CACHE_DUMP_READ 4930#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 4931#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL 4932//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 4933#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 4934#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL 4935//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 4936#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 4937#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 4938#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 4939#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc 4940#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd 4941#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf 4942#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10 4943#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11 4944#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12 4945#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e 4946#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL 4947#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L 4948#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L 4949#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L 4950#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L 4951#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L 4952#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L 4953#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L 4954#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L 4955#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L 4956//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 4957#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 4958#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL 4959//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 4960#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 4961#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 4962#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 4963#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd 4964#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe 4965#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf 4966#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 4967#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 4968#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 4969#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 4970#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 4971#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 4972#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f 4973#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL 4974#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L 4975#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L 4976#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L 4977#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L 4978#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L 4979#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L 4980#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L 4981#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L 4982#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L 4983#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L 4984#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L 4985#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L 4986//MMVM_L2_BANK_SELECT_MASKS 4987#define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 4988#define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 4989#define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 4990#define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc 4991#define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL 4992#define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L 4993#define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L 4994#define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L 4995//MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 4996#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 4997#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa 4998#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL 4999#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L 5000//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 5001#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 5002#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa 5003#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL 5004#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L 5005//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 5006#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 5007#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa 5008#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL 5009#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L 5010//MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 5011#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 5012#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa 5013#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL 5014#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L 5015//MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 5016#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 5017#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa 5018#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL 5019#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L 5020 5021 5022// addressBlock: mmhub_mmutcl2_mmvml2vcdec 5023//MMVM_CONTEXT0_CNTL 5024#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5025#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5026#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5027#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5028#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5029#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5030#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5031#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5032#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5033#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5034#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5035#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5036#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5037#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5038#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5039#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5040#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5041#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5042#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5043#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5044#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5045#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5046#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5047#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5048#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5049#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5050#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5051#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5052#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5053#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5054#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5055#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5056#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5057#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5058#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5059#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5060#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5061#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5062#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5063#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5064#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5065#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5066//MMVM_CONTEXT1_CNTL 5067#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5068#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5069#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5070#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5071#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5072#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5073#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5074#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5075#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5076#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5077#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5078#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5079#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5080#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5081#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5082#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5083#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5084#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5085#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5086#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5087#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5088#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5089#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5090#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5091#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5092#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5093#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5094#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5095#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5096#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5097#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5098#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5099#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5100#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5101#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5102#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5103#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5104#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5105#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5106#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5107#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5108#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5109//MMVM_CONTEXT2_CNTL 5110#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5111#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5112#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5113#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5114#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5115#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5116#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5117#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5118#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5119#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5120#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5121#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5122#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5123#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5124#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5125#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5126#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5127#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5128#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5129#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5130#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5131#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5132#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5133#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5134#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5135#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5136#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5137#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5138#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5139#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5140#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5141#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5142#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5143#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5144#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5145#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5146#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5147#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5148#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5149#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5150#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5151#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5152//MMVM_CONTEXT3_CNTL 5153#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5154#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5155#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5156#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5157#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5158#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5159#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5160#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5161#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5162#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5163#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5164#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5165#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5166#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5167#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5168#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5169#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5170#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5171#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5172#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5173#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5174#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5175#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5176#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5177#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5178#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5179#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5180#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5181#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5182#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5183#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5184#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5185#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5186#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5187#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5188#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5189#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5190#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5191#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5192#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5193#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5194#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5195//MMVM_CONTEXT4_CNTL 5196#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5197#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5198#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5199#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5200#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5201#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5202#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5203#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5204#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5205#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5206#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5207#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5208#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5209#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5210#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5211#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5212#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5213#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5214#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5215#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5216#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5217#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5218#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5219#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5220#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5221#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5222#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5223#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5224#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5225#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5226#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5227#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5228#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5229#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5230#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5231#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5232#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5233#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5234#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5235#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5236#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5237#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5238//MMVM_CONTEXT5_CNTL 5239#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5240#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5241#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5242#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5243#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5244#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5245#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5246#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5247#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5248#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5249#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5250#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5251#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5252#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5253#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5254#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5255#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5256#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5257#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5258#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5259#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5260#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5261#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5262#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5263#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5264#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5265#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5266#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5267#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5268#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5269#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5270#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5271#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5272#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5273#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5274#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5275#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5276#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5277#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5278#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5279#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5280#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5281//MMVM_CONTEXT6_CNTL 5282#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5283#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5284#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5285#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5286#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5287#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5288#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5289#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5290#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5291#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5292#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5293#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5294#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5295#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5296#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5297#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5298#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5299#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5300#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5301#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5302#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5303#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5304#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5305#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5306#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5307#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5308#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5309#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5310#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5311#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5312#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5313#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5314#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5315#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5316#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5317#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5318#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5319#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5320#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5321#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5322#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5323#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5324//MMVM_CONTEXT7_CNTL 5325#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5326#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5327#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5328#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5329#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5330#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5331#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5332#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5333#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5334#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5335#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5336#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5337#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5338#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5339#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5340#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5341#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5342#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5343#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5344#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5345#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5346#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5347#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5348#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5349#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5350#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5351#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5352#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5353#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5354#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5355#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5356#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5357#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5358#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5359#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5360#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5361#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5362#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5363#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5364#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5365#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5366#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5367//MMVM_CONTEXT8_CNTL 5368#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5369#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5370#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5371#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5372#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5373#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5374#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5375#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5376#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5377#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5378#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5379#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5380#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5381#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5382#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5383#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5384#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5385#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5386#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5387#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5388#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5389#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5390#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5391#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5392#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5393#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5394#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5395#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5396#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5397#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5398#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5399#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5400#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5401#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5402#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5403#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5404#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5405#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5406#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5407#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5408#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5409#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5410//MMVM_CONTEXT9_CNTL 5411#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5412#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5413#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5414#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5415#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5416#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5417#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5418#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5419#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5420#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5421#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5422#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5423#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5424#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5425#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5426#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5427#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5428#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5429#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5430#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5431#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5432#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5433#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5434#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5435#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5436#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5437#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5438#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5439#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5440#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5441#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5442#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5443#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5444#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5445#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5446#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5447#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5448#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5449#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5450#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5451#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5452#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5453//MMVM_CONTEXT10_CNTL 5454#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5455#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5456#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5457#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5458#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5459#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5460#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5461#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5462#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5463#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5464#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5465#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5466#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5467#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5468#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5469#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5470#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5471#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5472#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5473#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5474#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5475#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5476#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5477#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5478#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5479#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5480#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5481#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5482#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5483#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5484#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5485#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5486#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5487#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5488#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5489#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5490#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5491#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5492#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5493#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5494#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5495#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5496//MMVM_CONTEXT11_CNTL 5497#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5498#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5499#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5500#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5501#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5502#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5503#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5504#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5505#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5506#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5507#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5508#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5509#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5510#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5511#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5512#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5513#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5514#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5515#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5516#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5517#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5518#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5519#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5520#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5521#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5522#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5523#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5524#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5525#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5526#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5527#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5528#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5529#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5530#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5531#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5532#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5533#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5534#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5535#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5536#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5537#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5538#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5539//MMVM_CONTEXT12_CNTL 5540#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5541#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5542#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5543#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5544#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5545#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5546#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5547#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5548#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5549#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5550#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5551#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5552#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5553#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5554#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5555#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5556#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5557#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5558#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5559#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5560#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5561#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5562#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5563#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5564#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5565#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5566#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5567#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5568#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5569#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5570#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5571#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5572#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5573#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5574#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5575#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5576#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5577#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5578#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5579#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5580#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5581#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5582//MMVM_CONTEXT13_CNTL 5583#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5584#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5585#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5586#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5587#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5588#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5589#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5590#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5591#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5592#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5593#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5594#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5595#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5596#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5597#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5598#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5599#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5600#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5601#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5602#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5603#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5604#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5605#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5606#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5607#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5608#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5609#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5610#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5611#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5612#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5613#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5614#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5615#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5616#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5617#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5618#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5619#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5620#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5621#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5622#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5623#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5624#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5625//MMVM_CONTEXT14_CNTL 5626#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5627#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5628#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5629#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5630#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5631#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5632#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5633#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5634#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5635#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5636#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5637#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5638#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5639#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5640#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5641#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5642#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5643#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5644#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5645#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5646#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5647#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5648#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5649#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5650#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5651#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5652#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5653#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5654#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5655#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5656#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5657#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5658#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5659#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5660#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5661#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5662#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5663#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5664#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5665#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5666#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5667#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5668//MMVM_CONTEXT15_CNTL 5669#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5670#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5671#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5672#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5673#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5674#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5675#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5676#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5677#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5678#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5679#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5680#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5681#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5682#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5683#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5684#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5685#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5686#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5687#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5688#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5689#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5690#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5691#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5692#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5693#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5694#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5695#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5696#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5697#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5698#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5699#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5700#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5701#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5702#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5703#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5704#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5705#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5706#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5707#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5708#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5709#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5710#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5711//MMVM_CONTEXTS_DISABLE 5712#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 5713#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 5714#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 5715#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 5716#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 5717#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 5718#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 5719#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 5720#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 5721#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 5722#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 5723#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 5724#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 5725#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 5726#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 5727#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 5728#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 5729#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 5730#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 5731#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 5732#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 5733#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 5734#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 5735#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 5736#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 5737#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 5738#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 5739#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 5740#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 5741#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 5742#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 5743#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 5744//MMVM_INVALIDATE_ENG0_SEM 5745#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 5746#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 5747//MMVM_INVALIDATE_ENG1_SEM 5748#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 5749#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 5750//MMVM_INVALIDATE_ENG2_SEM 5751#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 5752#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 5753//MMVM_INVALIDATE_ENG3_SEM 5754#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 5755#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 5756//MMVM_INVALIDATE_ENG4_SEM 5757#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 5758#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 5759//MMVM_INVALIDATE_ENG5_SEM 5760#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 5761#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 5762//MMVM_INVALIDATE_ENG6_SEM 5763#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 5764#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 5765//MMVM_INVALIDATE_ENG7_SEM 5766#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 5767#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 5768//MMVM_INVALIDATE_ENG8_SEM 5769#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 5770#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 5771//MMVM_INVALIDATE_ENG9_SEM 5772#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 5773#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 5774//MMVM_INVALIDATE_ENG10_SEM 5775#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 5776#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 5777//MMVM_INVALIDATE_ENG11_SEM 5778#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 5779#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 5780//MMVM_INVALIDATE_ENG12_SEM 5781#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 5782#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 5783//MMVM_INVALIDATE_ENG13_SEM 5784#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 5785#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 5786//MMVM_INVALIDATE_ENG14_SEM 5787#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 5788#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 5789//MMVM_INVALIDATE_ENG15_SEM 5790#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 5791#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 5792//MMVM_INVALIDATE_ENG16_SEM 5793#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 5794#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 5795//MMVM_INVALIDATE_ENG17_SEM 5796#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 5797#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 5798//MMVM_INVALIDATE_ENG0_REQ 5799#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5800#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 5801#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5802#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5803#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5804#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5805#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5806#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5807#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 5808#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5809#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5810#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L 5811#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5812#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5813#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5814#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5815#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5816#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5817#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L 5818#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5819//MMVM_INVALIDATE_ENG1_REQ 5820#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5821#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 5822#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5823#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5824#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5825#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5826#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5827#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5828#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 5829#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5830#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5831#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L 5832#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5833#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5834#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5835#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5836#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5837#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5838#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L 5839#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5840//MMVM_INVALIDATE_ENG2_REQ 5841#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5842#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 5843#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5844#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5845#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5846#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5847#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5848#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5849#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 5850#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5851#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5852#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L 5853#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5854#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5855#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5856#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5857#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5858#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5859#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L 5860#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5861//MMVM_INVALIDATE_ENG3_REQ 5862#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5863#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 5864#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5865#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5866#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5867#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5868#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5869#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5870#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 5871#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5872#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5873#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L 5874#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5875#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5876#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5877#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5878#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5879#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5880#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L 5881#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5882//MMVM_INVALIDATE_ENG4_REQ 5883#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5884#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 5885#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5886#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5887#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5888#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5889#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5890#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5891#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 5892#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5893#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5894#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L 5895#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5896#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5897#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5898#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5899#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5900#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5901#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L 5902#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5903//MMVM_INVALIDATE_ENG5_REQ 5904#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5905#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 5906#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5907#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5908#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5909#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5910#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5911#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5912#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 5913#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5914#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5915#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L 5916#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5917#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5918#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5919#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5920#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5921#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5922#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L 5923#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5924//MMVM_INVALIDATE_ENG6_REQ 5925#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5926#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 5927#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5928#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5929#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5930#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5931#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5932#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5933#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 5934#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5935#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5936#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L 5937#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5938#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5939#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5940#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5941#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5942#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5943#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L 5944#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5945//MMVM_INVALIDATE_ENG7_REQ 5946#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5947#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 5948#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5949#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5950#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5951#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5952#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5953#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5954#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 5955#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5956#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5957#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L 5958#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5959#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5960#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5961#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5962#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5963#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5964#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L 5965#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5966//MMVM_INVALIDATE_ENG8_REQ 5967#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5968#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 5969#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5970#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5971#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5972#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5973#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5974#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5975#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 5976#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5977#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5978#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L 5979#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5980#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5981#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5982#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5983#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5984#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5985#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L 5986#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5987//MMVM_INVALIDATE_ENG9_REQ 5988#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5989#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 5990#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5991#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5992#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5993#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5994#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5995#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5996#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 5997#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5998#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5999#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L 6000#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6001#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6002#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6003#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6004#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6005#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6006#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L 6007#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6008//MMVM_INVALIDATE_ENG10_REQ 6009#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6010#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 6011#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6012#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6013#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6014#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6015#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6016#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6017#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 6018#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6019#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6020#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L 6021#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6022#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6023#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6024#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6025#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6026#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6027#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L 6028#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6029//MMVM_INVALIDATE_ENG11_REQ 6030#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6031#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 6032#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6033#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6034#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6035#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6036#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6037#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6038#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 6039#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6040#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6041#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L 6042#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6043#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6044#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6045#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6046#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6047#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6048#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L 6049#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6050//MMVM_INVALIDATE_ENG12_REQ 6051#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6052#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 6053#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6054#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6055#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6056#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6057#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6058#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6059#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 6060#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6061#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6062#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L 6063#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6064#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6065#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6066#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6067#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6068#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6069#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L 6070#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6071//MMVM_INVALIDATE_ENG13_REQ 6072#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6073#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 6074#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6075#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6076#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6077#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6078#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6079#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6080#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 6081#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6082#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6083#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L 6084#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6085#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6086#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6087#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6088#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6089#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6090#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L 6091#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6092//MMVM_INVALIDATE_ENG14_REQ 6093#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6094#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 6095#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6096#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6097#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6098#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6099#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6100#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6101#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 6102#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6103#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6104#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L 6105#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6106#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6107#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6108#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6109#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6110#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6111#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L 6112#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6113//MMVM_INVALIDATE_ENG15_REQ 6114#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6115#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 6116#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6117#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6118#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6119#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6120#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6121#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6122#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 6123#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6124#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6125#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L 6126#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6127#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6128#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6129#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6130#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6131#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6132#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L 6133#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6134//MMVM_INVALIDATE_ENG16_REQ 6135#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6136#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 6137#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6138#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6139#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6140#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6141#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6142#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6143#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 6144#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6145#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6146#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L 6147#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6148#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6149#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6150#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6151#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6152#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6153#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L 6154#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6155//MMVM_INVALIDATE_ENG17_REQ 6156#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6157#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 6158#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6159#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6160#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6161#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6162#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6163#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6164#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 6165#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6166#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6167#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L 6168#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6169#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6170#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6171#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6172#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6173#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6174#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L 6175#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6176//MMVM_INVALIDATE_ENG0_ACK 6177#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6178#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 6179#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6180#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 6181//MMVM_INVALIDATE_ENG1_ACK 6182#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6183#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 6184#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6185#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 6186//MMVM_INVALIDATE_ENG2_ACK 6187#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6188#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 6189#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6190#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 6191//MMVM_INVALIDATE_ENG3_ACK 6192#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6193#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 6194#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6195#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 6196//MMVM_INVALIDATE_ENG4_ACK 6197#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6198#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 6199#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6200#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 6201//MMVM_INVALIDATE_ENG5_ACK 6202#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6203#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 6204#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6205#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 6206//MMVM_INVALIDATE_ENG6_ACK 6207#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6208#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 6209#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6210#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 6211//MMVM_INVALIDATE_ENG7_ACK 6212#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6213#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 6214#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6215#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 6216//MMVM_INVALIDATE_ENG8_ACK 6217#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6218#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 6219#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6220#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 6221//MMVM_INVALIDATE_ENG9_ACK 6222#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6223#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 6224#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6225#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 6226//MMVM_INVALIDATE_ENG10_ACK 6227#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6228#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 6229#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6230#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 6231//MMVM_INVALIDATE_ENG11_ACK 6232#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6233#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 6234#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6235#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 6236//MMVM_INVALIDATE_ENG12_ACK 6237#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6238#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 6239#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6240#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 6241//MMVM_INVALIDATE_ENG13_ACK 6242#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6243#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 6244#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6245#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 6246//MMVM_INVALIDATE_ENG14_ACK 6247#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6248#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 6249#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6250#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 6251//MMVM_INVALIDATE_ENG15_ACK 6252#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6253#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 6254#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6255#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 6256//MMVM_INVALIDATE_ENG16_ACK 6257#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6258#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 6259#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6260#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 6261//MMVM_INVALIDATE_ENG17_ACK 6262#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6263#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 6264#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6265#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 6266//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 6267#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6268#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6269#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6270#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6271//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 6272#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6273#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6274//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 6275#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6276#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6277#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6278#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6279//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 6280#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6281#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6282//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 6283#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6284#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6285#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6286#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6287//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 6288#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6289#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6290//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 6291#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6292#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6293#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6294#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6295//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 6296#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6297#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6298//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 6299#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6300#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6301#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6302#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6303//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 6304#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6305#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6306//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 6307#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6308#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6309#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6310#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6311//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 6312#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6313#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6314//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 6315#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6316#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6317#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6318#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6319//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 6320#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6321#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6322//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 6323#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6324#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6325#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6326#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6327//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 6328#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6329#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6330//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 6331#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6332#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6333#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6334#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6335//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 6336#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6337#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6338//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 6339#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6340#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6341#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6342#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6343//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 6344#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6345#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6346//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 6347#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6348#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6349#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6350#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6351//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 6352#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6353#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6354//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 6355#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6356#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6357#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6358#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6359//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 6360#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6361#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6362//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 6363#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6364#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6365#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6366#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6367//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 6368#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6369#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6370//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 6371#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6372#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6373#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6374#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6375//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 6376#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6377#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6378//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 6379#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6380#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6381#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6382#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6383//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 6384#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6385#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6386//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 6387#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6388#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6389#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6390#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6391//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 6392#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6393#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6394//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 6395#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6396#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6397#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6398#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6399//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 6400#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6401#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6402//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 6403#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6404#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6405#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6406#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6407//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 6408#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6409#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6410//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 6411#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6412#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6413//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 6414#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6415#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6416//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 6417#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6418#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6419//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 6420#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6421#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6422//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 6423#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6424#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6425//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 6426#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6427#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6428//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 6429#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6430#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6431//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 6432#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6433#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6434//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 6435#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6436#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6437//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 6438#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6439#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6440//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 6441#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6442#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6443//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 6444#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6445#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6446//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 6447#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6448#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6449//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 6450#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6451#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6452//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 6453#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6454#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6455//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 6456#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6457#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6458//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 6459#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6460#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6461//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 6462#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6463#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6464//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 6465#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6466#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6467//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 6468#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6469#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6470//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 6471#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6472#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6473//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 6474#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6475#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6476//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 6477#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6478#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6479//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 6480#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6481#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6482//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 6483#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6484#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6485//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 6486#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6487#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6488//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 6489#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6490#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6491//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 6492#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6493#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6494//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 6495#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6496#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6497//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 6498#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6499#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6500//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 6501#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6502#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6503//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 6504#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6505#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6506//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 6507#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6508#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6509//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 6510#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6511#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6512//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 6513#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6514#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6515//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 6516#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6517#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6518//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 6519#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6520#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6521//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 6522#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6523#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6524//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 6525#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6526#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6527//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 6528#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6529#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6530//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 6531#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6532#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6533//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 6534#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6535#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6536//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 6537#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6538#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6539//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 6540#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6541#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6542//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 6543#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6544#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6545//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 6546#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6547#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6548//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 6549#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6550#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6551//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 6552#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6553#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6554//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 6555#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6556#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6557//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 6558#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6559#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6560//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 6561#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6562#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6563//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 6564#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6565#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6566//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 6567#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6568#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6569//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 6570#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6571#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6572//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 6573#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6574#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6575//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 6576#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6577#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6578//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 6579#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6580#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6581//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 6582#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6583#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6584//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 6585#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6586#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6587//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 6588#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6589#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6590//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 6591#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6592#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6593//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 6594#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6595#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6596//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 6597#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6598#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6599//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 6600#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6601#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6602//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 6603#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6604#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6605//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 6606#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6607#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6608//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 6609#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6610#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6611//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 6612#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6613#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6614//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 6615#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6616#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6617//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 6618#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6619#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6620//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 6621#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6622#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6623//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 6624#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6625#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6626//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 6627#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6628#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6629//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 6630#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6631#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6632//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 6633#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6634#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6635//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 6636#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6637#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6638//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 6639#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6640#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6641//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 6642#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6643#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6644//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 6645#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6646#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6647//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 6648#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6649#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6650//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 6651#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6652#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6653//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 6654#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6655#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6656//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 6657#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6658#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6659//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 6660#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6661#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6662//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 6663#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6664#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6665//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 6666#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6667#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6668//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 6669#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6670#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6671//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 6672#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6673#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6674//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 6675#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6676#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6677//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 6678#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6679#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6680//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 6681#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6682#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6683//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 6684#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6685#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6686//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 6687#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6688#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6689//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 6690#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6691#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6692//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 6693#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6694#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6695//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 6696#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6697#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6698//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6699#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6700#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6701#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6702#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6703#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6704#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6705//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6706#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6707#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6708#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6709#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6710#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6711#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6712//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6713#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6714#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6715#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6716#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6717#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6718#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6719//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6720#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6721#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6722#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6723#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6724#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6725#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6726//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6727#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6728#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6729#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6730#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6731#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6732#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6733//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6734#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6735#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6736#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6737#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6738#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6739#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6740//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6741#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6742#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6743#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6744#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6745#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6746#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6747//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6748#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6749#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6750#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6751#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6752#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6753#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6754//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6755#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6756#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6757#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6758#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6759#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6760#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6761//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6762#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6763#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6764#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6765#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6766#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6767#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6768//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6769#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6770#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6771#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6772#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6773#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6774#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6775//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6776#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6777#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6778#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6779#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6780#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6781#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6782//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6783#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6784#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6785#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6786#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6787#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6788#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6789//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6790#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6791#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6792#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6793#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6794#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6795#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6796//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6797#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6798#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6799#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6800#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6801#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6802#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6803//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6804#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6805#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6806#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6807#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6808#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6809#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6810//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6811#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6812#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6813#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6814#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6815#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6816#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6817 6818 6819// addressBlock: mmhub_mmutcl2_mmvml2pldec 6820//MMMC_VM_L2_PERFCOUNTER0_CFG 6821#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6822#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6823#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6824#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6825#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6826#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6827#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6828#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6829#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6830#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6831//MMMC_VM_L2_PERFCOUNTER1_CFG 6832#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6833#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6834#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6835#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6836#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6837#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6838#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6839#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6840#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6841#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6842//MMMC_VM_L2_PERFCOUNTER2_CFG 6843#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6844#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6845#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6846#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6847#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6848#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6849#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6850#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6851#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6852#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6853//MMMC_VM_L2_PERFCOUNTER3_CFG 6854#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 6855#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 6856#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 6857#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 6858#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 6859#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 6860#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 6861#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 6862#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 6863#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 6864//MMMC_VM_L2_PERFCOUNTER4_CFG 6865#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 6866#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 6867#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 6868#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 6869#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 6870#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 6871#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 6872#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 6873#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 6874#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 6875//MMMC_VM_L2_PERFCOUNTER5_CFG 6876#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 6877#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 6878#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 6879#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 6880#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 6881#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 6882#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 6883#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 6884#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 6885#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 6886//MMMC_VM_L2_PERFCOUNTER6_CFG 6887#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 6888#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 6889#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 6890#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 6891#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 6892#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 6893#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 6894#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 6895#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 6896#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 6897//MMMC_VM_L2_PERFCOUNTER7_CFG 6898#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 6899#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 6900#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 6901#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 6902#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 6903#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 6904#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 6905#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 6906#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 6907#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 6908//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 6909#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6910#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6911#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6912#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6913#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6914#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6915#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6916#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6917#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6918#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6919#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6920#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6921//MMUTCL2_PERFCOUNTER0_CFG 6922#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6923#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6924#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6925#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6926#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6927#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6928#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6929#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6930#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6931#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6932//MMUTCL2_PERFCOUNTER1_CFG 6933#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6934#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6935#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6936#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6937#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6938#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6939#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6940#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6941#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6942#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6943//MMUTCL2_PERFCOUNTER2_CFG 6944#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6945#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6946#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6947#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6948#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6949#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6950#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6951#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6952#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6953#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6954//MMUTCL2_PERFCOUNTER3_CFG 6955#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 6956#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 6957#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 6958#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 6959#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 6960#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 6961#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 6962#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 6963#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 6964#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 6965//MMUTCL2_PERFCOUNTER_RSLT_CNTL 6966#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6967#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6968#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6969#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6970#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6971#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6972#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6973#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6974#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6975#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6976#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6977#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6978 6979 6980// addressBlock: mmhub_mmutcl2_mmvml2prdec 6981//MMMC_VM_L2_PERFCOUNTER_LO 6982#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6983#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6984//MMMC_VM_L2_PERFCOUNTER_HI 6985#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6986#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6987#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6988#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6989//MMUTCL2_PERFCOUNTER_LO 6990#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6991#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6992//MMUTCL2_PERFCOUNTER_HI 6993#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6994#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6995#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6996#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6997 6998 6999// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 7000//MMMC_VM_FB_SIZE_OFFSET_VF0 7001#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 7002#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 7003#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 7004#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 7005//MMMC_VM_FB_SIZE_OFFSET_VF1 7006#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 7007#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 7008#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 7009#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 7010//MMMC_VM_FB_SIZE_OFFSET_VF2 7011#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 7012#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 7013#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 7014#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 7015//MMMC_VM_FB_SIZE_OFFSET_VF3 7016#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 7017#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 7018#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 7019#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 7020//MMMC_VM_FB_SIZE_OFFSET_VF4 7021#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 7022#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 7023#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 7024#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 7025//MMMC_VM_FB_SIZE_OFFSET_VF5 7026#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 7027#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 7028#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 7029#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 7030//MMMC_VM_FB_SIZE_OFFSET_VF6 7031#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 7032#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 7033#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 7034#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 7035//MMMC_VM_FB_SIZE_OFFSET_VF7 7036#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 7037#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 7038#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 7039#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 7040//MMMC_VM_FB_SIZE_OFFSET_VF8 7041#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 7042#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 7043#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 7044#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 7045//MMMC_VM_FB_SIZE_OFFSET_VF9 7046#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 7047#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 7048#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 7049#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 7050//MMMC_VM_FB_SIZE_OFFSET_VF10 7051#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 7052#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 7053#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 7054#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 7055//MMMC_VM_FB_SIZE_OFFSET_VF11 7056#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 7057#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 7058#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 7059#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 7060//MMMC_VM_FB_SIZE_OFFSET_VF12 7061#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 7062#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 7063#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 7064#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 7065//MMMC_VM_FB_SIZE_OFFSET_VF13 7066#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 7067#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 7068#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 7069#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 7070//MMMC_VM_FB_SIZE_OFFSET_VF14 7071#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 7072#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 7073#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 7074#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 7075//MMMC_VM_FB_SIZE_OFFSET_VF15 7076#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 7077#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 7078#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 7079#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 7080 7081 7082// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 7083//MMMC_VM_FB_OFFSET 7084#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 7085#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 7086//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 7087#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 7088#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 7089//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 7090#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 7091#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 7092//MMMC_VM_STEERING 7093#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 7094#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 7095//MMMC_MEM_POWER_LS 7096#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 7097#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 7098#define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 7099#define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 7100//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START 7101#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 7102#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7103//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END 7104#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 7105#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7106//MMMC_VM_LOCAL_SYSMEM_ADDRESS_START 7107#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 7108#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7109//MMMC_VM_LOCAL_SYSMEM_ADDRESS_END 7110#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 7111#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7112//MMMC_VM_APT_CNTL 7113#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 7114#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 7115#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 7116#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 7117#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 7118#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 7119#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 7120#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 7121#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL 7122#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L 7123#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L 7124#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L 7125//MMMC_VM_LOCAL_FB_ADDRESS_START 7126#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 7127#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7128//MMMC_VM_LOCAL_FB_ADDRESS_END 7129#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 7130#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7131//MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 7132#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 7133#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 7134//MMUTCL2_CGTT_CLK_CTRL 7135#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7136#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 7137#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 7138#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 7139#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 7140#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 7141#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 7142#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 7143#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 7144#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 7145//MMUTCL2_CGTT_BUSY_CTRL 7146#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 7147#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 7148#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 7149#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 7150//MMMC_VM_FB_NOALLOC_CNTL 7151#define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT 0x0 7152#define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT 0x1 7153#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT 0x2 7154#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT 0x3 7155#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT 0x4 7156#define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK 0x00000001L 7157#define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK 0x00000002L 7158#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK 0x00000004L 7159#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK 0x00000008L 7160#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK 0x00000010L 7161//MMUTCL2_HARVEST_BYPASS_GROUPS 7162#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 7163#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL 7164//MMUTCL2_GROUP_RET_FAULT_STATUS 7165#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 7166#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL 7167 7168 7169// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 7170//MMMC_VM_FB_LOCATION_BASE 7171#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 7172#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 7173//MMMC_VM_FB_LOCATION_TOP 7174#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 7175#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 7176//MMMC_VM_AGP_TOP 7177#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 7178#define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 7179//MMMC_VM_AGP_BOT 7180#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 7181#define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 7182//MMMC_VM_AGP_BASE 7183#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 7184#define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 7185//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR 7186#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 7187#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7188//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 7189#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 7190#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7191//MMMC_VM_MX_L1_TLB_CNTL 7192#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 7193#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 7194#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 7195#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 7196#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 7197#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 7198#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 7199#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 7200#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 7201#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 7202#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 7203#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L 7204 7205 7206// addressBlock: mmhub_mmutcl2_mmvml2pspdec 7207//MMUTCL2_TRANSLATION_BYPASS_BY_VMID 7208#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 7209#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 7210#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL 7211#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L 7212//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 7213#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 7214#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L 7215//MMUTC_TRANSLATION_FAULT_CNTL0 7216#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 7217#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL 7218//MMUTC_TRANSLATION_FAULT_CNTL1 7219#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 7220#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 7221#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 7222#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 7223#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL 7224#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L 7225#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L 7226#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L 7227 7228#endif 7229