1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _mmhub_1_8_0_OFFSET_HEADER 24#define _mmhub_1_8_0_OFFSET_HEADER 25 26 27 28// addressBlock: aid_mmhub_dagb_dagbdec0 29// base address: 0x60000 30#define regDAGB0_RDCLI0 0x0000 31#define regDAGB0_RDCLI0_BASE_IDX 0 32#define regDAGB0_RDCLI1 0x0001 33#define regDAGB0_RDCLI1_BASE_IDX 0 34#define regDAGB0_RDCLI2 0x0002 35#define regDAGB0_RDCLI2_BASE_IDX 0 36#define regDAGB0_RDCLI3 0x0003 37#define regDAGB0_RDCLI3_BASE_IDX 0 38#define regDAGB0_RDCLI4 0x0004 39#define regDAGB0_RDCLI4_BASE_IDX 0 40#define regDAGB0_RDCLI5 0x0005 41#define regDAGB0_RDCLI5_BASE_IDX 0 42#define regDAGB0_RDCLI6 0x0006 43#define regDAGB0_RDCLI6_BASE_IDX 0 44#define regDAGB0_RDCLI7 0x0007 45#define regDAGB0_RDCLI7_BASE_IDX 0 46#define regDAGB0_RDCLI8 0x0008 47#define regDAGB0_RDCLI8_BASE_IDX 0 48#define regDAGB0_RDCLI9 0x0009 49#define regDAGB0_RDCLI9_BASE_IDX 0 50#define regDAGB0_RDCLI10 0x000a 51#define regDAGB0_RDCLI10_BASE_IDX 0 52#define regDAGB0_RDCLI11 0x000b 53#define regDAGB0_RDCLI11_BASE_IDX 0 54#define regDAGB0_RDCLI12 0x000c 55#define regDAGB0_RDCLI12_BASE_IDX 0 56#define regDAGB0_RDCLI13 0x000d 57#define regDAGB0_RDCLI13_BASE_IDX 0 58#define regDAGB0_RDCLI14 0x000e 59#define regDAGB0_RDCLI14_BASE_IDX 0 60#define regDAGB0_RDCLI15 0x000f 61#define regDAGB0_RDCLI15_BASE_IDX 0 62#define regDAGB0_RD_CNTL 0x0010 63#define regDAGB0_RD_CNTL_BASE_IDX 0 64#define regDAGB0_RD_GMI_CNTL 0x0011 65#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0 66#define regDAGB0_RD_ADDR_DAGB 0x0012 67#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0 68#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 69#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 70#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 71#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 72#define regDAGB0_RD_CGTT_CLK_CTRL 0x0015 73#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 74#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 75#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 76#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 77#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 78#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 79#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 80#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 81#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 82#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a 83#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 84#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b 85#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 86#define regDAGB0_RD_VC0_CNTL 0x001c 87#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0 88#define regDAGB0_RD_VC1_CNTL 0x001d 89#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0 90#define regDAGB0_RD_VC2_CNTL 0x001e 91#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0 92#define regDAGB0_RD_VC3_CNTL 0x001f 93#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0 94#define regDAGB0_RD_VC4_CNTL 0x0020 95#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0 96#define regDAGB0_RD_VC5_CNTL 0x0021 97#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0 98#define regDAGB0_RD_VC6_CNTL 0x0022 99#define regDAGB0_RD_VC6_CNTL_BASE_IDX 0 100#define regDAGB0_RD_VC7_CNTL 0x0023 101#define regDAGB0_RD_VC7_CNTL_BASE_IDX 0 102#define regDAGB0_RD_CNTL_MISC 0x0024 103#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0 104#define regDAGB0_RD_TLB_CREDIT 0x0025 105#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0 106#define regDAGB0_RD_RDRET_CREDIT_CNTL 0x0026 107#define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 108#define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x0027 109#define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 110#define regDAGB0_RDCLI_ASK_PENDING 0x0028 111#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 112#define regDAGB0_RDCLI_GO_PENDING 0x0029 113#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 114#define regDAGB0_RDCLI_GBLSEND_PENDING 0x002a 115#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 116#define regDAGB0_RDCLI_TLB_PENDING 0x002b 117#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 118#define regDAGB0_RDCLI_OARB_PENDING 0x002c 119#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 120#define regDAGB0_RDCLI_OSD_PENDING 0x002d 121#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 122#define regDAGB0_RDCLI_NOALLOC_OVERRIDE 0x002e 123#define regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX 0 124#define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE 0x002f 125#define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 126#define regDAGB0_WRCLI0 0x0030 127#define regDAGB0_WRCLI0_BASE_IDX 0 128#define regDAGB0_WRCLI1 0x0031 129#define regDAGB0_WRCLI1_BASE_IDX 0 130#define regDAGB0_WRCLI2 0x0032 131#define regDAGB0_WRCLI2_BASE_IDX 0 132#define regDAGB0_WRCLI3 0x0033 133#define regDAGB0_WRCLI3_BASE_IDX 0 134#define regDAGB0_WRCLI4 0x0034 135#define regDAGB0_WRCLI4_BASE_IDX 0 136#define regDAGB0_WRCLI5 0x0035 137#define regDAGB0_WRCLI5_BASE_IDX 0 138#define regDAGB0_WRCLI6 0x0036 139#define regDAGB0_WRCLI6_BASE_IDX 0 140#define regDAGB0_WRCLI7 0x0037 141#define regDAGB0_WRCLI7_BASE_IDX 0 142#define regDAGB0_WRCLI8 0x0038 143#define regDAGB0_WRCLI8_BASE_IDX 0 144#define regDAGB0_WRCLI9 0x0039 145#define regDAGB0_WRCLI9_BASE_IDX 0 146#define regDAGB0_WRCLI10 0x003a 147#define regDAGB0_WRCLI10_BASE_IDX 0 148#define regDAGB0_WRCLI11 0x003b 149#define regDAGB0_WRCLI11_BASE_IDX 0 150#define regDAGB0_WRCLI12 0x003c 151#define regDAGB0_WRCLI12_BASE_IDX 0 152#define regDAGB0_WRCLI13 0x003d 153#define regDAGB0_WRCLI13_BASE_IDX 0 154#define regDAGB0_WRCLI14 0x003e 155#define regDAGB0_WRCLI14_BASE_IDX 0 156#define regDAGB0_WRCLI15 0x003f 157#define regDAGB0_WRCLI15_BASE_IDX 0 158#define regDAGB0_WR_CNTL 0x0040 159#define regDAGB0_WR_CNTL_BASE_IDX 0 160#define regDAGB0_WR_GMI_CNTL 0x0041 161#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0 162#define regDAGB0_WR_ADDR_DAGB 0x0042 163#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0 164#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0043 165#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 166#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0044 167#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 168#define regDAGB0_WR_CGTT_CLK_CTRL 0x0045 169#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 170#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0046 171#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 172#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0047 173#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 174#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0048 175#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 176#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0049 177#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 178#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x004a 179#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 180#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x004b 181#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 182#define regDAGB0_WR_DATA_DAGB 0x004c 183#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0 184#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x004d 185#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 186#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004e 187#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 188#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004f 189#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 190#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0050 191#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 192#define regDAGB0_WR_VC0_CNTL 0x0051 193#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0 194#define regDAGB0_WR_VC1_CNTL 0x0052 195#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0 196#define regDAGB0_WR_VC2_CNTL 0x0053 197#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0 198#define regDAGB0_WR_VC3_CNTL 0x0054 199#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0 200#define regDAGB0_WR_VC4_CNTL 0x0055 201#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0 202#define regDAGB0_WR_VC5_CNTL 0x0056 203#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0 204#define regDAGB0_WR_VC6_CNTL 0x0057 205#define regDAGB0_WR_VC6_CNTL_BASE_IDX 0 206#define regDAGB0_WR_VC7_CNTL 0x0058 207#define regDAGB0_WR_VC7_CNTL_BASE_IDX 0 208#define regDAGB0_WR_CNTL_MISC 0x0059 209#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0 210#define regDAGB0_WR_TLB_CREDIT 0x005a 211#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0 212#define regDAGB0_WR_DATA_CREDIT 0x005b 213#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0 214#define regDAGB0_WR_MISC_CREDIT 0x005c 215#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0 216#define regDAGB0_WR_OSD_CREDIT_CNTL1 0x005d 217#define regDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 218#define regDAGB0_WR_OSD_CREDIT_CNTL2 0x005e 219#define regDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 220#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x005f 221#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 222#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x0060 223#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 224#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x0061 225#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 226#define regDAGB0_WRCLI_ASK_PENDING 0x0062 227#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 228#define regDAGB0_WRCLI_GO_PENDING 0x0063 229#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 230#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0064 231#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 232#define regDAGB0_WRCLI_TLB_PENDING 0x0065 233#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 234#define regDAGB0_WRCLI_OARB_PENDING 0x0066 235#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 236#define regDAGB0_WRCLI_OSD_PENDING 0x0067 237#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 238#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0068 239#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 240#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x0069 241#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 242#define regDAGB0_WRCLI_NOALLOC_OVERRIDE 0x006a 243#define regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX 0 244#define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE 0x006b 245#define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 246#define regDAGB0_DAGB_DLY 0x006c 247#define regDAGB0_DAGB_DLY_BASE_IDX 0 248#define regDAGB0_CNTL_MISC 0x006d 249#define regDAGB0_CNTL_MISC_BASE_IDX 0 250#define regDAGB0_CNTL_MISC2 0x006e 251#define regDAGB0_CNTL_MISC2_BASE_IDX 0 252#define regDAGB0_FATAL_ERROR_CNTL 0x006f 253#define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0 254#define regDAGB0_FATAL_ERROR_CLEAR 0x0070 255#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0 256#define regDAGB0_FATAL_ERROR_STATUS0 0x0071 257#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0 258#define regDAGB0_FATAL_ERROR_STATUS1 0x0072 259#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0 260#define regDAGB0_FATAL_ERROR_STATUS2 0x0073 261#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0 262#define regDAGB0_FATAL_ERROR_STATUS3 0x0074 263#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0 264#define regDAGB0_FIFO_EMPTY 0x0075 265#define regDAGB0_FIFO_EMPTY_BASE_IDX 0 266#define regDAGB0_FIFO_FULL 0x0076 267#define regDAGB0_FIFO_FULL_BASE_IDX 0 268#define regDAGB0_WR_CREDITS_FULL 0x0077 269#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0 270#define regDAGB0_RD_CREDITS_FULL 0x0078 271#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0 272#define regDAGB0_PERFCOUNTER_LO 0x0079 273#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0 274#define regDAGB0_PERFCOUNTER_HI 0x007a 275#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0 276#define regDAGB0_PERFCOUNTER0_CFG 0x007b 277#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 278#define regDAGB0_PERFCOUNTER1_CFG 0x007c 279#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 280#define regDAGB0_PERFCOUNTER2_CFG 0x007d 281#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 282#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x007e 283#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 284#define regDAGB0_L1TLB_REG_RW 0x007f 285#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0 286 287 288// addressBlock: aid_mmhub_dagb_dagbdec1 289// base address: 0x60200 290#define regDAGB1_RDCLI0 0x0080 291#define regDAGB1_RDCLI0_BASE_IDX 0 292#define regDAGB1_RDCLI1 0x0081 293#define regDAGB1_RDCLI1_BASE_IDX 0 294#define regDAGB1_RDCLI2 0x0082 295#define regDAGB1_RDCLI2_BASE_IDX 0 296#define regDAGB1_RDCLI3 0x0083 297#define regDAGB1_RDCLI3_BASE_IDX 0 298#define regDAGB1_RDCLI4 0x0084 299#define regDAGB1_RDCLI4_BASE_IDX 0 300#define regDAGB1_RDCLI5 0x0085 301#define regDAGB1_RDCLI5_BASE_IDX 0 302#define regDAGB1_RDCLI6 0x0086 303#define regDAGB1_RDCLI6_BASE_IDX 0 304#define regDAGB1_RDCLI7 0x0087 305#define regDAGB1_RDCLI7_BASE_IDX 0 306#define regDAGB1_RDCLI8 0x0088 307#define regDAGB1_RDCLI8_BASE_IDX 0 308#define regDAGB1_RDCLI9 0x0089 309#define regDAGB1_RDCLI9_BASE_IDX 0 310#define regDAGB1_RDCLI10 0x008a 311#define regDAGB1_RDCLI10_BASE_IDX 0 312#define regDAGB1_RDCLI11 0x008b 313#define regDAGB1_RDCLI11_BASE_IDX 0 314#define regDAGB1_RDCLI12 0x008c 315#define regDAGB1_RDCLI12_BASE_IDX 0 316#define regDAGB1_RDCLI13 0x008d 317#define regDAGB1_RDCLI13_BASE_IDX 0 318#define regDAGB1_RDCLI14 0x008e 319#define regDAGB1_RDCLI14_BASE_IDX 0 320#define regDAGB1_RDCLI15 0x008f 321#define regDAGB1_RDCLI15_BASE_IDX 0 322#define regDAGB1_RD_CNTL 0x0090 323#define regDAGB1_RD_CNTL_BASE_IDX 0 324#define regDAGB1_RD_GMI_CNTL 0x0091 325#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0 326#define regDAGB1_RD_ADDR_DAGB 0x0092 327#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0 328#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 329#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 330#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 331#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 332#define regDAGB1_RD_CGTT_CLK_CTRL 0x0095 333#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 334#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 335#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 336#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 337#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 338#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 339#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 340#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 341#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 342#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a 343#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 344#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b 345#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 346#define regDAGB1_RD_VC0_CNTL 0x009c 347#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0 348#define regDAGB1_RD_VC1_CNTL 0x009d 349#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0 350#define regDAGB1_RD_VC2_CNTL 0x009e 351#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0 352#define regDAGB1_RD_VC3_CNTL 0x009f 353#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0 354#define regDAGB1_RD_VC4_CNTL 0x00a0 355#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0 356#define regDAGB1_RD_VC5_CNTL 0x00a1 357#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0 358#define regDAGB1_RD_VC6_CNTL 0x00a2 359#define regDAGB1_RD_VC6_CNTL_BASE_IDX 0 360#define regDAGB1_RD_VC7_CNTL 0x00a3 361#define regDAGB1_RD_VC7_CNTL_BASE_IDX 0 362#define regDAGB1_RD_CNTL_MISC 0x00a4 363#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0 364#define regDAGB1_RD_TLB_CREDIT 0x00a5 365#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0 366#define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00a6 367#define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 368#define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00a7 369#define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 370#define regDAGB1_RDCLI_ASK_PENDING 0x00a8 371#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 372#define regDAGB1_RDCLI_GO_PENDING 0x00a9 373#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 374#define regDAGB1_RDCLI_GBLSEND_PENDING 0x00aa 375#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 376#define regDAGB1_RDCLI_TLB_PENDING 0x00ab 377#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 378#define regDAGB1_RDCLI_OARB_PENDING 0x00ac 379#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 380#define regDAGB1_RDCLI_OSD_PENDING 0x00ad 381#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 382#define regDAGB1_RDCLI_NOALLOC_OVERRIDE 0x00ae 383#define regDAGB1_RDCLI_NOALLOC_OVERRIDE_BASE_IDX 0 384#define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE 0x00af 385#define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 386#define regDAGB1_WRCLI0 0x00b0 387#define regDAGB1_WRCLI0_BASE_IDX 0 388#define regDAGB1_WRCLI1 0x00b1 389#define regDAGB1_WRCLI1_BASE_IDX 0 390#define regDAGB1_WRCLI2 0x00b2 391#define regDAGB1_WRCLI2_BASE_IDX 0 392#define regDAGB1_WRCLI3 0x00b3 393#define regDAGB1_WRCLI3_BASE_IDX 0 394#define regDAGB1_WRCLI4 0x00b4 395#define regDAGB1_WRCLI4_BASE_IDX 0 396#define regDAGB1_WRCLI5 0x00b5 397#define regDAGB1_WRCLI5_BASE_IDX 0 398#define regDAGB1_WRCLI6 0x00b6 399#define regDAGB1_WRCLI6_BASE_IDX 0 400#define regDAGB1_WRCLI7 0x00b7 401#define regDAGB1_WRCLI7_BASE_IDX 0 402#define regDAGB1_WRCLI8 0x00b8 403#define regDAGB1_WRCLI8_BASE_IDX 0 404#define regDAGB1_WRCLI9 0x00b9 405#define regDAGB1_WRCLI9_BASE_IDX 0 406#define regDAGB1_WRCLI10 0x00ba 407#define regDAGB1_WRCLI10_BASE_IDX 0 408#define regDAGB1_WRCLI11 0x00bb 409#define regDAGB1_WRCLI11_BASE_IDX 0 410#define regDAGB1_WRCLI12 0x00bc 411#define regDAGB1_WRCLI12_BASE_IDX 0 412#define regDAGB1_WRCLI13 0x00bd 413#define regDAGB1_WRCLI13_BASE_IDX 0 414#define regDAGB1_WRCLI14 0x00be 415#define regDAGB1_WRCLI14_BASE_IDX 0 416#define regDAGB1_WRCLI15 0x00bf 417#define regDAGB1_WRCLI15_BASE_IDX 0 418#define regDAGB1_WR_CNTL 0x00c0 419#define regDAGB1_WR_CNTL_BASE_IDX 0 420#define regDAGB1_WR_GMI_CNTL 0x00c1 421#define regDAGB1_WR_GMI_CNTL_BASE_IDX 0 422#define regDAGB1_WR_ADDR_DAGB 0x00c2 423#define regDAGB1_WR_ADDR_DAGB_BASE_IDX 0 424#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00c3 425#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 426#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c4 427#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 428#define regDAGB1_WR_CGTT_CLK_CTRL 0x00c5 429#define regDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0 430#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c6 431#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 432#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c7 433#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 434#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c8 435#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 436#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c9 437#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 438#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00ca 439#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 440#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00cb 441#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 442#define regDAGB1_WR_DATA_DAGB 0x00cc 443#define regDAGB1_WR_DATA_DAGB_BASE_IDX 0 444#define regDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00cd 445#define regDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 446#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ce 447#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 448#define regDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cf 449#define regDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 450#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00d0 451#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 452#define regDAGB1_WR_VC0_CNTL 0x00d1 453#define regDAGB1_WR_VC0_CNTL_BASE_IDX 0 454#define regDAGB1_WR_VC1_CNTL 0x00d2 455#define regDAGB1_WR_VC1_CNTL_BASE_IDX 0 456#define regDAGB1_WR_VC2_CNTL 0x00d3 457#define regDAGB1_WR_VC2_CNTL_BASE_IDX 0 458#define regDAGB1_WR_VC3_CNTL 0x00d4 459#define regDAGB1_WR_VC3_CNTL_BASE_IDX 0 460#define regDAGB1_WR_VC4_CNTL 0x00d5 461#define regDAGB1_WR_VC4_CNTL_BASE_IDX 0 462#define regDAGB1_WR_VC5_CNTL 0x00d6 463#define regDAGB1_WR_VC5_CNTL_BASE_IDX 0 464#define regDAGB1_WR_VC6_CNTL 0x00d7 465#define regDAGB1_WR_VC6_CNTL_BASE_IDX 0 466#define regDAGB1_WR_VC7_CNTL 0x00d8 467#define regDAGB1_WR_VC7_CNTL_BASE_IDX 0 468#define regDAGB1_WR_CNTL_MISC 0x00d9 469#define regDAGB1_WR_CNTL_MISC_BASE_IDX 0 470#define regDAGB1_WR_TLB_CREDIT 0x00da 471#define regDAGB1_WR_TLB_CREDIT_BASE_IDX 0 472#define regDAGB1_WR_DATA_CREDIT 0x00db 473#define regDAGB1_WR_DATA_CREDIT_BASE_IDX 0 474#define regDAGB1_WR_MISC_CREDIT 0x00dc 475#define regDAGB1_WR_MISC_CREDIT_BASE_IDX 0 476#define regDAGB1_WR_OSD_CREDIT_CNTL1 0x00dd 477#define regDAGB1_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 478#define regDAGB1_WR_OSD_CREDIT_CNTL2 0x00de 479#define regDAGB1_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 480#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x00df 481#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 482#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE 0x00e0 483#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 484#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00e1 485#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 486#define regDAGB1_WRCLI_ASK_PENDING 0x00e2 487#define regDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0 488#define regDAGB1_WRCLI_GO_PENDING 0x00e3 489#define regDAGB1_WRCLI_GO_PENDING_BASE_IDX 0 490#define regDAGB1_WRCLI_GBLSEND_PENDING 0x00e4 491#define regDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0 492#define regDAGB1_WRCLI_TLB_PENDING 0x00e5 493#define regDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0 494#define regDAGB1_WRCLI_OARB_PENDING 0x00e6 495#define regDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0 496#define regDAGB1_WRCLI_OSD_PENDING 0x00e7 497#define regDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0 498#define regDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e8 499#define regDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 500#define regDAGB1_WRCLI_DBUS_GO_PENDING 0x00e9 501#define regDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 502#define regDAGB1_DAGB_DLY 0x00ec 503#define regDAGB1_DAGB_DLY_BASE_IDX 0 504#define regDAGB1_CNTL_MISC 0x00ed 505#define regDAGB1_CNTL_MISC_BASE_IDX 0 506#define regDAGB1_CNTL_MISC2 0x00ee 507#define regDAGB1_CNTL_MISC2_BASE_IDX 0 508#define regDAGB1_FATAL_ERROR_CNTL 0x00ef 509#define regDAGB1_FATAL_ERROR_CNTL_BASE_IDX 0 510#define regDAGB1_FATAL_ERROR_CLEAR 0x00f0 511#define regDAGB1_FATAL_ERROR_CLEAR_BASE_IDX 0 512#define regDAGB1_FATAL_ERROR_STATUS0 0x00f1 513#define regDAGB1_FATAL_ERROR_STATUS0_BASE_IDX 0 514#define regDAGB1_FATAL_ERROR_STATUS1 0x00f2 515#define regDAGB1_FATAL_ERROR_STATUS1_BASE_IDX 0 516#define regDAGB1_FATAL_ERROR_STATUS2 0x00f3 517#define regDAGB1_FATAL_ERROR_STATUS2_BASE_IDX 0 518#define regDAGB1_FATAL_ERROR_STATUS3 0x00f4 519#define regDAGB1_FATAL_ERROR_STATUS3_BASE_IDX 0 520#define regDAGB1_FIFO_EMPTY 0x00f5 521#define regDAGB1_FIFO_EMPTY_BASE_IDX 0 522#define regDAGB1_FIFO_FULL 0x00f6 523#define regDAGB1_FIFO_FULL_BASE_IDX 0 524#define regDAGB1_WR_CREDITS_FULL 0x00f7 525#define regDAGB1_WR_CREDITS_FULL_BASE_IDX 0 526#define regDAGB1_RD_CREDITS_FULL 0x00f8 527#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0 528#define regDAGB1_PERFCOUNTER_LO 0x00f9 529#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0 530#define regDAGB1_PERFCOUNTER_HI 0x00fa 531#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0 532#define regDAGB1_PERFCOUNTER0_CFG 0x00fb 533#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 534#define regDAGB1_PERFCOUNTER1_CFG 0x00fc 535#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 536#define regDAGB1_PERFCOUNTER2_CFG 0x00fd 537#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 538#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x00fe 539#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 540#define regDAGB1_L1TLB_REG_RW 0x00ff 541#define regDAGB1_L1TLB_REG_RW_BASE_IDX 0 542 543 544// addressBlock: aid_mmhub_dagb_dagbdec2 545// base address: 0x60400 546#define regDAGB2_RDCLI0 0x0100 547#define regDAGB2_RDCLI0_BASE_IDX 0 548#define regDAGB2_RDCLI1 0x0101 549#define regDAGB2_RDCLI1_BASE_IDX 0 550#define regDAGB2_RDCLI2 0x0102 551#define regDAGB2_RDCLI2_BASE_IDX 0 552#define regDAGB2_RDCLI3 0x0103 553#define regDAGB2_RDCLI3_BASE_IDX 0 554#define regDAGB2_RDCLI4 0x0104 555#define regDAGB2_RDCLI4_BASE_IDX 0 556#define regDAGB2_RDCLI5 0x0105 557#define regDAGB2_RDCLI5_BASE_IDX 0 558#define regDAGB2_RDCLI6 0x0106 559#define regDAGB2_RDCLI6_BASE_IDX 0 560#define regDAGB2_RDCLI7 0x0107 561#define regDAGB2_RDCLI7_BASE_IDX 0 562#define regDAGB2_RDCLI8 0x0108 563#define regDAGB2_RDCLI8_BASE_IDX 0 564#define regDAGB2_RDCLI9 0x0109 565#define regDAGB2_RDCLI9_BASE_IDX 0 566#define regDAGB2_RDCLI10 0x010a 567#define regDAGB2_RDCLI10_BASE_IDX 0 568#define regDAGB2_RDCLI11 0x010b 569#define regDAGB2_RDCLI11_BASE_IDX 0 570#define regDAGB2_RDCLI12 0x010c 571#define regDAGB2_RDCLI12_BASE_IDX 0 572#define regDAGB2_RDCLI13 0x010d 573#define regDAGB2_RDCLI13_BASE_IDX 0 574#define regDAGB2_RDCLI14 0x010e 575#define regDAGB2_RDCLI14_BASE_IDX 0 576#define regDAGB2_RDCLI15 0x010f 577#define regDAGB2_RDCLI15_BASE_IDX 0 578#define regDAGB2_RD_CNTL 0x0110 579#define regDAGB2_RD_CNTL_BASE_IDX 0 580#define regDAGB2_RD_GMI_CNTL 0x0111 581#define regDAGB2_RD_GMI_CNTL_BASE_IDX 0 582#define regDAGB2_RD_ADDR_DAGB 0x0112 583#define regDAGB2_RD_ADDR_DAGB_BASE_IDX 0 584#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113 585#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 586#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114 587#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 588#define regDAGB2_RD_CGTT_CLK_CTRL 0x0115 589#define regDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 0 590#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116 591#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 592#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117 593#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 594#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118 595#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 596#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119 597#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 598#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a 599#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 600#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b 601#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 602#define regDAGB2_RD_VC0_CNTL 0x011c 603#define regDAGB2_RD_VC0_CNTL_BASE_IDX 0 604#define regDAGB2_RD_VC1_CNTL 0x011d 605#define regDAGB2_RD_VC1_CNTL_BASE_IDX 0 606#define regDAGB2_RD_VC2_CNTL 0x011e 607#define regDAGB2_RD_VC2_CNTL_BASE_IDX 0 608#define regDAGB2_RD_VC3_CNTL 0x011f 609#define regDAGB2_RD_VC3_CNTL_BASE_IDX 0 610#define regDAGB2_RD_VC4_CNTL 0x0120 611#define regDAGB2_RD_VC4_CNTL_BASE_IDX 0 612#define regDAGB2_RD_VC5_CNTL 0x0121 613#define regDAGB2_RD_VC5_CNTL_BASE_IDX 0 614#define regDAGB2_RD_VC6_CNTL 0x0122 615#define regDAGB2_RD_VC6_CNTL_BASE_IDX 0 616#define regDAGB2_RD_VC7_CNTL 0x0123 617#define regDAGB2_RD_VC7_CNTL_BASE_IDX 0 618#define regDAGB2_RD_CNTL_MISC 0x0124 619#define regDAGB2_RD_CNTL_MISC_BASE_IDX 0 620#define regDAGB2_RD_TLB_CREDIT 0x0125 621#define regDAGB2_RD_TLB_CREDIT_BASE_IDX 0 622#define regDAGB2_RD_RDRET_CREDIT_CNTL 0x0126 623#define regDAGB2_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 624#define regDAGB2_RD_RDRET_CREDIT_CNTL2 0x0127 625#define regDAGB2_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 626#define regDAGB2_RDCLI_ASK_PENDING 0x0128 627#define regDAGB2_RDCLI_ASK_PENDING_BASE_IDX 0 628#define regDAGB2_RDCLI_GO_PENDING 0x0129 629#define regDAGB2_RDCLI_GO_PENDING_BASE_IDX 0 630#define regDAGB2_RDCLI_GBLSEND_PENDING 0x012a 631#define regDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 0 632#define regDAGB2_RDCLI_TLB_PENDING 0x012b 633#define regDAGB2_RDCLI_TLB_PENDING_BASE_IDX 0 634#define regDAGB2_RDCLI_OARB_PENDING 0x012c 635#define regDAGB2_RDCLI_OARB_PENDING_BASE_IDX 0 636#define regDAGB2_RDCLI_OSD_PENDING 0x012d 637#define regDAGB2_RDCLI_OSD_PENDING_BASE_IDX 0 638#define regDAGB2_WRCLI0 0x0130 639#define regDAGB2_WRCLI0_BASE_IDX 0 640#define regDAGB2_WRCLI1 0x0131 641#define regDAGB2_WRCLI1_BASE_IDX 0 642#define regDAGB2_WRCLI2 0x0132 643#define regDAGB2_WRCLI2_BASE_IDX 0 644#define regDAGB2_WRCLI3 0x0133 645#define regDAGB2_WRCLI3_BASE_IDX 0 646#define regDAGB2_WRCLI4 0x0134 647#define regDAGB2_WRCLI4_BASE_IDX 0 648#define regDAGB2_WRCLI5 0x0135 649#define regDAGB2_WRCLI5_BASE_IDX 0 650#define regDAGB2_WRCLI6 0x0136 651#define regDAGB2_WRCLI6_BASE_IDX 0 652#define regDAGB2_WRCLI7 0x0137 653#define regDAGB2_WRCLI7_BASE_IDX 0 654#define regDAGB2_WRCLI8 0x0138 655#define regDAGB2_WRCLI8_BASE_IDX 0 656#define regDAGB2_WRCLI9 0x0139 657#define regDAGB2_WRCLI9_BASE_IDX 0 658#define regDAGB2_WRCLI10 0x013a 659#define regDAGB2_WRCLI10_BASE_IDX 0 660#define regDAGB2_WRCLI11 0x013b 661#define regDAGB2_WRCLI11_BASE_IDX 0 662#define regDAGB2_WRCLI12 0x013c 663#define regDAGB2_WRCLI12_BASE_IDX 0 664#define regDAGB2_WRCLI13 0x013d 665#define regDAGB2_WRCLI13_BASE_IDX 0 666#define regDAGB2_WRCLI14 0x013e 667#define regDAGB2_WRCLI14_BASE_IDX 0 668#define regDAGB2_WRCLI15 0x013f 669#define regDAGB2_WRCLI15_BASE_IDX 0 670#define regDAGB2_WR_CNTL 0x0140 671#define regDAGB2_WR_CNTL_BASE_IDX 0 672#define regDAGB2_WR_GMI_CNTL 0x0141 673#define regDAGB2_WR_GMI_CNTL_BASE_IDX 0 674#define regDAGB2_WR_ADDR_DAGB 0x0142 675#define regDAGB2_WR_ADDR_DAGB_BASE_IDX 0 676#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x0143 677#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 678#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0144 679#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 680#define regDAGB2_WR_CGTT_CLK_CTRL 0x0145 681#define regDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 0 682#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0146 683#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 684#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0147 685#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 686#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0148 687#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 688#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0149 689#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 690#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x014a 691#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 692#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x014b 693#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 694#define regDAGB2_WR_DATA_DAGB 0x014c 695#define regDAGB2_WR_DATA_DAGB_BASE_IDX 0 696#define regDAGB2_WR_DATA_DAGB_MAX_BURST0 0x014d 697#define regDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 698#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014e 699#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 700#define regDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014f 701#define regDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 702#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x0150 703#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 704#define regDAGB2_WR_VC0_CNTL 0x0151 705#define regDAGB2_WR_VC0_CNTL_BASE_IDX 0 706#define regDAGB2_WR_VC1_CNTL 0x0152 707#define regDAGB2_WR_VC1_CNTL_BASE_IDX 0 708#define regDAGB2_WR_VC2_CNTL 0x0153 709#define regDAGB2_WR_VC2_CNTL_BASE_IDX 0 710#define regDAGB2_WR_VC3_CNTL 0x0154 711#define regDAGB2_WR_VC3_CNTL_BASE_IDX 0 712#define regDAGB2_WR_VC4_CNTL 0x0155 713#define regDAGB2_WR_VC4_CNTL_BASE_IDX 0 714#define regDAGB2_WR_VC5_CNTL 0x0156 715#define regDAGB2_WR_VC5_CNTL_BASE_IDX 0 716#define regDAGB2_WR_VC6_CNTL 0x0157 717#define regDAGB2_WR_VC6_CNTL_BASE_IDX 0 718#define regDAGB2_WR_VC7_CNTL 0x0158 719#define regDAGB2_WR_VC7_CNTL_BASE_IDX 0 720#define regDAGB2_WR_CNTL_MISC 0x0159 721#define regDAGB2_WR_CNTL_MISC_BASE_IDX 0 722#define regDAGB2_WR_TLB_CREDIT 0x015a 723#define regDAGB2_WR_TLB_CREDIT_BASE_IDX 0 724#define regDAGB2_WR_DATA_CREDIT 0x015b 725#define regDAGB2_WR_DATA_CREDIT_BASE_IDX 0 726#define regDAGB2_WR_MISC_CREDIT 0x015c 727#define regDAGB2_WR_MISC_CREDIT_BASE_IDX 0 728#define regDAGB2_WR_OSD_CREDIT_CNTL1 0x015d 729#define regDAGB2_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 730#define regDAGB2_WR_OSD_CREDIT_CNTL2 0x015e 731#define regDAGB2_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 732#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x015f 733#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 734#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE 0x0160 735#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 736#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x0161 737#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 738#define regDAGB2_WRCLI_ASK_PENDING 0x0162 739#define regDAGB2_WRCLI_ASK_PENDING_BASE_IDX 0 740#define regDAGB2_WRCLI_GO_PENDING 0x0163 741#define regDAGB2_WRCLI_GO_PENDING_BASE_IDX 0 742#define regDAGB2_WRCLI_GBLSEND_PENDING 0x0164 743#define regDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 0 744#define regDAGB2_WRCLI_TLB_PENDING 0x0165 745#define regDAGB2_WRCLI_TLB_PENDING_BASE_IDX 0 746#define regDAGB2_WRCLI_OARB_PENDING 0x0166 747#define regDAGB2_WRCLI_OARB_PENDING_BASE_IDX 0 748#define regDAGB2_WRCLI_OSD_PENDING 0x0167 749#define regDAGB2_WRCLI_OSD_PENDING_BASE_IDX 0 750#define regDAGB2_WRCLI_DBUS_ASK_PENDING 0x0168 751#define regDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 752#define regDAGB2_WRCLI_DBUS_GO_PENDING 0x0169 753#define regDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 754#define regDAGB2_DAGB_DLY 0x016c 755#define regDAGB2_DAGB_DLY_BASE_IDX 0 756#define regDAGB2_CNTL_MISC 0x016d 757#define regDAGB2_CNTL_MISC_BASE_IDX 0 758#define regDAGB2_CNTL_MISC2 0x016e 759#define regDAGB2_CNTL_MISC2_BASE_IDX 0 760#define regDAGB2_FATAL_ERROR_CNTL 0x016f 761#define regDAGB2_FATAL_ERROR_CNTL_BASE_IDX 0 762#define regDAGB2_FATAL_ERROR_CLEAR 0x0170 763#define regDAGB2_FATAL_ERROR_CLEAR_BASE_IDX 0 764#define regDAGB2_FATAL_ERROR_STATUS0 0x0171 765#define regDAGB2_FATAL_ERROR_STATUS0_BASE_IDX 0 766#define regDAGB2_FATAL_ERROR_STATUS1 0x0172 767#define regDAGB2_FATAL_ERROR_STATUS1_BASE_IDX 0 768#define regDAGB2_FATAL_ERROR_STATUS2 0x0173 769#define regDAGB2_FATAL_ERROR_STATUS2_BASE_IDX 0 770#define regDAGB2_FATAL_ERROR_STATUS3 0x0174 771#define regDAGB2_FATAL_ERROR_STATUS3_BASE_IDX 0 772#define regDAGB2_FIFO_EMPTY 0x0175 773#define regDAGB2_FIFO_EMPTY_BASE_IDX 0 774#define regDAGB2_FIFO_FULL 0x0176 775#define regDAGB2_FIFO_FULL_BASE_IDX 0 776#define regDAGB2_WR_CREDITS_FULL 0x0177 777#define regDAGB2_WR_CREDITS_FULL_BASE_IDX 0 778#define regDAGB2_RD_CREDITS_FULL 0x0178 779#define regDAGB2_RD_CREDITS_FULL_BASE_IDX 0 780#define regDAGB2_PERFCOUNTER_LO 0x0179 781#define regDAGB2_PERFCOUNTER_LO_BASE_IDX 0 782#define regDAGB2_PERFCOUNTER_HI 0x017a 783#define regDAGB2_PERFCOUNTER_HI_BASE_IDX 0 784#define regDAGB2_PERFCOUNTER0_CFG 0x017b 785#define regDAGB2_PERFCOUNTER0_CFG_BASE_IDX 0 786#define regDAGB2_PERFCOUNTER1_CFG 0x017c 787#define regDAGB2_PERFCOUNTER1_CFG_BASE_IDX 0 788#define regDAGB2_PERFCOUNTER2_CFG 0x017d 789#define regDAGB2_PERFCOUNTER2_CFG_BASE_IDX 0 790#define regDAGB2_PERFCOUNTER_RSLT_CNTL 0x017e 791#define regDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 792#define regDAGB2_L1TLB_REG_RW 0x017f 793#define regDAGB2_L1TLB_REG_RW_BASE_IDX 0 794 795 796// addressBlock: aid_mmhub_dagb_dagbdec3 797// base address: 0x60600 798#define regDAGB3_RDCLI0 0x0180 799#define regDAGB3_RDCLI0_BASE_IDX 0 800#define regDAGB3_RDCLI1 0x0181 801#define regDAGB3_RDCLI1_BASE_IDX 0 802#define regDAGB3_RDCLI2 0x0182 803#define regDAGB3_RDCLI2_BASE_IDX 0 804#define regDAGB3_RDCLI3 0x0183 805#define regDAGB3_RDCLI3_BASE_IDX 0 806#define regDAGB3_RDCLI4 0x0184 807#define regDAGB3_RDCLI4_BASE_IDX 0 808#define regDAGB3_RDCLI5 0x0185 809#define regDAGB3_RDCLI5_BASE_IDX 0 810#define regDAGB3_RDCLI6 0x0186 811#define regDAGB3_RDCLI6_BASE_IDX 0 812#define regDAGB3_RDCLI7 0x0187 813#define regDAGB3_RDCLI7_BASE_IDX 0 814#define regDAGB3_RDCLI8 0x0188 815#define regDAGB3_RDCLI8_BASE_IDX 0 816#define regDAGB3_RDCLI9 0x0189 817#define regDAGB3_RDCLI9_BASE_IDX 0 818#define regDAGB3_RDCLI10 0x018a 819#define regDAGB3_RDCLI10_BASE_IDX 0 820#define regDAGB3_RDCLI11 0x018b 821#define regDAGB3_RDCLI11_BASE_IDX 0 822#define regDAGB3_RDCLI12 0x018c 823#define regDAGB3_RDCLI12_BASE_IDX 0 824#define regDAGB3_RDCLI13 0x018d 825#define regDAGB3_RDCLI13_BASE_IDX 0 826#define regDAGB3_RDCLI14 0x018e 827#define regDAGB3_RDCLI14_BASE_IDX 0 828#define regDAGB3_RDCLI15 0x018f 829#define regDAGB3_RDCLI15_BASE_IDX 0 830#define regDAGB3_RD_CNTL 0x0190 831#define regDAGB3_RD_CNTL_BASE_IDX 0 832#define regDAGB3_RD_GMI_CNTL 0x0191 833#define regDAGB3_RD_GMI_CNTL_BASE_IDX 0 834#define regDAGB3_RD_ADDR_DAGB 0x0192 835#define regDAGB3_RD_ADDR_DAGB_BASE_IDX 0 836#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193 837#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 838#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194 839#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 840#define regDAGB3_RD_CGTT_CLK_CTRL 0x0195 841#define regDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 0 842#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196 843#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 844#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197 845#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 846#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198 847#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 848#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199 849#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 850#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a 851#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 852#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b 853#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 854#define regDAGB3_RD_VC0_CNTL 0x019c 855#define regDAGB3_RD_VC0_CNTL_BASE_IDX 0 856#define regDAGB3_RD_VC1_CNTL 0x019d 857#define regDAGB3_RD_VC1_CNTL_BASE_IDX 0 858#define regDAGB3_RD_VC2_CNTL 0x019e 859#define regDAGB3_RD_VC2_CNTL_BASE_IDX 0 860#define regDAGB3_RD_VC3_CNTL 0x019f 861#define regDAGB3_RD_VC3_CNTL_BASE_IDX 0 862#define regDAGB3_RD_VC4_CNTL 0x01a0 863#define regDAGB3_RD_VC4_CNTL_BASE_IDX 0 864#define regDAGB3_RD_VC5_CNTL 0x01a1 865#define regDAGB3_RD_VC5_CNTL_BASE_IDX 0 866#define regDAGB3_RD_VC6_CNTL 0x01a2 867#define regDAGB3_RD_VC6_CNTL_BASE_IDX 0 868#define regDAGB3_RD_VC7_CNTL 0x01a3 869#define regDAGB3_RD_VC7_CNTL_BASE_IDX 0 870#define regDAGB3_RD_CNTL_MISC 0x01a4 871#define regDAGB3_RD_CNTL_MISC_BASE_IDX 0 872#define regDAGB3_RD_TLB_CREDIT 0x01a5 873#define regDAGB3_RD_TLB_CREDIT_BASE_IDX 0 874#define regDAGB3_RD_RDRET_CREDIT_CNTL 0x01a6 875#define regDAGB3_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 876#define regDAGB3_RD_RDRET_CREDIT_CNTL2 0x01a7 877#define regDAGB3_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 878#define regDAGB3_RDCLI_ASK_PENDING 0x01a8 879#define regDAGB3_RDCLI_ASK_PENDING_BASE_IDX 0 880#define regDAGB3_RDCLI_GO_PENDING 0x01a9 881#define regDAGB3_RDCLI_GO_PENDING_BASE_IDX 0 882#define regDAGB3_RDCLI_GBLSEND_PENDING 0x01aa 883#define regDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 0 884#define regDAGB3_RDCLI_TLB_PENDING 0x01ab 885#define regDAGB3_RDCLI_TLB_PENDING_BASE_IDX 0 886#define regDAGB3_RDCLI_OARB_PENDING 0x01ac 887#define regDAGB3_RDCLI_OARB_PENDING_BASE_IDX 0 888#define regDAGB3_RDCLI_OSD_PENDING 0x01ad 889#define regDAGB3_RDCLI_OSD_PENDING_BASE_IDX 0 890#define regDAGB3_WRCLI0 0x01b0 891#define regDAGB3_WRCLI0_BASE_IDX 0 892#define regDAGB3_WRCLI1 0x01b1 893#define regDAGB3_WRCLI1_BASE_IDX 0 894#define regDAGB3_WRCLI2 0x01b2 895#define regDAGB3_WRCLI2_BASE_IDX 0 896#define regDAGB3_WRCLI3 0x01b3 897#define regDAGB3_WRCLI3_BASE_IDX 0 898#define regDAGB3_WRCLI4 0x01b4 899#define regDAGB3_WRCLI4_BASE_IDX 0 900#define regDAGB3_WRCLI5 0x01b5 901#define regDAGB3_WRCLI5_BASE_IDX 0 902#define regDAGB3_WRCLI6 0x01b6 903#define regDAGB3_WRCLI6_BASE_IDX 0 904#define regDAGB3_WRCLI7 0x01b7 905#define regDAGB3_WRCLI7_BASE_IDX 0 906#define regDAGB3_WRCLI8 0x01b8 907#define regDAGB3_WRCLI8_BASE_IDX 0 908#define regDAGB3_WRCLI9 0x01b9 909#define regDAGB3_WRCLI9_BASE_IDX 0 910#define regDAGB3_WRCLI10 0x01ba 911#define regDAGB3_WRCLI10_BASE_IDX 0 912#define regDAGB3_WRCLI11 0x01bb 913#define regDAGB3_WRCLI11_BASE_IDX 0 914#define regDAGB3_WRCLI12 0x01bc 915#define regDAGB3_WRCLI12_BASE_IDX 0 916#define regDAGB3_WRCLI13 0x01bd 917#define regDAGB3_WRCLI13_BASE_IDX 0 918#define regDAGB3_WRCLI14 0x01be 919#define regDAGB3_WRCLI14_BASE_IDX 0 920#define regDAGB3_WRCLI15 0x01bf 921#define regDAGB3_WRCLI15_BASE_IDX 0 922#define regDAGB3_WR_CNTL 0x01c0 923#define regDAGB3_WR_CNTL_BASE_IDX 0 924#define regDAGB3_WR_GMI_CNTL 0x01c1 925#define regDAGB3_WR_GMI_CNTL_BASE_IDX 0 926#define regDAGB3_WR_ADDR_DAGB 0x01c2 927#define regDAGB3_WR_ADDR_DAGB_BASE_IDX 0 928#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01c3 929#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 930#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c4 931#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 932#define regDAGB3_WR_CGTT_CLK_CTRL 0x01c5 933#define regDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 0 934#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c6 935#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 936#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c7 937#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 938#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c8 939#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 940#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c9 941#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 942#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01ca 943#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 944#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01cb 945#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 946#define regDAGB3_WR_DATA_DAGB 0x01cc 947#define regDAGB3_WR_DATA_DAGB_BASE_IDX 0 948#define regDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01cd 949#define regDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 950#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01ce 951#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 952#define regDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cf 953#define regDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 954#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01d0 955#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 956#define regDAGB3_WR_VC0_CNTL 0x01d1 957#define regDAGB3_WR_VC0_CNTL_BASE_IDX 0 958#define regDAGB3_WR_VC1_CNTL 0x01d2 959#define regDAGB3_WR_VC1_CNTL_BASE_IDX 0 960#define regDAGB3_WR_VC2_CNTL 0x01d3 961#define regDAGB3_WR_VC2_CNTL_BASE_IDX 0 962#define regDAGB3_WR_VC3_CNTL 0x01d4 963#define regDAGB3_WR_VC3_CNTL_BASE_IDX 0 964#define regDAGB3_WR_VC4_CNTL 0x01d5 965#define regDAGB3_WR_VC4_CNTL_BASE_IDX 0 966#define regDAGB3_WR_VC5_CNTL 0x01d6 967#define regDAGB3_WR_VC5_CNTL_BASE_IDX 0 968#define regDAGB3_WR_VC6_CNTL 0x01d7 969#define regDAGB3_WR_VC6_CNTL_BASE_IDX 0 970#define regDAGB3_WR_VC7_CNTL 0x01d8 971#define regDAGB3_WR_VC7_CNTL_BASE_IDX 0 972#define regDAGB3_WR_CNTL_MISC 0x01d9 973#define regDAGB3_WR_CNTL_MISC_BASE_IDX 0 974#define regDAGB3_WR_TLB_CREDIT 0x01da 975#define regDAGB3_WR_TLB_CREDIT_BASE_IDX 0 976#define regDAGB3_WR_DATA_CREDIT 0x01db 977#define regDAGB3_WR_DATA_CREDIT_BASE_IDX 0 978#define regDAGB3_WR_MISC_CREDIT 0x01dc 979#define regDAGB3_WR_MISC_CREDIT_BASE_IDX 0 980#define regDAGB3_WR_OSD_CREDIT_CNTL1 0x01dd 981#define regDAGB3_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 982#define regDAGB3_WR_OSD_CREDIT_CNTL2 0x01de 983#define regDAGB3_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 984#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x01df 985#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 986#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE 0x01e0 987#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 988#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x01e1 989#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 990#define regDAGB3_WRCLI_ASK_PENDING 0x01e2 991#define regDAGB3_WRCLI_ASK_PENDING_BASE_IDX 0 992#define regDAGB3_WRCLI_GO_PENDING 0x01e3 993#define regDAGB3_WRCLI_GO_PENDING_BASE_IDX 0 994#define regDAGB3_WRCLI_GBLSEND_PENDING 0x01e4 995#define regDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 0 996#define regDAGB3_WRCLI_TLB_PENDING 0x01e5 997#define regDAGB3_WRCLI_TLB_PENDING_BASE_IDX 0 998#define regDAGB3_WRCLI_OARB_PENDING 0x01e6 999#define regDAGB3_WRCLI_OARB_PENDING_BASE_IDX 0 1000#define regDAGB3_WRCLI_OSD_PENDING 0x01e7 1001#define regDAGB3_WRCLI_OSD_PENDING_BASE_IDX 0 1002#define regDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e8 1003#define regDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 1004#define regDAGB3_WRCLI_DBUS_GO_PENDING 0x01e9 1005#define regDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 1006#define regDAGB3_DAGB_DLY 0x01ec 1007#define regDAGB3_DAGB_DLY_BASE_IDX 0 1008#define regDAGB3_CNTL_MISC 0x01ed 1009#define regDAGB3_CNTL_MISC_BASE_IDX 0 1010#define regDAGB3_CNTL_MISC2 0x01ee 1011#define regDAGB3_CNTL_MISC2_BASE_IDX 0 1012#define regDAGB3_FATAL_ERROR_CNTL 0x01ef 1013#define regDAGB3_FATAL_ERROR_CNTL_BASE_IDX 0 1014#define regDAGB3_FATAL_ERROR_CLEAR 0x01f0 1015#define regDAGB3_FATAL_ERROR_CLEAR_BASE_IDX 0 1016#define regDAGB3_FATAL_ERROR_STATUS0 0x01f1 1017#define regDAGB3_FATAL_ERROR_STATUS0_BASE_IDX 0 1018#define regDAGB3_FATAL_ERROR_STATUS1 0x01f2 1019#define regDAGB3_FATAL_ERROR_STATUS1_BASE_IDX 0 1020#define regDAGB3_FATAL_ERROR_STATUS2 0x01f3 1021#define regDAGB3_FATAL_ERROR_STATUS2_BASE_IDX 0 1022#define regDAGB3_FATAL_ERROR_STATUS3 0x01f4 1023#define regDAGB3_FATAL_ERROR_STATUS3_BASE_IDX 0 1024#define regDAGB3_FIFO_EMPTY 0x01f5 1025#define regDAGB3_FIFO_EMPTY_BASE_IDX 0 1026#define regDAGB3_FIFO_FULL 0x01f6 1027#define regDAGB3_FIFO_FULL_BASE_IDX 0 1028#define regDAGB3_WR_CREDITS_FULL 0x01f7 1029#define regDAGB3_WR_CREDITS_FULL_BASE_IDX 0 1030#define regDAGB3_RD_CREDITS_FULL 0x01f8 1031#define regDAGB3_RD_CREDITS_FULL_BASE_IDX 0 1032#define regDAGB3_PERFCOUNTER_LO 0x01f9 1033#define regDAGB3_PERFCOUNTER_LO_BASE_IDX 0 1034#define regDAGB3_PERFCOUNTER_HI 0x01fa 1035#define regDAGB3_PERFCOUNTER_HI_BASE_IDX 0 1036#define regDAGB3_PERFCOUNTER0_CFG 0x01fb 1037#define regDAGB3_PERFCOUNTER0_CFG_BASE_IDX 0 1038#define regDAGB3_PERFCOUNTER1_CFG 0x01fc 1039#define regDAGB3_PERFCOUNTER1_CFG_BASE_IDX 0 1040#define regDAGB3_PERFCOUNTER2_CFG 0x01fd 1041#define regDAGB3_PERFCOUNTER2_CFG_BASE_IDX 0 1042#define regDAGB3_PERFCOUNTER_RSLT_CNTL 0x01fe 1043#define regDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1044#define regDAGB3_L1TLB_REG_RW 0x01ff 1045#define regDAGB3_L1TLB_REG_RW_BASE_IDX 0 1046 1047 1048// addressBlock: aid_mmhub_dagb_dagbdec4 1049// base address: 0x60800 1050#define regDAGB4_RDCLI0 0x0200 1051#define regDAGB4_RDCLI0_BASE_IDX 0 1052#define regDAGB4_RDCLI1 0x0201 1053#define regDAGB4_RDCLI1_BASE_IDX 0 1054#define regDAGB4_RDCLI2 0x0202 1055#define regDAGB4_RDCLI2_BASE_IDX 0 1056#define regDAGB4_RDCLI3 0x0203 1057#define regDAGB4_RDCLI3_BASE_IDX 0 1058#define regDAGB4_RDCLI4 0x0204 1059#define regDAGB4_RDCLI4_BASE_IDX 0 1060#define regDAGB4_RDCLI5 0x0205 1061#define regDAGB4_RDCLI5_BASE_IDX 0 1062#define regDAGB4_RDCLI6 0x0206 1063#define regDAGB4_RDCLI6_BASE_IDX 0 1064#define regDAGB4_RDCLI7 0x0207 1065#define regDAGB4_RDCLI7_BASE_IDX 0 1066#define regDAGB4_RDCLI8 0x0208 1067#define regDAGB4_RDCLI8_BASE_IDX 0 1068#define regDAGB4_RDCLI9 0x0209 1069#define regDAGB4_RDCLI9_BASE_IDX 0 1070#define regDAGB4_RDCLI10 0x020a 1071#define regDAGB4_RDCLI10_BASE_IDX 0 1072#define regDAGB4_RDCLI11 0x020b 1073#define regDAGB4_RDCLI11_BASE_IDX 0 1074#define regDAGB4_RDCLI12 0x020c 1075#define regDAGB4_RDCLI12_BASE_IDX 0 1076#define regDAGB4_RDCLI13 0x020d 1077#define regDAGB4_RDCLI13_BASE_IDX 0 1078#define regDAGB4_RDCLI14 0x020e 1079#define regDAGB4_RDCLI14_BASE_IDX 0 1080#define regDAGB4_RDCLI15 0x020f 1081#define regDAGB4_RDCLI15_BASE_IDX 0 1082#define regDAGB4_RD_CNTL 0x0210 1083#define regDAGB4_RD_CNTL_BASE_IDX 0 1084#define regDAGB4_RD_GMI_CNTL 0x0211 1085#define regDAGB4_RD_GMI_CNTL_BASE_IDX 0 1086#define regDAGB4_RD_ADDR_DAGB 0x0212 1087#define regDAGB4_RD_ADDR_DAGB_BASE_IDX 0 1088#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213 1089#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 1090#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214 1091#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 1092#define regDAGB4_RD_CGTT_CLK_CTRL 0x0215 1093#define regDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 0 1094#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216 1095#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 1096#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217 1097#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 1098#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218 1099#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 1100#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219 1101#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 1102#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a 1103#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 1104#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b 1105#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 1106#define regDAGB4_RD_VC0_CNTL 0x021c 1107#define regDAGB4_RD_VC0_CNTL_BASE_IDX 0 1108#define regDAGB4_RD_VC1_CNTL 0x021d 1109#define regDAGB4_RD_VC1_CNTL_BASE_IDX 0 1110#define regDAGB4_RD_VC2_CNTL 0x021e 1111#define regDAGB4_RD_VC2_CNTL_BASE_IDX 0 1112#define regDAGB4_RD_VC3_CNTL 0x021f 1113#define regDAGB4_RD_VC3_CNTL_BASE_IDX 0 1114#define regDAGB4_RD_VC4_CNTL 0x0220 1115#define regDAGB4_RD_VC4_CNTL_BASE_IDX 0 1116#define regDAGB4_RD_VC5_CNTL 0x0221 1117#define regDAGB4_RD_VC5_CNTL_BASE_IDX 0 1118#define regDAGB4_RD_VC6_CNTL 0x0222 1119#define regDAGB4_RD_VC6_CNTL_BASE_IDX 0 1120#define regDAGB4_RD_VC7_CNTL 0x0223 1121#define regDAGB4_RD_VC7_CNTL_BASE_IDX 0 1122#define regDAGB4_RD_CNTL_MISC 0x0224 1123#define regDAGB4_RD_CNTL_MISC_BASE_IDX 0 1124#define regDAGB4_RD_TLB_CREDIT 0x0225 1125#define regDAGB4_RD_TLB_CREDIT_BASE_IDX 0 1126#define regDAGB4_RD_RDRET_CREDIT_CNTL 0x0226 1127#define regDAGB4_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 1128#define regDAGB4_RD_RDRET_CREDIT_CNTL2 0x0227 1129#define regDAGB4_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 1130#define regDAGB4_RDCLI_ASK_PENDING 0x0228 1131#define regDAGB4_RDCLI_ASK_PENDING_BASE_IDX 0 1132#define regDAGB4_RDCLI_GO_PENDING 0x0229 1133#define regDAGB4_RDCLI_GO_PENDING_BASE_IDX 0 1134#define regDAGB4_RDCLI_GBLSEND_PENDING 0x022a 1135#define regDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 0 1136#define regDAGB4_RDCLI_TLB_PENDING 0x022b 1137#define regDAGB4_RDCLI_TLB_PENDING_BASE_IDX 0 1138#define regDAGB4_RDCLI_OARB_PENDING 0x022c 1139#define regDAGB4_RDCLI_OARB_PENDING_BASE_IDX 0 1140#define regDAGB4_RDCLI_OSD_PENDING 0x022d 1141#define regDAGB4_RDCLI_OSD_PENDING_BASE_IDX 0 1142#define regDAGB4_WRCLI0 0x0230 1143#define regDAGB4_WRCLI0_BASE_IDX 0 1144#define regDAGB4_WRCLI1 0x0231 1145#define regDAGB4_WRCLI1_BASE_IDX 0 1146#define regDAGB4_WRCLI2 0x0232 1147#define regDAGB4_WRCLI2_BASE_IDX 0 1148#define regDAGB4_WRCLI3 0x0233 1149#define regDAGB4_WRCLI3_BASE_IDX 0 1150#define regDAGB4_WRCLI4 0x0234 1151#define regDAGB4_WRCLI4_BASE_IDX 0 1152#define regDAGB4_WRCLI5 0x0235 1153#define regDAGB4_WRCLI5_BASE_IDX 0 1154#define regDAGB4_WRCLI6 0x0236 1155#define regDAGB4_WRCLI6_BASE_IDX 0 1156#define regDAGB4_WRCLI7 0x0237 1157#define regDAGB4_WRCLI7_BASE_IDX 0 1158#define regDAGB4_WRCLI8 0x0238 1159#define regDAGB4_WRCLI8_BASE_IDX 0 1160#define regDAGB4_WRCLI9 0x0239 1161#define regDAGB4_WRCLI9_BASE_IDX 0 1162#define regDAGB4_WRCLI10 0x023a 1163#define regDAGB4_WRCLI10_BASE_IDX 0 1164#define regDAGB4_WRCLI11 0x023b 1165#define regDAGB4_WRCLI11_BASE_IDX 0 1166#define regDAGB4_WRCLI12 0x023c 1167#define regDAGB4_WRCLI12_BASE_IDX 0 1168#define regDAGB4_WRCLI13 0x023d 1169#define regDAGB4_WRCLI13_BASE_IDX 0 1170#define regDAGB4_WRCLI14 0x023e 1171#define regDAGB4_WRCLI14_BASE_IDX 0 1172#define regDAGB4_WRCLI15 0x023f 1173#define regDAGB4_WRCLI15_BASE_IDX 0 1174#define regDAGB4_WR_CNTL 0x0240 1175#define regDAGB4_WR_CNTL_BASE_IDX 0 1176#define regDAGB4_WR_GMI_CNTL 0x0241 1177#define regDAGB4_WR_GMI_CNTL_BASE_IDX 0 1178#define regDAGB4_WR_ADDR_DAGB 0x0242 1179#define regDAGB4_WR_ADDR_DAGB_BASE_IDX 0 1180#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x0243 1181#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 1182#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0244 1183#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 1184#define regDAGB4_WR_CGTT_CLK_CTRL 0x0245 1185#define regDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 0 1186#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0246 1187#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 1188#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0247 1189#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 1190#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0248 1191#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 1192#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0249 1193#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 1194#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x024a 1195#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 1196#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x024b 1197#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 1198#define regDAGB4_WR_DATA_DAGB 0x024c 1199#define regDAGB4_WR_DATA_DAGB_BASE_IDX 0 1200#define regDAGB4_WR_DATA_DAGB_MAX_BURST0 0x024d 1201#define regDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 1202#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024e 1203#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 1204#define regDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024f 1205#define regDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 1206#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x0250 1207#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 1208#define regDAGB4_WR_VC0_CNTL 0x0251 1209#define regDAGB4_WR_VC0_CNTL_BASE_IDX 0 1210#define regDAGB4_WR_VC1_CNTL 0x0252 1211#define regDAGB4_WR_VC1_CNTL_BASE_IDX 0 1212#define regDAGB4_WR_VC2_CNTL 0x0253 1213#define regDAGB4_WR_VC2_CNTL_BASE_IDX 0 1214#define regDAGB4_WR_VC3_CNTL 0x0254 1215#define regDAGB4_WR_VC3_CNTL_BASE_IDX 0 1216#define regDAGB4_WR_VC4_CNTL 0x0255 1217#define regDAGB4_WR_VC4_CNTL_BASE_IDX 0 1218#define regDAGB4_WR_VC5_CNTL 0x0256 1219#define regDAGB4_WR_VC5_CNTL_BASE_IDX 0 1220#define regDAGB4_WR_VC6_CNTL 0x0257 1221#define regDAGB4_WR_VC6_CNTL_BASE_IDX 0 1222#define regDAGB4_WR_VC7_CNTL 0x0258 1223#define regDAGB4_WR_VC7_CNTL_BASE_IDX 0 1224#define regDAGB4_WR_CNTL_MISC 0x0259 1225#define regDAGB4_WR_CNTL_MISC_BASE_IDX 0 1226#define regDAGB4_WR_TLB_CREDIT 0x025a 1227#define regDAGB4_WR_TLB_CREDIT_BASE_IDX 0 1228#define regDAGB4_WR_DATA_CREDIT 0x025b 1229#define regDAGB4_WR_DATA_CREDIT_BASE_IDX 0 1230#define regDAGB4_WR_MISC_CREDIT 0x025c 1231#define regDAGB4_WR_MISC_CREDIT_BASE_IDX 0 1232#define regDAGB4_WR_OSD_CREDIT_CNTL1 0x025d 1233#define regDAGB4_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 1234#define regDAGB4_WR_OSD_CREDIT_CNTL2 0x025e 1235#define regDAGB4_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 1236#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x025f 1237#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 1238#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE 0x0260 1239#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 1240#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x0261 1241#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 1242#define regDAGB4_WRCLI_ASK_PENDING 0x0262 1243#define regDAGB4_WRCLI_ASK_PENDING_BASE_IDX 0 1244#define regDAGB4_WRCLI_GO_PENDING 0x0263 1245#define regDAGB4_WRCLI_GO_PENDING_BASE_IDX 0 1246#define regDAGB4_WRCLI_GBLSEND_PENDING 0x0264 1247#define regDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 0 1248#define regDAGB4_WRCLI_TLB_PENDING 0x0265 1249#define regDAGB4_WRCLI_TLB_PENDING_BASE_IDX 0 1250#define regDAGB4_WRCLI_OARB_PENDING 0x0266 1251#define regDAGB4_WRCLI_OARB_PENDING_BASE_IDX 0 1252#define regDAGB4_WRCLI_OSD_PENDING 0x0267 1253#define regDAGB4_WRCLI_OSD_PENDING_BASE_IDX 0 1254#define regDAGB4_WRCLI_DBUS_ASK_PENDING 0x0268 1255#define regDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 1256#define regDAGB4_WRCLI_DBUS_GO_PENDING 0x0269 1257#define regDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 1258#define regDAGB4_DAGB_DLY 0x026c 1259#define regDAGB4_DAGB_DLY_BASE_IDX 0 1260#define regDAGB4_CNTL_MISC 0x026d 1261#define regDAGB4_CNTL_MISC_BASE_IDX 0 1262#define regDAGB4_CNTL_MISC2 0x026e 1263#define regDAGB4_CNTL_MISC2_BASE_IDX 0 1264#define regDAGB4_FATAL_ERROR_CNTL 0x026f 1265#define regDAGB4_FATAL_ERROR_CNTL_BASE_IDX 0 1266#define regDAGB4_FATAL_ERROR_CLEAR 0x0270 1267#define regDAGB4_FATAL_ERROR_CLEAR_BASE_IDX 0 1268#define regDAGB4_FATAL_ERROR_STATUS0 0x0271 1269#define regDAGB4_FATAL_ERROR_STATUS0_BASE_IDX 0 1270#define regDAGB4_FATAL_ERROR_STATUS1 0x0272 1271#define regDAGB4_FATAL_ERROR_STATUS1_BASE_IDX 0 1272#define regDAGB4_FATAL_ERROR_STATUS2 0x0273 1273#define regDAGB4_FATAL_ERROR_STATUS2_BASE_IDX 0 1274#define regDAGB4_FATAL_ERROR_STATUS3 0x0274 1275#define regDAGB4_FATAL_ERROR_STATUS3_BASE_IDX 0 1276#define regDAGB4_FIFO_EMPTY 0x0275 1277#define regDAGB4_FIFO_EMPTY_BASE_IDX 0 1278#define regDAGB4_FIFO_FULL 0x0276 1279#define regDAGB4_FIFO_FULL_BASE_IDX 0 1280#define regDAGB4_WR_CREDITS_FULL 0x0277 1281#define regDAGB4_WR_CREDITS_FULL_BASE_IDX 0 1282#define regDAGB4_RD_CREDITS_FULL 0x0278 1283#define regDAGB4_RD_CREDITS_FULL_BASE_IDX 0 1284#define regDAGB4_PERFCOUNTER_LO 0x0279 1285#define regDAGB4_PERFCOUNTER_LO_BASE_IDX 0 1286#define regDAGB4_PERFCOUNTER_HI 0x027a 1287#define regDAGB4_PERFCOUNTER_HI_BASE_IDX 0 1288#define regDAGB4_PERFCOUNTER0_CFG 0x027b 1289#define regDAGB4_PERFCOUNTER0_CFG_BASE_IDX 0 1290#define regDAGB4_PERFCOUNTER1_CFG 0x027c 1291#define regDAGB4_PERFCOUNTER1_CFG_BASE_IDX 0 1292#define regDAGB4_PERFCOUNTER2_CFG 0x027d 1293#define regDAGB4_PERFCOUNTER2_CFG_BASE_IDX 0 1294#define regDAGB4_PERFCOUNTER_RSLT_CNTL 0x027e 1295#define regDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1296#define regDAGB4_L1TLB_REG_RW 0x027f 1297#define regDAGB4_L1TLB_REG_RW_BASE_IDX 0 1298 1299 1300// addressBlock: aid_mmhub_ea_mmeadec0 1301// base address: 0x60c00 1302#define regMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0300 1303#define regMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 1304#define regMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0301 1305#define regMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 1306#define regMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0302 1307#define regMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 1308#define regMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0303 1309#define regMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 1310#define regMMEA0_DRAM_RD_GRP2VC_MAP 0x0304 1311#define regMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 1312#define regMMEA0_DRAM_WR_GRP2VC_MAP 0x0305 1313#define regMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 1314#define regMMEA0_DRAM_RD_LAZY 0x0306 1315#define regMMEA0_DRAM_RD_LAZY_BASE_IDX 0 1316#define regMMEA0_DRAM_WR_LAZY 0x0307 1317#define regMMEA0_DRAM_WR_LAZY_BASE_IDX 0 1318#define regMMEA0_DRAM_RD_CAM_CNTL 0x0308 1319#define regMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 1320#define regMMEA0_DRAM_WR_CAM_CNTL 0x0309 1321#define regMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 1322#define regMMEA0_DRAM_PAGE_BURST 0x030a 1323#define regMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 1324#define regMMEA0_DRAM_RD_PRI_AGE 0x030b 1325#define regMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 1326#define regMMEA0_DRAM_WR_PRI_AGE 0x030c 1327#define regMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 1328#define regMMEA0_DRAM_RD_PRI_QUEUING 0x030d 1329#define regMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 1330#define regMMEA0_DRAM_WR_PRI_QUEUING 0x030e 1331#define regMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 1332#define regMMEA0_DRAM_RD_PRI_FIXED 0x030f 1333#define regMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 1334#define regMMEA0_DRAM_WR_PRI_FIXED 0x0310 1335#define regMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 1336#define regMMEA0_DRAM_RD_PRI_URGENCY 0x0311 1337#define regMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 1338#define regMMEA0_DRAM_WR_PRI_URGENCY 0x0312 1339#define regMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 1340#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0313 1341#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 1342#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0314 1343#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 1344#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0315 1345#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 1346#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0316 1347#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 1348#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0317 1349#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 1350#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0318 1351#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 1352#define regMMEA0_GMI_RD_CLI2GRP_MAP0 0x0319 1353#define regMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 1354#define regMMEA0_GMI_RD_CLI2GRP_MAP1 0x031a 1355#define regMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 1356#define regMMEA0_GMI_WR_CLI2GRP_MAP0 0x031b 1357#define regMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 1358#define regMMEA0_GMI_WR_CLI2GRP_MAP1 0x031c 1359#define regMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 1360#define regMMEA0_GMI_RD_GRP2VC_MAP 0x031d 1361#define regMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 0 1362#define regMMEA0_GMI_WR_GRP2VC_MAP 0x031e 1363#define regMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 0 1364#define regMMEA0_GMI_RD_LAZY 0x031f 1365#define regMMEA0_GMI_RD_LAZY_BASE_IDX 0 1366#define regMMEA0_GMI_WR_LAZY 0x0320 1367#define regMMEA0_GMI_WR_LAZY_BASE_IDX 0 1368#define regMMEA0_GMI_RD_CAM_CNTL 0x0321 1369#define regMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 0 1370#define regMMEA0_GMI_WR_CAM_CNTL 0x0322 1371#define regMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 0 1372#define regMMEA0_GMI_PAGE_BURST 0x0323 1373#define regMMEA0_GMI_PAGE_BURST_BASE_IDX 0 1374#define regMMEA0_GMI_RD_PRI_AGE 0x0324 1375#define regMMEA0_GMI_RD_PRI_AGE_BASE_IDX 0 1376#define regMMEA0_GMI_WR_PRI_AGE 0x0325 1377#define regMMEA0_GMI_WR_PRI_AGE_BASE_IDX 0 1378#define regMMEA0_GMI_RD_PRI_QUEUING 0x0326 1379#define regMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 0 1380#define regMMEA0_GMI_WR_PRI_QUEUING 0x0327 1381#define regMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 0 1382#define regMMEA0_GMI_RD_PRI_FIXED 0x0328 1383#define regMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 0 1384#define regMMEA0_GMI_WR_PRI_FIXED 0x0329 1385#define regMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 0 1386#define regMMEA0_GMI_RD_PRI_URGENCY 0x032a 1387#define regMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 0 1388#define regMMEA0_GMI_WR_PRI_URGENCY 0x032b 1389#define regMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 0 1390#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x032c 1391#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 1392#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x032d 1393#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 1394#define regMMEA0_GMI_RD_PRI_QUANT_PRI1 0x032e 1395#define regMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 1396#define regMMEA0_GMI_RD_PRI_QUANT_PRI2 0x032f 1397#define regMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 1398#define regMMEA0_GMI_RD_PRI_QUANT_PRI3 0x0330 1399#define regMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 1400#define regMMEA0_GMI_WR_PRI_QUANT_PRI1 0x0331 1401#define regMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 1402#define regMMEA0_GMI_WR_PRI_QUANT_PRI2 0x0332 1403#define regMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 1404#define regMMEA0_GMI_WR_PRI_QUANT_PRI3 0x0333 1405#define regMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 1406#define regMMEA0_IO_RD_CLI2GRP_MAP0 0x03d5 1407#define regMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 1408#define regMMEA0_IO_RD_CLI2GRP_MAP1 0x03d6 1409#define regMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 1410#define regMMEA0_IO_WR_CLI2GRP_MAP0 0x03d7 1411#define regMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 1412#define regMMEA0_IO_WR_CLI2GRP_MAP1 0x03d8 1413#define regMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 1414#define regMMEA0_IO_RD_COMBINE_FLUSH 0x03d9 1415#define regMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 1416#define regMMEA0_IO_WR_COMBINE_FLUSH 0x03da 1417#define regMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 1418#define regMMEA0_IO_GROUP_BURST 0x03db 1419#define regMMEA0_IO_GROUP_BURST_BASE_IDX 0 1420#define regMMEA0_IO_RD_PRI_AGE 0x03dc 1421#define regMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 1422#define regMMEA0_IO_WR_PRI_AGE 0x03dd 1423#define regMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 1424#define regMMEA0_IO_RD_PRI_QUEUING 0x03de 1425#define regMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 1426#define regMMEA0_IO_WR_PRI_QUEUING 0x03df 1427#define regMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 1428#define regMMEA0_IO_RD_PRI_FIXED 0x03e0 1429#define regMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 1430#define regMMEA0_IO_WR_PRI_FIXED 0x03e1 1431#define regMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 1432#define regMMEA0_IO_RD_PRI_URGENCY 0x03e2 1433#define regMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 1434#define regMMEA0_IO_WR_PRI_URGENCY 0x03e3 1435#define regMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 1436#define regMMEA0_IO_RD_PRI_URGENCY_MASKING 0x03e4 1437#define regMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 1438#define regMMEA0_IO_WR_PRI_URGENCY_MASKING 0x03e5 1439#define regMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 1440#define regMMEA0_IO_RD_PRI_QUANT_PRI1 0x03e6 1441#define regMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 1442#define regMMEA0_IO_RD_PRI_QUANT_PRI2 0x03e7 1443#define regMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 1444#define regMMEA0_IO_RD_PRI_QUANT_PRI3 0x03e8 1445#define regMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 1446#define regMMEA0_IO_WR_PRI_QUANT_PRI1 0x03e9 1447#define regMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 1448#define regMMEA0_IO_WR_PRI_QUANT_PRI2 0x03ea 1449#define regMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 1450#define regMMEA0_IO_WR_PRI_QUANT_PRI3 0x03eb 1451#define regMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 1452#define regMMEA0_SDP_ARB_DRAM 0x03ec 1453#define regMMEA0_SDP_ARB_DRAM_BASE_IDX 0 1454#define regMMEA0_SDP_ARB_GMI 0x03ed 1455#define regMMEA0_SDP_ARB_GMI_BASE_IDX 0 1456#define regMMEA0_SDP_ARB_FINAL 0x03ee 1457#define regMMEA0_SDP_ARB_FINAL_BASE_IDX 0 1458#define regMMEA0_SDP_DRAM_PRIORITY 0x03ef 1459#define regMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 1460#define regMMEA0_SDP_GMI_PRIORITY 0x03f0 1461#define regMMEA0_SDP_GMI_PRIORITY_BASE_IDX 0 1462#define regMMEA0_SDP_IO_PRIORITY 0x03f1 1463#define regMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 1464#define regMMEA0_SDP_CREDITS 0x03f2 1465#define regMMEA0_SDP_CREDITS_BASE_IDX 0 1466#define regMMEA0_SDP_TAG_RESERVE0 0x03f3 1467#define regMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 1468#define regMMEA0_SDP_TAG_RESERVE1 0x03f4 1469#define regMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 1470#define regMMEA0_SDP_VCC_RESERVE0 0x03f5 1471#define regMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 1472#define regMMEA0_SDP_VCC_RESERVE1 0x03f6 1473#define regMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 1474#define regMMEA0_SDP_VCD_RESERVE0 0x03f7 1475#define regMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 1476#define regMMEA0_SDP_VCD_RESERVE1 0x03f8 1477#define regMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 1478#define regMMEA0_SDP_REQ_CNTL 0x03f9 1479#define regMMEA0_SDP_REQ_CNTL_BASE_IDX 0 1480#define regMMEA0_MISC 0x03fa 1481#define regMMEA0_MISC_BASE_IDX 0 1482#define regMMEA0_LATENCY_SAMPLING 0x03fb 1483#define regMMEA0_LATENCY_SAMPLING_BASE_IDX 0 1484#define regMMEA0_PERFCOUNTER_LO 0x03fc 1485#define regMMEA0_PERFCOUNTER_LO_BASE_IDX 0 1486#define regMMEA0_PERFCOUNTER_HI 0x03fd 1487#define regMMEA0_PERFCOUNTER_HI_BASE_IDX 0 1488#define regMMEA0_PERFCOUNTER0_CFG 0x03fe 1489#define regMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 1490#define regMMEA0_PERFCOUNTER1_CFG 0x03ff 1491#define regMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 1492#define regMMEA0_PERFCOUNTER_RSLT_CNTL 0x0400 1493#define regMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1494#define regMMEA0_UE_ERR_STATUS_LO 0x0406 1495#define regMMEA0_UE_ERR_STATUS_LO_BASE_IDX 0 1496#define regMMEA0_UE_ERR_STATUS_HI 0x0407 1497#define regMMEA0_UE_ERR_STATUS_HI_BASE_IDX 0 1498#define regMMEA0_DSM_CNTL 0x0408 1499#define regMMEA0_DSM_CNTL_BASE_IDX 0 1500#define regMMEA0_DSM_CNTLA 0x0409 1501#define regMMEA0_DSM_CNTLA_BASE_IDX 0 1502#define regMMEA0_DSM_CNTLB 0x040a 1503#define regMMEA0_DSM_CNTLB_BASE_IDX 0 1504#define regMMEA0_DSM_CNTL2 0x040b 1505#define regMMEA0_DSM_CNTL2_BASE_IDX 0 1506#define regMMEA0_DSM_CNTL2A 0x040c 1507#define regMMEA0_DSM_CNTL2A_BASE_IDX 0 1508#define regMMEA0_DSM_CNTL2B 0x040d 1509#define regMMEA0_DSM_CNTL2B_BASE_IDX 0 1510#define regMMEA0_CGTT_CLK_CTRL 0x040f 1511#define regMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 1512#define regMMEA0_EDC_MODE 0x0410 1513#define regMMEA0_EDC_MODE_BASE_IDX 0 1514#define regMMEA0_ERR_STATUS 0x0411 1515#define regMMEA0_ERR_STATUS_BASE_IDX 0 1516#define regMMEA0_MISC2 0x0412 1517#define regMMEA0_MISC2_BASE_IDX 0 1518#define regMMEA0_CE_ERR_STATUS_LO 0x0414 1519#define regMMEA0_CE_ERR_STATUS_LO_BASE_IDX 0 1520#define regMMEA0_MISC_AON 0x0415 1521#define regMMEA0_MISC_AON_BASE_IDX 0 1522#define regMMEA0_CE_ERR_STATUS_HI 0x0416 1523#define regMMEA0_CE_ERR_STATUS_HI_BASE_IDX 0 1524 1525 1526// addressBlock: aid_mmhub_ea_mmeadec1 1527// base address: 0x61100 1528#define regMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0440 1529#define regMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 1530#define regMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0441 1531#define regMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 1532#define regMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0442 1533#define regMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 1534#define regMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0443 1535#define regMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 1536#define regMMEA1_DRAM_RD_GRP2VC_MAP 0x0444 1537#define regMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 1538#define regMMEA1_DRAM_WR_GRP2VC_MAP 0x0445 1539#define regMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 1540#define regMMEA1_DRAM_RD_LAZY 0x0446 1541#define regMMEA1_DRAM_RD_LAZY_BASE_IDX 0 1542#define regMMEA1_DRAM_WR_LAZY 0x0447 1543#define regMMEA1_DRAM_WR_LAZY_BASE_IDX 0 1544#define regMMEA1_DRAM_RD_CAM_CNTL 0x0448 1545#define regMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0 1546#define regMMEA1_DRAM_WR_CAM_CNTL 0x0449 1547#define regMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0 1548#define regMMEA1_DRAM_PAGE_BURST 0x044a 1549#define regMMEA1_DRAM_PAGE_BURST_BASE_IDX 0 1550#define regMMEA1_DRAM_RD_PRI_AGE 0x044b 1551#define regMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0 1552#define regMMEA1_DRAM_WR_PRI_AGE 0x044c 1553#define regMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0 1554#define regMMEA1_DRAM_RD_PRI_QUEUING 0x044d 1555#define regMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0 1556#define regMMEA1_DRAM_WR_PRI_QUEUING 0x044e 1557#define regMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0 1558#define regMMEA1_DRAM_RD_PRI_FIXED 0x044f 1559#define regMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0 1560#define regMMEA1_DRAM_WR_PRI_FIXED 0x0450 1561#define regMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0 1562#define regMMEA1_DRAM_RD_PRI_URGENCY 0x0451 1563#define regMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0 1564#define regMMEA1_DRAM_WR_PRI_URGENCY 0x0452 1565#define regMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0 1566#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0453 1567#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 1568#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0454 1569#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 1570#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0455 1571#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 1572#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0456 1573#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 1574#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0457 1575#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 1576#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0458 1577#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 1578#define regMMEA1_GMI_RD_CLI2GRP_MAP0 0x0459 1579#define regMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 1580#define regMMEA1_GMI_RD_CLI2GRP_MAP1 0x045a 1581#define regMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 1582#define regMMEA1_GMI_WR_CLI2GRP_MAP0 0x045b 1583#define regMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 1584#define regMMEA1_GMI_WR_CLI2GRP_MAP1 0x045c 1585#define regMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 1586#define regMMEA1_GMI_RD_GRP2VC_MAP 0x045d 1587#define regMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 0 1588#define regMMEA1_GMI_WR_GRP2VC_MAP 0x045e 1589#define regMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 0 1590#define regMMEA1_GMI_RD_LAZY 0x045f 1591#define regMMEA1_GMI_RD_LAZY_BASE_IDX 0 1592#define regMMEA1_GMI_WR_LAZY 0x0460 1593#define regMMEA1_GMI_WR_LAZY_BASE_IDX 0 1594#define regMMEA1_GMI_RD_CAM_CNTL 0x0461 1595#define regMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 0 1596#define regMMEA1_GMI_WR_CAM_CNTL 0x0462 1597#define regMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 0 1598#define regMMEA1_GMI_PAGE_BURST 0x0463 1599#define regMMEA1_GMI_PAGE_BURST_BASE_IDX 0 1600#define regMMEA1_GMI_RD_PRI_AGE 0x0464 1601#define regMMEA1_GMI_RD_PRI_AGE_BASE_IDX 0 1602#define regMMEA1_GMI_WR_PRI_AGE 0x0465 1603#define regMMEA1_GMI_WR_PRI_AGE_BASE_IDX 0 1604#define regMMEA1_GMI_RD_PRI_QUEUING 0x0466 1605#define regMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 0 1606#define regMMEA1_GMI_WR_PRI_QUEUING 0x0467 1607#define regMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 0 1608#define regMMEA1_GMI_RD_PRI_FIXED 0x0468 1609#define regMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 0 1610#define regMMEA1_GMI_WR_PRI_FIXED 0x0469 1611#define regMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 0 1612#define regMMEA1_GMI_RD_PRI_URGENCY 0x046a 1613#define regMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 0 1614#define regMMEA1_GMI_WR_PRI_URGENCY 0x046b 1615#define regMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 0 1616#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x046c 1617#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 1618#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x046d 1619#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 1620#define regMMEA1_GMI_RD_PRI_QUANT_PRI1 0x046e 1621#define regMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 1622#define regMMEA1_GMI_RD_PRI_QUANT_PRI2 0x046f 1623#define regMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 1624#define regMMEA1_GMI_RD_PRI_QUANT_PRI3 0x0470 1625#define regMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 1626#define regMMEA1_GMI_WR_PRI_QUANT_PRI1 0x0471 1627#define regMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 1628#define regMMEA1_GMI_WR_PRI_QUANT_PRI2 0x0472 1629#define regMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 1630#define regMMEA1_GMI_WR_PRI_QUANT_PRI3 0x0473 1631#define regMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 1632#define regMMEA1_IO_RD_CLI2GRP_MAP0 0x0515 1633#define regMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 1634#define regMMEA1_IO_RD_CLI2GRP_MAP1 0x0516 1635#define regMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 1636#define regMMEA1_IO_WR_CLI2GRP_MAP0 0x0517 1637#define regMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 1638#define regMMEA1_IO_WR_CLI2GRP_MAP1 0x0518 1639#define regMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 1640#define regMMEA1_IO_RD_COMBINE_FLUSH 0x0519 1641#define regMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0 1642#define regMMEA1_IO_WR_COMBINE_FLUSH 0x051a 1643#define regMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0 1644#define regMMEA1_IO_GROUP_BURST 0x051b 1645#define regMMEA1_IO_GROUP_BURST_BASE_IDX 0 1646#define regMMEA1_IO_RD_PRI_AGE 0x051c 1647#define regMMEA1_IO_RD_PRI_AGE_BASE_IDX 0 1648#define regMMEA1_IO_WR_PRI_AGE 0x051d 1649#define regMMEA1_IO_WR_PRI_AGE_BASE_IDX 0 1650#define regMMEA1_IO_RD_PRI_QUEUING 0x051e 1651#define regMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0 1652#define regMMEA1_IO_WR_PRI_QUEUING 0x051f 1653#define regMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0 1654#define regMMEA1_IO_RD_PRI_FIXED 0x0520 1655#define regMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0 1656#define regMMEA1_IO_WR_PRI_FIXED 0x0521 1657#define regMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0 1658#define regMMEA1_IO_RD_PRI_URGENCY 0x0522 1659#define regMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0 1660#define regMMEA1_IO_WR_PRI_URGENCY 0x0523 1661#define regMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0 1662#define regMMEA1_IO_RD_PRI_URGENCY_MASKING 0x0524 1663#define regMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 1664#define regMMEA1_IO_WR_PRI_URGENCY_MASKING 0x0525 1665#define regMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 1666#define regMMEA1_IO_RD_PRI_QUANT_PRI1 0x0526 1667#define regMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 1668#define regMMEA1_IO_RD_PRI_QUANT_PRI2 0x0527 1669#define regMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 1670#define regMMEA1_IO_RD_PRI_QUANT_PRI3 0x0528 1671#define regMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 1672#define regMMEA1_IO_WR_PRI_QUANT_PRI1 0x0529 1673#define regMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 1674#define regMMEA1_IO_WR_PRI_QUANT_PRI2 0x052a 1675#define regMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 1676#define regMMEA1_IO_WR_PRI_QUANT_PRI3 0x052b 1677#define regMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 1678#define regMMEA1_SDP_ARB_DRAM 0x052c 1679#define regMMEA1_SDP_ARB_DRAM_BASE_IDX 0 1680#define regMMEA1_SDP_ARB_GMI 0x052d 1681#define regMMEA1_SDP_ARB_GMI_BASE_IDX 0 1682#define regMMEA1_SDP_ARB_FINAL 0x052e 1683#define regMMEA1_SDP_ARB_FINAL_BASE_IDX 0 1684#define regMMEA1_SDP_DRAM_PRIORITY 0x052f 1685#define regMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0 1686#define regMMEA1_SDP_GMI_PRIORITY 0x0530 1687#define regMMEA1_SDP_GMI_PRIORITY_BASE_IDX 0 1688#define regMMEA1_SDP_IO_PRIORITY 0x0531 1689#define regMMEA1_SDP_IO_PRIORITY_BASE_IDX 0 1690#define regMMEA1_SDP_CREDITS 0x0532 1691#define regMMEA1_SDP_CREDITS_BASE_IDX 0 1692#define regMMEA1_SDP_TAG_RESERVE0 0x0533 1693#define regMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0 1694#define regMMEA1_SDP_TAG_RESERVE1 0x0534 1695#define regMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0 1696#define regMMEA1_SDP_VCC_RESERVE0 0x0535 1697#define regMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0 1698#define regMMEA1_SDP_VCC_RESERVE1 0x0536 1699#define regMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0 1700#define regMMEA1_SDP_VCD_RESERVE0 0x0537 1701#define regMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0 1702#define regMMEA1_SDP_VCD_RESERVE1 0x0538 1703#define regMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0 1704#define regMMEA1_SDP_REQ_CNTL 0x0539 1705#define regMMEA1_SDP_REQ_CNTL_BASE_IDX 0 1706#define regMMEA1_MISC 0x053a 1707#define regMMEA1_MISC_BASE_IDX 0 1708#define regMMEA1_LATENCY_SAMPLING 0x053b 1709#define regMMEA1_LATENCY_SAMPLING_BASE_IDX 0 1710#define regMMEA1_PERFCOUNTER_LO 0x053c 1711#define regMMEA1_PERFCOUNTER_LO_BASE_IDX 0 1712#define regMMEA1_PERFCOUNTER_HI 0x053d 1713#define regMMEA1_PERFCOUNTER_HI_BASE_IDX 0 1714#define regMMEA1_PERFCOUNTER0_CFG 0x053e 1715#define regMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0 1716#define regMMEA1_PERFCOUNTER1_CFG 0x053f 1717#define regMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0 1718#define regMMEA1_PERFCOUNTER_RSLT_CNTL 0x0540 1719#define regMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1720#define regMMEA1_UE_ERR_STATUS_LO 0x0546 1721#define regMMEA1_UE_ERR_STATUS_LO_BASE_IDX 0 1722#define regMMEA1_UE_ERR_STATUS_HI 0x0547 1723#define regMMEA1_UE_ERR_STATUS_HI_BASE_IDX 0 1724#define regMMEA1_DSM_CNTL 0x0548 1725#define regMMEA1_DSM_CNTL_BASE_IDX 0 1726#define regMMEA1_DSM_CNTLA 0x0549 1727#define regMMEA1_DSM_CNTLA_BASE_IDX 0 1728#define regMMEA1_DSM_CNTLB 0x054a 1729#define regMMEA1_DSM_CNTLB_BASE_IDX 0 1730#define regMMEA1_DSM_CNTL2 0x054b 1731#define regMMEA1_DSM_CNTL2_BASE_IDX 0 1732#define regMMEA1_DSM_CNTL2A 0x054c 1733#define regMMEA1_DSM_CNTL2A_BASE_IDX 0 1734#define regMMEA1_DSM_CNTL2B 0x054d 1735#define regMMEA1_DSM_CNTL2B_BASE_IDX 0 1736#define regMMEA1_CGTT_CLK_CTRL 0x054f 1737#define regMMEA1_CGTT_CLK_CTRL_BASE_IDX 0 1738#define regMMEA1_EDC_MODE 0x0550 1739#define regMMEA1_EDC_MODE_BASE_IDX 0 1740#define regMMEA1_ERR_STATUS 0x0551 1741#define regMMEA1_ERR_STATUS_BASE_IDX 0 1742#define regMMEA1_MISC2 0x0552 1743#define regMMEA1_MISC2_BASE_IDX 0 1744#define regMMEA1_CE_ERR_STATUS_LO 0x0554 1745#define regMMEA1_CE_ERR_STATUS_LO_BASE_IDX 0 1746#define regMMEA1_MISC_AON 0x0555 1747#define regMMEA1_MISC_AON_BASE_IDX 0 1748#define regMMEA1_CE_ERR_STATUS_HI 0x0556 1749#define regMMEA1_CE_ERR_STATUS_HI_BASE_IDX 0 1750 1751 1752// addressBlock: aid_mmhub_ea_mmeadec2 1753// base address: 0x61600 1754#define regMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0580 1755#define regMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 1756#define regMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0581 1757#define regMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 1758#define regMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0582 1759#define regMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 1760#define regMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0583 1761#define regMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 1762#define regMMEA2_DRAM_RD_GRP2VC_MAP 0x0584 1763#define regMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 1764#define regMMEA2_DRAM_WR_GRP2VC_MAP 0x0585 1765#define regMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 1766#define regMMEA2_DRAM_RD_LAZY 0x0586 1767#define regMMEA2_DRAM_RD_LAZY_BASE_IDX 0 1768#define regMMEA2_DRAM_WR_LAZY 0x0587 1769#define regMMEA2_DRAM_WR_LAZY_BASE_IDX 0 1770#define regMMEA2_DRAM_RD_CAM_CNTL 0x0588 1771#define regMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 0 1772#define regMMEA2_DRAM_WR_CAM_CNTL 0x0589 1773#define regMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 0 1774#define regMMEA2_DRAM_PAGE_BURST 0x058a 1775#define regMMEA2_DRAM_PAGE_BURST_BASE_IDX 0 1776#define regMMEA2_DRAM_RD_PRI_AGE 0x058b 1777#define regMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 0 1778#define regMMEA2_DRAM_WR_PRI_AGE 0x058c 1779#define regMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 0 1780#define regMMEA2_DRAM_RD_PRI_QUEUING 0x058d 1781#define regMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 0 1782#define regMMEA2_DRAM_WR_PRI_QUEUING 0x058e 1783#define regMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 0 1784#define regMMEA2_DRAM_RD_PRI_FIXED 0x058f 1785#define regMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 0 1786#define regMMEA2_DRAM_WR_PRI_FIXED 0x0590 1787#define regMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 0 1788#define regMMEA2_DRAM_RD_PRI_URGENCY 0x0591 1789#define regMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 0 1790#define regMMEA2_DRAM_WR_PRI_URGENCY 0x0592 1791#define regMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 0 1792#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0593 1793#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 1794#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0594 1795#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 1796#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0595 1797#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 1798#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0596 1799#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 1800#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0597 1801#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 1802#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0598 1803#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 1804#define regMMEA2_GMI_RD_CLI2GRP_MAP0 0x0599 1805#define regMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 1806#define regMMEA2_GMI_RD_CLI2GRP_MAP1 0x059a 1807#define regMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 1808#define regMMEA2_GMI_WR_CLI2GRP_MAP0 0x059b 1809#define regMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 1810#define regMMEA2_GMI_WR_CLI2GRP_MAP1 0x059c 1811#define regMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 1812#define regMMEA2_GMI_RD_GRP2VC_MAP 0x059d 1813#define regMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 0 1814#define regMMEA2_GMI_WR_GRP2VC_MAP 0x059e 1815#define regMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 0 1816#define regMMEA2_GMI_RD_LAZY 0x059f 1817#define regMMEA2_GMI_RD_LAZY_BASE_IDX 0 1818#define regMMEA2_GMI_WR_LAZY 0x05a0 1819#define regMMEA2_GMI_WR_LAZY_BASE_IDX 0 1820#define regMMEA2_GMI_RD_CAM_CNTL 0x05a1 1821#define regMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 0 1822#define regMMEA2_GMI_WR_CAM_CNTL 0x05a2 1823#define regMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 0 1824#define regMMEA2_GMI_PAGE_BURST 0x05a3 1825#define regMMEA2_GMI_PAGE_BURST_BASE_IDX 0 1826#define regMMEA2_GMI_RD_PRI_AGE 0x05a4 1827#define regMMEA2_GMI_RD_PRI_AGE_BASE_IDX 0 1828#define regMMEA2_GMI_WR_PRI_AGE 0x05a5 1829#define regMMEA2_GMI_WR_PRI_AGE_BASE_IDX 0 1830#define regMMEA2_GMI_RD_PRI_QUEUING 0x05a6 1831#define regMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 0 1832#define regMMEA2_GMI_WR_PRI_QUEUING 0x05a7 1833#define regMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 0 1834#define regMMEA2_GMI_RD_PRI_FIXED 0x05a8 1835#define regMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 0 1836#define regMMEA2_GMI_WR_PRI_FIXED 0x05a9 1837#define regMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 0 1838#define regMMEA2_GMI_RD_PRI_URGENCY 0x05aa 1839#define regMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 0 1840#define regMMEA2_GMI_WR_PRI_URGENCY 0x05ab 1841#define regMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 0 1842#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x05ac 1843#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 1844#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x05ad 1845#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 1846#define regMMEA2_GMI_RD_PRI_QUANT_PRI1 0x05ae 1847#define regMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 1848#define regMMEA2_GMI_RD_PRI_QUANT_PRI2 0x05af 1849#define regMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 1850#define regMMEA2_GMI_RD_PRI_QUANT_PRI3 0x05b0 1851#define regMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 1852#define regMMEA2_GMI_WR_PRI_QUANT_PRI1 0x05b1 1853#define regMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 1854#define regMMEA2_GMI_WR_PRI_QUANT_PRI2 0x05b2 1855#define regMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 1856#define regMMEA2_GMI_WR_PRI_QUANT_PRI3 0x05b3 1857#define regMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 1858#define regMMEA2_IO_RD_CLI2GRP_MAP0 0x0655 1859#define regMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 1860#define regMMEA2_IO_RD_CLI2GRP_MAP1 0x0656 1861#define regMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 1862#define regMMEA2_IO_WR_CLI2GRP_MAP0 0x0657 1863#define regMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 1864#define regMMEA2_IO_WR_CLI2GRP_MAP1 0x0658 1865#define regMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 1866#define regMMEA2_IO_RD_COMBINE_FLUSH 0x0659 1867#define regMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX 0 1868#define regMMEA2_IO_WR_COMBINE_FLUSH 0x065a 1869#define regMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX 0 1870#define regMMEA2_IO_GROUP_BURST 0x065b 1871#define regMMEA2_IO_GROUP_BURST_BASE_IDX 0 1872#define regMMEA2_IO_RD_PRI_AGE 0x065c 1873#define regMMEA2_IO_RD_PRI_AGE_BASE_IDX 0 1874#define regMMEA2_IO_WR_PRI_AGE 0x065d 1875#define regMMEA2_IO_WR_PRI_AGE_BASE_IDX 0 1876#define regMMEA2_IO_RD_PRI_QUEUING 0x065e 1877#define regMMEA2_IO_RD_PRI_QUEUING_BASE_IDX 0 1878#define regMMEA2_IO_WR_PRI_QUEUING 0x065f 1879#define regMMEA2_IO_WR_PRI_QUEUING_BASE_IDX 0 1880#define regMMEA2_IO_RD_PRI_FIXED 0x0660 1881#define regMMEA2_IO_RD_PRI_FIXED_BASE_IDX 0 1882#define regMMEA2_IO_WR_PRI_FIXED 0x0661 1883#define regMMEA2_IO_WR_PRI_FIXED_BASE_IDX 0 1884#define regMMEA2_IO_RD_PRI_URGENCY 0x0662 1885#define regMMEA2_IO_RD_PRI_URGENCY_BASE_IDX 0 1886#define regMMEA2_IO_WR_PRI_URGENCY 0x0663 1887#define regMMEA2_IO_WR_PRI_URGENCY_BASE_IDX 0 1888#define regMMEA2_IO_RD_PRI_URGENCY_MASKING 0x0664 1889#define regMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 1890#define regMMEA2_IO_WR_PRI_URGENCY_MASKING 0x0665 1891#define regMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 1892#define regMMEA2_IO_RD_PRI_QUANT_PRI1 0x0666 1893#define regMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 1894#define regMMEA2_IO_RD_PRI_QUANT_PRI2 0x0667 1895#define regMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 1896#define regMMEA2_IO_RD_PRI_QUANT_PRI3 0x0668 1897#define regMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 1898#define regMMEA2_IO_WR_PRI_QUANT_PRI1 0x0669 1899#define regMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 1900#define regMMEA2_IO_WR_PRI_QUANT_PRI2 0x066a 1901#define regMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 1902#define regMMEA2_IO_WR_PRI_QUANT_PRI3 0x066b 1903#define regMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 1904#define regMMEA2_SDP_ARB_DRAM 0x066c 1905#define regMMEA2_SDP_ARB_DRAM_BASE_IDX 0 1906#define regMMEA2_SDP_ARB_GMI 0x066d 1907#define regMMEA2_SDP_ARB_GMI_BASE_IDX 0 1908#define regMMEA2_SDP_ARB_FINAL 0x066e 1909#define regMMEA2_SDP_ARB_FINAL_BASE_IDX 0 1910#define regMMEA2_SDP_DRAM_PRIORITY 0x066f 1911#define regMMEA2_SDP_DRAM_PRIORITY_BASE_IDX 0 1912#define regMMEA2_SDP_GMI_PRIORITY 0x0670 1913#define regMMEA2_SDP_GMI_PRIORITY_BASE_IDX 0 1914#define regMMEA2_SDP_IO_PRIORITY 0x0671 1915#define regMMEA2_SDP_IO_PRIORITY_BASE_IDX 0 1916#define regMMEA2_SDP_CREDITS 0x0672 1917#define regMMEA2_SDP_CREDITS_BASE_IDX 0 1918#define regMMEA2_SDP_TAG_RESERVE0 0x0673 1919#define regMMEA2_SDP_TAG_RESERVE0_BASE_IDX 0 1920#define regMMEA2_SDP_TAG_RESERVE1 0x0674 1921#define regMMEA2_SDP_TAG_RESERVE1_BASE_IDX 0 1922#define regMMEA2_SDP_VCC_RESERVE0 0x0675 1923#define regMMEA2_SDP_VCC_RESERVE0_BASE_IDX 0 1924#define regMMEA2_SDP_VCC_RESERVE1 0x0676 1925#define regMMEA2_SDP_VCC_RESERVE1_BASE_IDX 0 1926#define regMMEA2_SDP_VCD_RESERVE0 0x0677 1927#define regMMEA2_SDP_VCD_RESERVE0_BASE_IDX 0 1928#define regMMEA2_SDP_VCD_RESERVE1 0x0678 1929#define regMMEA2_SDP_VCD_RESERVE1_BASE_IDX 0 1930#define regMMEA2_SDP_REQ_CNTL 0x0679 1931#define regMMEA2_SDP_REQ_CNTL_BASE_IDX 0 1932#define regMMEA2_MISC 0x067a 1933#define regMMEA2_MISC_BASE_IDX 0 1934#define regMMEA2_LATENCY_SAMPLING 0x067b 1935#define regMMEA2_LATENCY_SAMPLING_BASE_IDX 0 1936#define regMMEA2_PERFCOUNTER_LO 0x067c 1937#define regMMEA2_PERFCOUNTER_LO_BASE_IDX 0 1938#define regMMEA2_PERFCOUNTER_HI 0x067d 1939#define regMMEA2_PERFCOUNTER_HI_BASE_IDX 0 1940#define regMMEA2_PERFCOUNTER0_CFG 0x067e 1941#define regMMEA2_PERFCOUNTER0_CFG_BASE_IDX 0 1942#define regMMEA2_PERFCOUNTER1_CFG 0x067f 1943#define regMMEA2_PERFCOUNTER1_CFG_BASE_IDX 0 1944#define regMMEA2_PERFCOUNTER_RSLT_CNTL 0x0680 1945#define regMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1946#define regMMEA2_UE_ERR_STATUS_LO 0x0686 1947#define regMMEA2_UE_ERR_STATUS_LO_BASE_IDX 0 1948#define regMMEA2_UE_ERR_STATUS_HI 0x0687 1949#define regMMEA2_UE_ERR_STATUS_HI_BASE_IDX 0 1950#define regMMEA2_DSM_CNTL 0x0688 1951#define regMMEA2_DSM_CNTL_BASE_IDX 0 1952#define regMMEA2_DSM_CNTLA 0x0689 1953#define regMMEA2_DSM_CNTLA_BASE_IDX 0 1954#define regMMEA2_DSM_CNTLB 0x068a 1955#define regMMEA2_DSM_CNTLB_BASE_IDX 0 1956#define regMMEA2_DSM_CNTL2 0x068b 1957#define regMMEA2_DSM_CNTL2_BASE_IDX 0 1958#define regMMEA2_DSM_CNTL2A 0x068c 1959#define regMMEA2_DSM_CNTL2A_BASE_IDX 0 1960#define regMMEA2_DSM_CNTL2B 0x068d 1961#define regMMEA2_DSM_CNTL2B_BASE_IDX 0 1962#define regMMEA2_CGTT_CLK_CTRL 0x068f 1963#define regMMEA2_CGTT_CLK_CTRL_BASE_IDX 0 1964#define regMMEA2_EDC_MODE 0x0690 1965#define regMMEA2_EDC_MODE_BASE_IDX 0 1966#define regMMEA2_ERR_STATUS 0x0691 1967#define regMMEA2_ERR_STATUS_BASE_IDX 0 1968#define regMMEA2_MISC2 0x0692 1969#define regMMEA2_MISC2_BASE_IDX 0 1970#define regMMEA2_CE_ERR_STATUS_LO 0x0694 1971#define regMMEA2_CE_ERR_STATUS_LO_BASE_IDX 0 1972#define regMMEA2_MISC_AON 0x0695 1973#define regMMEA2_MISC_AON_BASE_IDX 0 1974#define regMMEA2_CE_ERR_STATUS_HI 0x0696 1975#define regMMEA2_CE_ERR_STATUS_HI_BASE_IDX 0 1976 1977 1978// addressBlock: aid_mmhub_ea_mmeadec3 1979// base address: 0x61b00 1980#define regMMEA3_DRAM_RD_CLI2GRP_MAP0 0x06c0 1981#define regMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 1982#define regMMEA3_DRAM_RD_CLI2GRP_MAP1 0x06c1 1983#define regMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 1984#define regMMEA3_DRAM_WR_CLI2GRP_MAP0 0x06c2 1985#define regMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 1986#define regMMEA3_DRAM_WR_CLI2GRP_MAP1 0x06c3 1987#define regMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 1988#define regMMEA3_DRAM_RD_GRP2VC_MAP 0x06c4 1989#define regMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 1990#define regMMEA3_DRAM_WR_GRP2VC_MAP 0x06c5 1991#define regMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 1992#define regMMEA3_DRAM_RD_LAZY 0x06c6 1993#define regMMEA3_DRAM_RD_LAZY_BASE_IDX 0 1994#define regMMEA3_DRAM_WR_LAZY 0x06c7 1995#define regMMEA3_DRAM_WR_LAZY_BASE_IDX 0 1996#define regMMEA3_DRAM_RD_CAM_CNTL 0x06c8 1997#define regMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX 0 1998#define regMMEA3_DRAM_WR_CAM_CNTL 0x06c9 1999#define regMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX 0 2000#define regMMEA3_DRAM_PAGE_BURST 0x06ca 2001#define regMMEA3_DRAM_PAGE_BURST_BASE_IDX 0 2002#define regMMEA3_DRAM_RD_PRI_AGE 0x06cb 2003#define regMMEA3_DRAM_RD_PRI_AGE_BASE_IDX 0 2004#define regMMEA3_DRAM_WR_PRI_AGE 0x06cc 2005#define regMMEA3_DRAM_WR_PRI_AGE_BASE_IDX 0 2006#define regMMEA3_DRAM_RD_PRI_QUEUING 0x06cd 2007#define regMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX 0 2008#define regMMEA3_DRAM_WR_PRI_QUEUING 0x06ce 2009#define regMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX 0 2010#define regMMEA3_DRAM_RD_PRI_FIXED 0x06cf 2011#define regMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX 0 2012#define regMMEA3_DRAM_WR_PRI_FIXED 0x06d0 2013#define regMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX 0 2014#define regMMEA3_DRAM_RD_PRI_URGENCY 0x06d1 2015#define regMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX 0 2016#define regMMEA3_DRAM_WR_PRI_URGENCY 0x06d2 2017#define regMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX 0 2018#define regMMEA3_DRAM_RD_PRI_QUANT_PRI1 0x06d3 2019#define regMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 2020#define regMMEA3_DRAM_RD_PRI_QUANT_PRI2 0x06d4 2021#define regMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 2022#define regMMEA3_DRAM_RD_PRI_QUANT_PRI3 0x06d5 2023#define regMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 2024#define regMMEA3_DRAM_WR_PRI_QUANT_PRI1 0x06d6 2025#define regMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 2026#define regMMEA3_DRAM_WR_PRI_QUANT_PRI2 0x06d7 2027#define regMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 2028#define regMMEA3_DRAM_WR_PRI_QUANT_PRI3 0x06d8 2029#define regMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 2030#define regMMEA3_GMI_RD_CLI2GRP_MAP0 0x06d9 2031#define regMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 2032#define regMMEA3_GMI_RD_CLI2GRP_MAP1 0x06da 2033#define regMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 2034#define regMMEA3_GMI_WR_CLI2GRP_MAP0 0x06db 2035#define regMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 2036#define regMMEA3_GMI_WR_CLI2GRP_MAP1 0x06dc 2037#define regMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 2038#define regMMEA3_GMI_RD_GRP2VC_MAP 0x06dd 2039#define regMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX 0 2040#define regMMEA3_GMI_WR_GRP2VC_MAP 0x06de 2041#define regMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX 0 2042#define regMMEA3_GMI_RD_LAZY 0x06df 2043#define regMMEA3_GMI_RD_LAZY_BASE_IDX 0 2044#define regMMEA3_GMI_WR_LAZY 0x06e0 2045#define regMMEA3_GMI_WR_LAZY_BASE_IDX 0 2046#define regMMEA3_GMI_RD_CAM_CNTL 0x06e1 2047#define regMMEA3_GMI_RD_CAM_CNTL_BASE_IDX 0 2048#define regMMEA3_GMI_WR_CAM_CNTL 0x06e2 2049#define regMMEA3_GMI_WR_CAM_CNTL_BASE_IDX 0 2050#define regMMEA3_GMI_PAGE_BURST 0x06e3 2051#define regMMEA3_GMI_PAGE_BURST_BASE_IDX 0 2052#define regMMEA3_GMI_RD_PRI_AGE 0x06e4 2053#define regMMEA3_GMI_RD_PRI_AGE_BASE_IDX 0 2054#define regMMEA3_GMI_WR_PRI_AGE 0x06e5 2055#define regMMEA3_GMI_WR_PRI_AGE_BASE_IDX 0 2056#define regMMEA3_GMI_RD_PRI_QUEUING 0x06e6 2057#define regMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX 0 2058#define regMMEA3_GMI_WR_PRI_QUEUING 0x06e7 2059#define regMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX 0 2060#define regMMEA3_GMI_RD_PRI_FIXED 0x06e8 2061#define regMMEA3_GMI_RD_PRI_FIXED_BASE_IDX 0 2062#define regMMEA3_GMI_WR_PRI_FIXED 0x06e9 2063#define regMMEA3_GMI_WR_PRI_FIXED_BASE_IDX 0 2064#define regMMEA3_GMI_RD_PRI_URGENCY 0x06ea 2065#define regMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX 0 2066#define regMMEA3_GMI_WR_PRI_URGENCY 0x06eb 2067#define regMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX 0 2068#define regMMEA3_GMI_RD_PRI_URGENCY_MASKING 0x06ec 2069#define regMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 2070#define regMMEA3_GMI_WR_PRI_URGENCY_MASKING 0x06ed 2071#define regMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 2072#define regMMEA3_GMI_RD_PRI_QUANT_PRI1 0x06ee 2073#define regMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 2074#define regMMEA3_GMI_RD_PRI_QUANT_PRI2 0x06ef 2075#define regMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 2076#define regMMEA3_GMI_RD_PRI_QUANT_PRI3 0x06f0 2077#define regMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 2078#define regMMEA3_GMI_WR_PRI_QUANT_PRI1 0x06f1 2079#define regMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 2080#define regMMEA3_GMI_WR_PRI_QUANT_PRI2 0x06f2 2081#define regMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 2082#define regMMEA3_GMI_WR_PRI_QUANT_PRI3 0x06f3 2083#define regMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 2084#define regMMEA3_IO_RD_CLI2GRP_MAP0 0x0795 2085#define regMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 2086#define regMMEA3_IO_RD_CLI2GRP_MAP1 0x0796 2087#define regMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 2088#define regMMEA3_IO_WR_CLI2GRP_MAP0 0x0797 2089#define regMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 2090#define regMMEA3_IO_WR_CLI2GRP_MAP1 0x0798 2091#define regMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 2092#define regMMEA3_IO_RD_COMBINE_FLUSH 0x0799 2093#define regMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX 0 2094#define regMMEA3_IO_WR_COMBINE_FLUSH 0x079a 2095#define regMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX 0 2096#define regMMEA3_IO_GROUP_BURST 0x079b 2097#define regMMEA3_IO_GROUP_BURST_BASE_IDX 0 2098#define regMMEA3_IO_RD_PRI_AGE 0x079c 2099#define regMMEA3_IO_RD_PRI_AGE_BASE_IDX 0 2100#define regMMEA3_IO_WR_PRI_AGE 0x079d 2101#define regMMEA3_IO_WR_PRI_AGE_BASE_IDX 0 2102#define regMMEA3_IO_RD_PRI_QUEUING 0x079e 2103#define regMMEA3_IO_RD_PRI_QUEUING_BASE_IDX 0 2104#define regMMEA3_IO_WR_PRI_QUEUING 0x079f 2105#define regMMEA3_IO_WR_PRI_QUEUING_BASE_IDX 0 2106#define regMMEA3_IO_RD_PRI_FIXED 0x07a0 2107#define regMMEA3_IO_RD_PRI_FIXED_BASE_IDX 0 2108#define regMMEA3_IO_WR_PRI_FIXED 0x07a1 2109#define regMMEA3_IO_WR_PRI_FIXED_BASE_IDX 0 2110#define regMMEA3_IO_RD_PRI_URGENCY 0x07a2 2111#define regMMEA3_IO_RD_PRI_URGENCY_BASE_IDX 0 2112#define regMMEA3_IO_WR_PRI_URGENCY 0x07a3 2113#define regMMEA3_IO_WR_PRI_URGENCY_BASE_IDX 0 2114#define regMMEA3_IO_RD_PRI_URGENCY_MASKING 0x07a4 2115#define regMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 2116#define regMMEA3_IO_WR_PRI_URGENCY_MASKING 0x07a5 2117#define regMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 2118#define regMMEA3_IO_RD_PRI_QUANT_PRI1 0x07a6 2119#define regMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 2120#define regMMEA3_IO_RD_PRI_QUANT_PRI2 0x07a7 2121#define regMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 2122#define regMMEA3_IO_RD_PRI_QUANT_PRI3 0x07a8 2123#define regMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 2124#define regMMEA3_IO_WR_PRI_QUANT_PRI1 0x07a9 2125#define regMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 2126#define regMMEA3_IO_WR_PRI_QUANT_PRI2 0x07aa 2127#define regMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 2128#define regMMEA3_IO_WR_PRI_QUANT_PRI3 0x07ab 2129#define regMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 2130#define regMMEA3_SDP_ARB_DRAM 0x07ac 2131#define regMMEA3_SDP_ARB_DRAM_BASE_IDX 0 2132#define regMMEA3_SDP_ARB_GMI 0x07ad 2133#define regMMEA3_SDP_ARB_GMI_BASE_IDX 0 2134#define regMMEA3_SDP_ARB_FINAL 0x07ae 2135#define regMMEA3_SDP_ARB_FINAL_BASE_IDX 0 2136#define regMMEA3_SDP_DRAM_PRIORITY 0x07af 2137#define regMMEA3_SDP_DRAM_PRIORITY_BASE_IDX 0 2138#define regMMEA3_SDP_GMI_PRIORITY 0x07b0 2139#define regMMEA3_SDP_GMI_PRIORITY_BASE_IDX 0 2140#define regMMEA3_SDP_IO_PRIORITY 0x07b1 2141#define regMMEA3_SDP_IO_PRIORITY_BASE_IDX 0 2142#define regMMEA3_SDP_CREDITS 0x07b2 2143#define regMMEA3_SDP_CREDITS_BASE_IDX 0 2144#define regMMEA3_SDP_TAG_RESERVE0 0x07b3 2145#define regMMEA3_SDP_TAG_RESERVE0_BASE_IDX 0 2146#define regMMEA3_SDP_TAG_RESERVE1 0x07b4 2147#define regMMEA3_SDP_TAG_RESERVE1_BASE_IDX 0 2148#define regMMEA3_SDP_VCC_RESERVE0 0x07b5 2149#define regMMEA3_SDP_VCC_RESERVE0_BASE_IDX 0 2150#define regMMEA3_SDP_VCC_RESERVE1 0x07b6 2151#define regMMEA3_SDP_VCC_RESERVE1_BASE_IDX 0 2152#define regMMEA3_SDP_VCD_RESERVE0 0x07b7 2153#define regMMEA3_SDP_VCD_RESERVE0_BASE_IDX 0 2154#define regMMEA3_SDP_VCD_RESERVE1 0x07b8 2155#define regMMEA3_SDP_VCD_RESERVE1_BASE_IDX 0 2156#define regMMEA3_SDP_REQ_CNTL 0x07b9 2157#define regMMEA3_SDP_REQ_CNTL_BASE_IDX 0 2158#define regMMEA3_MISC 0x07ba 2159#define regMMEA3_MISC_BASE_IDX 0 2160#define regMMEA3_LATENCY_SAMPLING 0x07bb 2161#define regMMEA3_LATENCY_SAMPLING_BASE_IDX 0 2162#define regMMEA3_PERFCOUNTER_LO 0x07bc 2163#define regMMEA3_PERFCOUNTER_LO_BASE_IDX 0 2164#define regMMEA3_PERFCOUNTER_HI 0x07bd 2165#define regMMEA3_PERFCOUNTER_HI_BASE_IDX 0 2166#define regMMEA3_PERFCOUNTER0_CFG 0x07be 2167#define regMMEA3_PERFCOUNTER0_CFG_BASE_IDX 0 2168#define regMMEA3_PERFCOUNTER1_CFG 0x07bf 2169#define regMMEA3_PERFCOUNTER1_CFG_BASE_IDX 0 2170#define regMMEA3_PERFCOUNTER_RSLT_CNTL 0x07c0 2171#define regMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 2172#define regMMEA3_UE_ERR_STATUS_LO 0x07c6 2173#define regMMEA3_UE_ERR_STATUS_LO_BASE_IDX 0 2174#define regMMEA3_UE_ERR_STATUS_HI 0x07c7 2175#define regMMEA3_UE_ERR_STATUS_HI_BASE_IDX 0 2176#define regMMEA3_DSM_CNTL 0x07c8 2177#define regMMEA3_DSM_CNTL_BASE_IDX 0 2178#define regMMEA3_DSM_CNTLA 0x07c9 2179#define regMMEA3_DSM_CNTLA_BASE_IDX 0 2180#define regMMEA3_DSM_CNTLB 0x07ca 2181#define regMMEA3_DSM_CNTLB_BASE_IDX 0 2182#define regMMEA3_DSM_CNTL2 0x07cb 2183#define regMMEA3_DSM_CNTL2_BASE_IDX 0 2184#define regMMEA3_DSM_CNTL2A 0x07cc 2185#define regMMEA3_DSM_CNTL2A_BASE_IDX 0 2186#define regMMEA3_DSM_CNTL2B 0x07cd 2187#define regMMEA3_DSM_CNTL2B_BASE_IDX 0 2188#define regMMEA3_CGTT_CLK_CTRL 0x07cf 2189#define regMMEA3_CGTT_CLK_CTRL_BASE_IDX 0 2190#define regMMEA3_EDC_MODE 0x07d0 2191#define regMMEA3_EDC_MODE_BASE_IDX 0 2192#define regMMEA3_ERR_STATUS 0x07d1 2193#define regMMEA3_ERR_STATUS_BASE_IDX 0 2194#define regMMEA3_MISC2 0x07d2 2195#define regMMEA3_MISC2_BASE_IDX 0 2196#define regMMEA3_CE_ERR_STATUS_LO 0x07d4 2197#define regMMEA3_CE_ERR_STATUS_LO_BASE_IDX 0 2198#define regMMEA3_MISC_AON 0x07d5 2199#define regMMEA3_MISC_AON_BASE_IDX 0 2200#define regMMEA3_CE_ERR_STATUS_HI 0x07d6 2201#define regMMEA3_CE_ERR_STATUS_HI_BASE_IDX 0 2202 2203// addressBlock: aid_mmhub_ea_mmeadec4 2204// base address: 0x62000 2205#define regMMEA4_DRAM_RD_CLI2GRP_MAP0 0x0800 2206#define regMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 2207#define regMMEA4_DRAM_RD_CLI2GRP_MAP1 0x0801 2208#define regMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 2209#define regMMEA4_DRAM_WR_CLI2GRP_MAP0 0x0802 2210#define regMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 2211#define regMMEA4_DRAM_WR_CLI2GRP_MAP1 0x0803 2212#define regMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 2213#define regMMEA4_DRAM_RD_GRP2VC_MAP 0x0804 2214#define regMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 2215#define regMMEA4_DRAM_WR_GRP2VC_MAP 0x0805 2216#define regMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 2217#define regMMEA4_DRAM_RD_LAZY 0x0806 2218#define regMMEA4_DRAM_RD_LAZY_BASE_IDX 0 2219#define regMMEA4_DRAM_WR_LAZY 0x0807 2220#define regMMEA4_DRAM_WR_LAZY_BASE_IDX 0 2221#define regMMEA4_DRAM_RD_CAM_CNTL 0x0808 2222#define regMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX 0 2223#define regMMEA4_DRAM_WR_CAM_CNTL 0x0809 2224#define regMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX 0 2225#define regMMEA4_DRAM_PAGE_BURST 0x080a 2226#define regMMEA4_DRAM_PAGE_BURST_BASE_IDX 0 2227#define regMMEA4_DRAM_RD_PRI_AGE 0x080b 2228#define regMMEA4_DRAM_RD_PRI_AGE_BASE_IDX 0 2229#define regMMEA4_DRAM_WR_PRI_AGE 0x080c 2230#define regMMEA4_DRAM_WR_PRI_AGE_BASE_IDX 0 2231#define regMMEA4_DRAM_RD_PRI_QUEUING 0x080d 2232#define regMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX 0 2233#define regMMEA4_DRAM_WR_PRI_QUEUING 0x080e 2234#define regMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX 0 2235#define regMMEA4_DRAM_RD_PRI_FIXED 0x080f 2236#define regMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX 0 2237#define regMMEA4_DRAM_WR_PRI_FIXED 0x0810 2238#define regMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX 0 2239#define regMMEA4_DRAM_RD_PRI_URGENCY 0x0811 2240#define regMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX 0 2241#define regMMEA4_DRAM_WR_PRI_URGENCY 0x0812 2242#define regMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX 0 2243#define regMMEA4_DRAM_RD_PRI_QUANT_PRI1 0x0813 2244#define regMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 2245#define regMMEA4_DRAM_RD_PRI_QUANT_PRI2 0x0814 2246#define regMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 2247#define regMMEA4_DRAM_RD_PRI_QUANT_PRI3 0x0815 2248#define regMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 2249#define regMMEA4_DRAM_WR_PRI_QUANT_PRI1 0x0816 2250#define regMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 2251#define regMMEA4_DRAM_WR_PRI_QUANT_PRI2 0x0817 2252#define regMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 2253#define regMMEA4_DRAM_WR_PRI_QUANT_PRI3 0x0818 2254#define regMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 2255#define regMMEA4_GMI_RD_CLI2GRP_MAP0 0x0819 2256#define regMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 2257#define regMMEA4_GMI_RD_CLI2GRP_MAP1 0x081a 2258#define regMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 2259#define regMMEA4_GMI_WR_CLI2GRP_MAP0 0x081b 2260#define regMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 2261#define regMMEA4_GMI_WR_CLI2GRP_MAP1 0x081c 2262#define regMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 2263#define regMMEA4_GMI_RD_GRP2VC_MAP 0x081d 2264#define regMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX 0 2265#define regMMEA4_GMI_WR_GRP2VC_MAP 0x081e 2266#define regMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX 0 2267#define regMMEA4_GMI_RD_LAZY 0x081f 2268#define regMMEA4_GMI_RD_LAZY_BASE_IDX 0 2269#define regMMEA4_GMI_WR_LAZY 0x0820 2270#define regMMEA4_GMI_WR_LAZY_BASE_IDX 0 2271#define regMMEA4_GMI_RD_CAM_CNTL 0x0821 2272#define regMMEA4_GMI_RD_CAM_CNTL_BASE_IDX 0 2273#define regMMEA4_GMI_WR_CAM_CNTL 0x0822 2274#define regMMEA4_GMI_WR_CAM_CNTL_BASE_IDX 0 2275#define regMMEA4_GMI_PAGE_BURST 0x0823 2276#define regMMEA4_GMI_PAGE_BURST_BASE_IDX 0 2277#define regMMEA4_GMI_RD_PRI_AGE 0x0824 2278#define regMMEA4_GMI_RD_PRI_AGE_BASE_IDX 0 2279#define regMMEA4_GMI_WR_PRI_AGE 0x0825 2280#define regMMEA4_GMI_WR_PRI_AGE_BASE_IDX 0 2281#define regMMEA4_GMI_RD_PRI_QUEUING 0x0826 2282#define regMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX 0 2283#define regMMEA4_GMI_WR_PRI_QUEUING 0x0827 2284#define regMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX 0 2285#define regMMEA4_GMI_RD_PRI_FIXED 0x0828 2286#define regMMEA4_GMI_RD_PRI_FIXED_BASE_IDX 0 2287#define regMMEA4_GMI_WR_PRI_FIXED 0x0829 2288#define regMMEA4_GMI_WR_PRI_FIXED_BASE_IDX 0 2289#define regMMEA4_GMI_RD_PRI_URGENCY 0x082a 2290#define regMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX 0 2291#define regMMEA4_GMI_WR_PRI_URGENCY 0x082b 2292#define regMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX 0 2293#define regMMEA4_GMI_RD_PRI_URGENCY_MASKING 0x082c 2294#define regMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 2295#define regMMEA4_GMI_WR_PRI_URGENCY_MASKING 0x082d 2296#define regMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 2297#define regMMEA4_GMI_RD_PRI_QUANT_PRI1 0x082e 2298#define regMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 2299#define regMMEA4_GMI_RD_PRI_QUANT_PRI2 0x082f 2300#define regMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 2301#define regMMEA4_GMI_RD_PRI_QUANT_PRI3 0x0830 2302#define regMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 2303#define regMMEA4_GMI_WR_PRI_QUANT_PRI1 0x0831 2304#define regMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 2305#define regMMEA4_GMI_WR_PRI_QUANT_PRI2 0x0832 2306#define regMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 2307#define regMMEA4_GMI_WR_PRI_QUANT_PRI3 0x0833 2308#define regMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 2309#define regMMEA4_IO_RD_CLI2GRP_MAP0 0x08d5 2310#define regMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 2311#define regMMEA4_IO_RD_CLI2GRP_MAP1 0x08d6 2312#define regMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 2313#define regMMEA4_IO_WR_CLI2GRP_MAP0 0x08d7 2314#define regMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 2315#define regMMEA4_IO_WR_CLI2GRP_MAP1 0x08d8 2316#define regMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 2317#define regMMEA4_IO_RD_COMBINE_FLUSH 0x08d9 2318#define regMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX 0 2319#define regMMEA4_IO_WR_COMBINE_FLUSH 0x08da 2320#define regMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX 0 2321#define regMMEA4_IO_GROUP_BURST 0x08db 2322#define regMMEA4_IO_GROUP_BURST_BASE_IDX 0 2323#define regMMEA4_IO_RD_PRI_AGE 0x08dc 2324#define regMMEA4_IO_RD_PRI_AGE_BASE_IDX 0 2325#define regMMEA4_IO_WR_PRI_AGE 0x08dd 2326#define regMMEA4_IO_WR_PRI_AGE_BASE_IDX 0 2327#define regMMEA4_IO_RD_PRI_QUEUING 0x08de 2328#define regMMEA4_IO_RD_PRI_QUEUING_BASE_IDX 0 2329#define regMMEA4_IO_WR_PRI_QUEUING 0x08df 2330#define regMMEA4_IO_WR_PRI_QUEUING_BASE_IDX 0 2331#define regMMEA4_IO_RD_PRI_FIXED 0x08e0 2332#define regMMEA4_IO_RD_PRI_FIXED_BASE_IDX 0 2333#define regMMEA4_IO_WR_PRI_FIXED 0x08e1 2334#define regMMEA4_IO_WR_PRI_FIXED_BASE_IDX 0 2335#define regMMEA4_IO_RD_PRI_URGENCY 0x08e2 2336#define regMMEA4_IO_RD_PRI_URGENCY_BASE_IDX 0 2337#define regMMEA4_IO_WR_PRI_URGENCY 0x08e3 2338#define regMMEA4_IO_WR_PRI_URGENCY_BASE_IDX 0 2339#define regMMEA4_IO_RD_PRI_URGENCY_MASKING 0x08e4 2340#define regMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 2341#define regMMEA4_IO_WR_PRI_URGENCY_MASKING 0x08e5 2342#define regMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 2343#define regMMEA4_IO_RD_PRI_QUANT_PRI1 0x08e6 2344#define regMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 2345#define regMMEA4_IO_RD_PRI_QUANT_PRI2 0x08e7 2346#define regMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 2347#define regMMEA4_IO_RD_PRI_QUANT_PRI3 0x08e8 2348#define regMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 2349#define regMMEA4_IO_WR_PRI_QUANT_PRI1 0x08e9 2350#define regMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 2351#define regMMEA4_IO_WR_PRI_QUANT_PRI2 0x08ea 2352#define regMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 2353#define regMMEA4_IO_WR_PRI_QUANT_PRI3 0x08eb 2354#define regMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 2355#define regMMEA4_SDP_ARB_DRAM 0x08ec 2356#define regMMEA4_SDP_ARB_DRAM_BASE_IDX 0 2357#define regMMEA4_SDP_ARB_GMI 0x08ed 2358#define regMMEA4_SDP_ARB_GMI_BASE_IDX 0 2359#define regMMEA4_SDP_ARB_FINAL 0x08ee 2360#define regMMEA4_SDP_ARB_FINAL_BASE_IDX 0 2361#define regMMEA4_SDP_DRAM_PRIORITY 0x08ef 2362#define regMMEA4_SDP_DRAM_PRIORITY_BASE_IDX 0 2363#define regMMEA4_SDP_GMI_PRIORITY 0x08f0 2364#define regMMEA4_SDP_GMI_PRIORITY_BASE_IDX 0 2365#define regMMEA4_SDP_IO_PRIORITY 0x08f1 2366#define regMMEA4_SDP_IO_PRIORITY_BASE_IDX 0 2367#define regMMEA4_SDP_CREDITS 0x08f2 2368#define regMMEA4_SDP_CREDITS_BASE_IDX 0 2369#define regMMEA4_SDP_TAG_RESERVE0 0x08f3 2370#define regMMEA4_SDP_TAG_RESERVE0_BASE_IDX 0 2371#define regMMEA4_SDP_TAG_RESERVE1 0x08f4 2372#define regMMEA4_SDP_TAG_RESERVE1_BASE_IDX 0 2373#define regMMEA4_SDP_VCC_RESERVE0 0x08f5 2374#define regMMEA4_SDP_VCC_RESERVE0_BASE_IDX 0 2375#define regMMEA4_SDP_VCC_RESERVE1 0x08f6 2376#define regMMEA4_SDP_VCC_RESERVE1_BASE_IDX 0 2377#define regMMEA4_SDP_VCD_RESERVE0 0x08f7 2378#define regMMEA4_SDP_VCD_RESERVE0_BASE_IDX 0 2379#define regMMEA4_SDP_VCD_RESERVE1 0x08f8 2380#define regMMEA4_SDP_VCD_RESERVE1_BASE_IDX 0 2381#define regMMEA4_SDP_REQ_CNTL 0x08f9 2382#define regMMEA4_SDP_REQ_CNTL_BASE_IDX 0 2383#define regMMEA4_MISC 0x08fa 2384#define regMMEA4_MISC_BASE_IDX 0 2385#define regMMEA4_LATENCY_SAMPLING 0x08fb 2386#define regMMEA4_LATENCY_SAMPLING_BASE_IDX 0 2387#define regMMEA4_PERFCOUNTER_LO 0x08fc 2388#define regMMEA4_PERFCOUNTER_LO_BASE_IDX 0 2389#define regMMEA4_PERFCOUNTER_HI 0x08fd 2390#define regMMEA4_PERFCOUNTER_HI_BASE_IDX 0 2391#define regMMEA4_PERFCOUNTER0_CFG 0x08fe 2392#define regMMEA4_PERFCOUNTER0_CFG_BASE_IDX 0 2393#define regMMEA4_PERFCOUNTER1_CFG 0x08ff 2394#define regMMEA4_PERFCOUNTER1_CFG_BASE_IDX 0 2395#define regMMEA4_PERFCOUNTER_RSLT_CNTL 0x0900 2396#define regMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 2397#define regMMEA4_UE_ERR_STATUS_LO 0x0906 2398#define regMMEA4_UE_ERR_STATUS_LO_BASE_IDX 0 2399#define regMMEA4_UE_ERR_STATUS_HI 0x0907 2400#define regMMEA4_UE_ERR_STATUS_HI_BASE_IDX 0 2401#define regMMEA4_DSM_CNTL 0x0908 2402#define regMMEA4_DSM_CNTL_BASE_IDX 0 2403#define regMMEA4_DSM_CNTLA 0x0909 2404#define regMMEA4_DSM_CNTLA_BASE_IDX 0 2405#define regMMEA4_DSM_CNTLB 0x090a 2406#define regMMEA4_DSM_CNTLB_BASE_IDX 0 2407#define regMMEA4_DSM_CNTL2 0x090b 2408#define regMMEA4_DSM_CNTL2_BASE_IDX 0 2409#define regMMEA4_DSM_CNTL2A 0x090c 2410#define regMMEA4_DSM_CNTL2A_BASE_IDX 0 2411#define regMMEA4_DSM_CNTL2B 0x090d 2412#define regMMEA4_DSM_CNTL2B_BASE_IDX 0 2413#define regMMEA4_CGTT_CLK_CTRL 0x090f 2414#define regMMEA4_CGTT_CLK_CTRL_BASE_IDX 0 2415#define regMMEA4_EDC_MODE 0x0910 2416#define regMMEA4_EDC_MODE_BASE_IDX 0 2417#define regMMEA4_ERR_STATUS 0x0911 2418#define regMMEA4_ERR_STATUS_BASE_IDX 0 2419#define regMMEA4_MISC2 0x0912 2420#define regMMEA4_MISC2_BASE_IDX 0 2421#define regMMEA4_CE_ERR_STATUS_LO 0x0914 2422#define regMMEA4_CE_ERR_STATUS_LO_BASE_IDX 0 2423#define regMMEA4_MISC_AON 0x0915 2424#define regMMEA4_MISC_AON_BASE_IDX 0 2425#define regMMEA4_CE_ERR_STATUS_HI 0x0916 2426#define regMMEA4_CE_ERR_STATUS_HI_BASE_IDX 0 2427 2428// addressBlock: aid_mmhub_pctldec0 2429// base address: 0x62a00 2430#define regPCTL0_CTRL 0x0a80 2431#define regPCTL0_CTRL_BASE_IDX 0 2432#define regPCTL0_MMHUB_DEEPSLEEP_IB 0x0a81 2433#define regPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX 0 2434#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0x0a82 2435#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 2436#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0a83 2437#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0 2438#define regPCTL0_PG_IGNORE_DEEPSLEEP 0x0a84 2439#define regPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 2440#define regPCTL0_PG_IGNORE_DEEPSLEEP_IB 0x0a85 2441#define regPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0 2442#define regPCTL0_SLICE0_CFG_DAGB_BUSY 0x0a86 2443#define regPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX 0 2444#define regPCTL0_SLICE0_CFG_DS_ALLOW 0x0a87 2445#define regPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX 0 2446#define regPCTL0_SLICE0_CFG_DS_ALLOW_IB 0x0a88 2447#define regPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0 2448#define regPCTL0_SLICE1_CFG_DAGB_BUSY 0x0a89 2449#define regPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX 0 2450#define regPCTL0_SLICE1_CFG_DS_ALLOW 0x0a8a 2451#define regPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX 0 2452#define regPCTL0_SLICE1_CFG_DS_ALLOW_IB 0x0a8b 2453#define regPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0 2454#define regPCTL0_SLICE2_CFG_DAGB_BUSY 0x0a8c 2455#define regPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX 0 2456#define regPCTL0_SLICE2_CFG_DS_ALLOW 0x0a8d 2457#define regPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX 0 2458#define regPCTL0_SLICE2_CFG_DS_ALLOW_IB 0x0a8e 2459#define regPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 0 2460#define regPCTL0_SLICE3_CFG_DAGB_BUSY 0x0a8f 2461#define regPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX 0 2462#define regPCTL0_SLICE3_CFG_DS_ALLOW 0x0a90 2463#define regPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX 0 2464#define regPCTL0_SLICE3_CFG_DS_ALLOW_IB 0x0a91 2465#define regPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 0 2466#define regPCTL0_SLICE4_CFG_DAGB_BUSY 0x0a92 2467#define regPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX 0 2468#define regPCTL0_SLICE4_CFG_DS_ALLOW 0x0a93 2469#define regPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX 0 2470#define regPCTL0_SLICE4_CFG_DS_ALLOW_IB 0x0a94 2471#define regPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 0 2472#define regPCTL0_UTCL2_MISC 0x0a95 2473#define regPCTL0_UTCL2_MISC_BASE_IDX 0 2474#define regPCTL0_SLICE0_MISC 0x0a96 2475#define regPCTL0_SLICE0_MISC_BASE_IDX 0 2476#define regPCTL0_SLICE1_MISC 0x0a97 2477#define regPCTL0_SLICE1_MISC_BASE_IDX 0 2478#define regPCTL0_SLICE2_MISC 0x0a98 2479#define regPCTL0_SLICE2_MISC_BASE_IDX 0 2480#define regPCTL0_SLICE3_MISC 0x0a99 2481#define regPCTL0_SLICE3_MISC_BASE_IDX 0 2482#define regPCTL0_SLICE4_MISC 0x0a9a 2483#define regPCTL0_SLICE4_MISC_BASE_IDX 0 2484 2485 2486// addressBlock: aid_mmhub_l1tlb_vml1dec 2487// base address: 0x62c00 2488#define regMC_VM_MX_L1_TLB0_STATUS 0x0b08 2489#define regMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 2490#define regMC_VM_MX_L1_TLB1_STATUS 0x0b09 2491#define regMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 2492#define regMC_VM_MX_L1_TLB2_STATUS 0x0b0a 2493#define regMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 2494#define regMC_VM_MX_L1_TLB3_STATUS 0x0b0b 2495#define regMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 2496#define regMC_VM_MX_L1_TLB4_STATUS 0x0b0c 2497#define regMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 2498#define regMC_VM_MX_L1_TLB5_STATUS 0x0b0d 2499#define regMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 2500#define regMC_VM_MX_L1_TLB6_STATUS 0x0b0e 2501#define regMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 2502#define regMC_VM_MX_L1_TLB7_STATUS 0x0b0f 2503#define regMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 2504 2505 2506// addressBlock: aid_mmhub_l1tlb_vml1pldec 2507// base address: 0x62c80 2508#define regMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0b20 2509#define regMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 2510#define regMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0b21 2511#define regMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 2512#define regMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0b22 2513#define regMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 2514#define regMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0b23 2515#define regMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 2516#define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0b24 2517#define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 2518 2519 2520// addressBlock: aid_mmhub_l1tlb_vml1prdec 2521// base address: 0x62cc0 2522#define regMC_VM_MX_L1_PERFCOUNTER_LO 0x0b30 2523#define regMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 2524#define regMC_VM_MX_L1_PERFCOUNTER_HI 0x0b31 2525#define regMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 2526 2527 2528// addressBlock: aid_mmhub_utcl2_atcl2dec 2529// base address: 0x62d00 2530#define regATC_L2_CNTL 0x0b40 2531#define regATC_L2_CNTL_BASE_IDX 0 2532#define regATC_L2_CNTL2 0x0b41 2533#define regATC_L2_CNTL2_BASE_IDX 0 2534#define regATC_L2_CACHE_DATA0 0x0b44 2535#define regATC_L2_CACHE_DATA0_BASE_IDX 0 2536#define regATC_L2_CACHE_DATA1 0x0b45 2537#define regATC_L2_CACHE_DATA1_BASE_IDX 0 2538#define regATC_L2_CACHE_DATA2 0x0b46 2539#define regATC_L2_CACHE_DATA2_BASE_IDX 0 2540#define regATC_L2_CACHE_DATA3 0x0b47 2541#define regATC_L2_CACHE_DATA3_BASE_IDX 0 2542#define regATC_L2_CNTL3 0x0b48 2543#define regATC_L2_CNTL3_BASE_IDX 0 2544#define regATC_L2_STATUS 0x0b49 2545#define regATC_L2_STATUS_BASE_IDX 0 2546#define regATC_L2_STATUS2 0x0b4a 2547#define regATC_L2_STATUS2_BASE_IDX 0 2548#define regATC_L2_MISC_CG 0x0b4b 2549#define regATC_L2_MISC_CG_BASE_IDX 0 2550#define regATC_L2_MEM_POWER_LS 0x0b4c 2551#define regATC_L2_MEM_POWER_LS_BASE_IDX 0 2552#define regATC_L2_CGTT_CLK_CTRL 0x0b4d 2553#define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 2554#define regATC_L2_CACHE_4K_DSM_INDEX 0x0b4f 2555#define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0 2556#define regATC_L2_CACHE_32K_DSM_INDEX 0x0b50 2557#define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0 2558#define regATC_L2_CACHE_2M_DSM_INDEX 0x0b51 2559#define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0 2560#define regATC_L2_CACHE_4K_DSM_CNTL 0x0b52 2561#define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0 2562#define regATC_L2_CACHE_32K_DSM_CNTL 0x0b53 2563#define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0 2564#define regATC_L2_CACHE_2M_DSM_CNTL 0x0b54 2565#define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0 2566#define regATC_L2_CNTL4 0x0b55 2567#define regATC_L2_CNTL4_BASE_IDX 0 2568#define regATC_L2_MM_GROUP_RT_CLASSES 0x0b56 2569#define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 2570 2571 2572// addressBlock: aid_mmhub_utcl2_vml2pfdec 2573// base address: 0x62d80 2574#define regVM_L2_CNTL 0x0b60 2575#define regVM_L2_CNTL_BASE_IDX 0 2576#define regVM_L2_CNTL2 0x0b61 2577#define regVM_L2_CNTL2_BASE_IDX 0 2578#define regVM_L2_CNTL3 0x0b62 2579#define regVM_L2_CNTL3_BASE_IDX 0 2580#define regVM_L2_STATUS 0x0b63 2581#define regVM_L2_STATUS_BASE_IDX 0 2582#define regVM_DUMMY_PAGE_FAULT_CNTL 0x0b64 2583#define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 2584#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0b65 2585#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 2586#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0b66 2587#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 2588#define regVM_L2_PROTECTION_FAULT_CNTL 0x0b67 2589#define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 2590#define regVM_L2_PROTECTION_FAULT_CNTL2 0x0b68 2591#define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 2592#define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0b69 2593#define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 2594#define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x0b6a 2595#define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 2596#define regVM_L2_PROTECTION_FAULT_STATUS 0x0b6b 2597#define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 2598#define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x0b6c 2599#define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 2600#define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x0b6d 2601#define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 2602#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x0b6e 2603#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 2604#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0b6f 2605#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 2606#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0b71 2607#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 2608#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0b72 2609#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 2610#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0b73 2611#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 2612#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0b74 2613#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 2614#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0b75 2615#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 2616#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0b76 2617#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 2618#define regVM_L2_CNTL4 0x0b77 2619#define regVM_L2_CNTL4_BASE_IDX 0 2620#define regVM_L2_CNTL5 0x0b78 2621#define regVM_L2_CNTL5_BASE_IDX 0 2622#define regVM_L2_MM_GROUP_RT_CLASSES 0x0b79 2623#define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 2624#define regVM_L2_BANK_SELECT_RESERVED_CID 0x0b7a 2625#define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 2626#define regVM_L2_BANK_SELECT_RESERVED_CID2 0x0b7b 2627#define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 2628#define regVM_L2_CACHE_PARITY_CNTL 0x0b7c 2629#define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 2630#define regVM_L2_CGTT_CLK_CTRL 0x0b7d 2631#define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 2632#define regVM_L2_CGTT_BUSY_CTRL 0x0b7e 2633#define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 2634#define regVML2_MEM_ECC_INDEX 0x0b82 2635#define regVML2_MEM_ECC_INDEX_BASE_IDX 0 2636#define regVML2_WALKER_MEM_ECC_INDEX 0x0b83 2637#define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 2638#define regUTCL2_MEM_ECC_INDEX 0x0b84 2639#define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0 2640#define regVML2_MEM_ECC_CNTL 0x0b85 2641#define regVML2_MEM_ECC_CNTL_BASE_IDX 0 2642#define regVML2_WALKER_MEM_ECC_CNTL 0x0b86 2643#define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0 2644#define regUTCL2_MEM_ECC_CNTL 0x0b87 2645#define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0 2646#define regVML2_MEM_ECC_STATUS 0x0b88 2647#define regVML2_MEM_ECC_STATUS_BASE_IDX 0 2648#define regVML2_WALKER_MEM_ECC_STATUS 0x0b89 2649#define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0 2650#define regUTCL2_MEM_ECC_STATUS 0x0b8a 2651#define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0 2652#define regUTCL2_EDC_MODE 0x0b8b 2653#define regUTCL2_EDC_MODE_BASE_IDX 0 2654#define regUTCL2_EDC_CONFIG 0x0b8c 2655#define regUTCL2_EDC_CONFIG_BASE_IDX 0 2656 2657 2658// addressBlock: aid_mmhub_utcl2_vml2vcdec 2659// base address: 0x62e80 2660#define regVM_CONTEXT0_CNTL 0x0ba0 2661#define regVM_CONTEXT0_CNTL_BASE_IDX 0 2662#define regVM_CONTEXT1_CNTL 0x0ba1 2663#define regVM_CONTEXT1_CNTL_BASE_IDX 0 2664#define regVM_CONTEXT2_CNTL 0x0ba2 2665#define regVM_CONTEXT2_CNTL_BASE_IDX 0 2666#define regVM_CONTEXT3_CNTL 0x0ba3 2667#define regVM_CONTEXT3_CNTL_BASE_IDX 0 2668#define regVM_CONTEXT4_CNTL 0x0ba4 2669#define regVM_CONTEXT4_CNTL_BASE_IDX 0 2670#define regVM_CONTEXT5_CNTL 0x0ba5 2671#define regVM_CONTEXT5_CNTL_BASE_IDX 0 2672#define regVM_CONTEXT6_CNTL 0x0ba6 2673#define regVM_CONTEXT6_CNTL_BASE_IDX 0 2674#define regVM_CONTEXT7_CNTL 0x0ba7 2675#define regVM_CONTEXT7_CNTL_BASE_IDX 0 2676#define regVM_CONTEXT8_CNTL 0x0ba8 2677#define regVM_CONTEXT8_CNTL_BASE_IDX 0 2678#define regVM_CONTEXT9_CNTL 0x0ba9 2679#define regVM_CONTEXT9_CNTL_BASE_IDX 0 2680#define regVM_CONTEXT10_CNTL 0x0baa 2681#define regVM_CONTEXT10_CNTL_BASE_IDX 0 2682#define regVM_CONTEXT11_CNTL 0x0bab 2683#define regVM_CONTEXT11_CNTL_BASE_IDX 0 2684#define regVM_CONTEXT12_CNTL 0x0bac 2685#define regVM_CONTEXT12_CNTL_BASE_IDX 0 2686#define regVM_CONTEXT13_CNTL 0x0bad 2687#define regVM_CONTEXT13_CNTL_BASE_IDX 0 2688#define regVM_CONTEXT14_CNTL 0x0bae 2689#define regVM_CONTEXT14_CNTL_BASE_IDX 0 2690#define regVM_CONTEXT15_CNTL 0x0baf 2691#define regVM_CONTEXT15_CNTL_BASE_IDX 0 2692#define regVM_CONTEXTS_DISABLE 0x0bb0 2693#define regVM_CONTEXTS_DISABLE_BASE_IDX 0 2694#define regVM_INVALIDATE_ENG0_SEM 0x0bb1 2695#define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 2696#define regVM_INVALIDATE_ENG1_SEM 0x0bb2 2697#define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 2698#define regVM_INVALIDATE_ENG2_SEM 0x0bb3 2699#define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 2700#define regVM_INVALIDATE_ENG3_SEM 0x0bb4 2701#define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 2702#define regVM_INVALIDATE_ENG4_SEM 0x0bb5 2703#define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 2704#define regVM_INVALIDATE_ENG5_SEM 0x0bb6 2705#define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 2706#define regVM_INVALIDATE_ENG6_SEM 0x0bb7 2707#define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 2708#define regVM_INVALIDATE_ENG7_SEM 0x0bb8 2709#define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 2710#define regVM_INVALIDATE_ENG8_SEM 0x0bb9 2711#define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 2712#define regVM_INVALIDATE_ENG9_SEM 0x0bba 2713#define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 2714#define regVM_INVALIDATE_ENG10_SEM 0x0bbb 2715#define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 2716#define regVM_INVALIDATE_ENG11_SEM 0x0bbc 2717#define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 2718#define regVM_INVALIDATE_ENG12_SEM 0x0bbd 2719#define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 2720#define regVM_INVALIDATE_ENG13_SEM 0x0bbe 2721#define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 2722#define regVM_INVALIDATE_ENG14_SEM 0x0bbf 2723#define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 2724#define regVM_INVALIDATE_ENG15_SEM 0x0bc0 2725#define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 2726#define regVM_INVALIDATE_ENG16_SEM 0x0bc1 2727#define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 2728#define regVM_INVALIDATE_ENG17_SEM 0x0bc2 2729#define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 2730#define regVM_INVALIDATE_ENG0_REQ 0x0bc3 2731#define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 2732#define regVM_INVALIDATE_ENG1_REQ 0x0bc4 2733#define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 2734#define regVM_INVALIDATE_ENG2_REQ 0x0bc5 2735#define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 2736#define regVM_INVALIDATE_ENG3_REQ 0x0bc6 2737#define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 2738#define regVM_INVALIDATE_ENG4_REQ 0x0bc7 2739#define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 2740#define regVM_INVALIDATE_ENG5_REQ 0x0bc8 2741#define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 2742#define regVM_INVALIDATE_ENG6_REQ 0x0bc9 2743#define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 2744#define regVM_INVALIDATE_ENG7_REQ 0x0bca 2745#define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 2746#define regVM_INVALIDATE_ENG8_REQ 0x0bcb 2747#define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 2748#define regVM_INVALIDATE_ENG9_REQ 0x0bcc 2749#define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 2750#define regVM_INVALIDATE_ENG10_REQ 0x0bcd 2751#define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 2752#define regVM_INVALIDATE_ENG11_REQ 0x0bce 2753#define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 2754#define regVM_INVALIDATE_ENG12_REQ 0x0bcf 2755#define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 2756#define regVM_INVALIDATE_ENG13_REQ 0x0bd0 2757#define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 2758#define regVM_INVALIDATE_ENG14_REQ 0x0bd1 2759#define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 2760#define regVM_INVALIDATE_ENG15_REQ 0x0bd2 2761#define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 2762#define regVM_INVALIDATE_ENG16_REQ 0x0bd3 2763#define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 2764#define regVM_INVALIDATE_ENG17_REQ 0x0bd4 2765#define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 2766#define regVM_INVALIDATE_ENG0_ACK 0x0bd5 2767#define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 2768#define regVM_INVALIDATE_ENG1_ACK 0x0bd6 2769#define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 2770#define regVM_INVALIDATE_ENG2_ACK 0x0bd7 2771#define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 2772#define regVM_INVALIDATE_ENG3_ACK 0x0bd8 2773#define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 2774#define regVM_INVALIDATE_ENG4_ACK 0x0bd9 2775#define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 2776#define regVM_INVALIDATE_ENG5_ACK 0x0bda 2777#define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 2778#define regVM_INVALIDATE_ENG6_ACK 0x0bdb 2779#define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 2780#define regVM_INVALIDATE_ENG7_ACK 0x0bdc 2781#define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 2782#define regVM_INVALIDATE_ENG8_ACK 0x0bdd 2783#define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 2784#define regVM_INVALIDATE_ENG9_ACK 0x0bde 2785#define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 2786#define regVM_INVALIDATE_ENG10_ACK 0x0bdf 2787#define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 2788#define regVM_INVALIDATE_ENG11_ACK 0x0be0 2789#define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 2790#define regVM_INVALIDATE_ENG12_ACK 0x0be1 2791#define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 2792#define regVM_INVALIDATE_ENG13_ACK 0x0be2 2793#define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 2794#define regVM_INVALIDATE_ENG14_ACK 0x0be3 2795#define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 2796#define regVM_INVALIDATE_ENG15_ACK 0x0be4 2797#define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 2798#define regVM_INVALIDATE_ENG16_ACK 0x0be5 2799#define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 2800#define regVM_INVALIDATE_ENG17_ACK 0x0be6 2801#define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 2802#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0be7 2803#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 2804#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0be8 2805#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 2806#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0be9 2807#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 2808#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0bea 2809#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 2810#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0beb 2811#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 2812#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0bec 2813#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 2814#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0bed 2815#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 2816#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0bee 2817#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 2818#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0bef 2819#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 2820#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0bf0 2821#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 2822#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0bf1 2823#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 2824#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0bf2 2825#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 2826#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0bf3 2827#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 2828#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0bf4 2829#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 2830#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0bf5 2831#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 2832#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0bf6 2833#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 2834#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0bf7 2835#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 2836#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0bf8 2837#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 2838#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0bf9 2839#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 2840#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0bfa 2841#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 2842#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0bfb 2843#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 2844#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0bfc 2845#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 2846#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0bfd 2847#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 2848#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0bfe 2849#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 2850#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0bff 2851#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 2852#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0c00 2853#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 2854#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0c01 2855#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 2856#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0c02 2857#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 2858#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0c03 2859#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 2860#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0c04 2861#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 2862#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0c05 2863#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 2864#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0c06 2865#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 2866#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0c07 2867#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 2868#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0c08 2869#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 2870#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0c09 2871#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 2872#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0c0a 2873#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 2874#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0c0b 2875#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2876#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0c0c 2877#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2878#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0c0d 2879#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2880#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0c0e 2881#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2882#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0c0f 2883#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2884#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0c10 2885#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2886#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0c11 2887#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2888#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0c12 2889#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2890#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0c13 2891#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2892#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0c14 2893#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2894#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0c15 2895#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2896#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0c16 2897#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2898#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0c17 2899#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2900#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0c18 2901#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2902#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0c19 2903#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2904#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0c1a 2905#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2906#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0c1b 2907#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2908#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0c1c 2909#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2910#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0c1d 2911#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2912#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0c1e 2913#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2914#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0c1f 2915#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2916#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0c20 2917#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2918#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0c21 2919#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2920#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0c22 2921#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2922#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0c23 2923#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2924#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0c24 2925#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2926#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0c25 2927#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2928#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0c26 2929#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2930#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0c27 2931#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2932#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0c28 2933#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2934#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0c29 2935#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 2936#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0c2a 2937#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 2938#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0c2b 2939#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2940#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0c2c 2941#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2942#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0c2d 2943#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2944#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0c2e 2945#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2946#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0c2f 2947#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2948#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0c30 2949#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2950#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0c31 2951#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2952#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0c32 2953#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2954#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0c33 2955#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2956#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0c34 2957#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2958#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0c35 2959#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2960#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0c36 2961#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2962#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0c37 2963#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2964#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0c38 2965#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2966#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0c39 2967#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2968#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0c3a 2969#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2970#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0c3b 2971#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2972#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0c3c 2973#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2974#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0c3d 2975#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2976#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0c3e 2977#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2978#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0c3f 2979#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2980#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0c40 2981#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2982#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0c41 2983#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2984#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0c42 2985#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2986#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0c43 2987#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2988#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0c44 2989#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2990#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0c45 2991#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2992#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0c46 2993#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2994#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0c47 2995#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 2996#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0c48 2997#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 2998#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0c49 2999#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3000#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0c4a 3001#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3002#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0c4b 3003#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3004#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0c4c 3005#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3006#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0c4d 3007#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3008#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0c4e 3009#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3010#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0c4f 3011#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3012#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0c50 3013#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3014#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0c51 3015#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3016#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0c52 3017#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3018#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0c53 3019#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3020#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0c54 3021#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3022#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0c55 3023#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3024#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0c56 3025#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3026#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0c57 3027#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3028#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0c58 3029#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3030#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0c59 3031#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3032#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0c5a 3033#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3034#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0c5b 3035#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3036#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0c5c 3037#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3038#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0c5d 3039#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3040#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0c5e 3041#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3042#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0c5f 3043#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3044#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0c60 3045#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3046#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0c61 3047#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3048#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0c62 3049#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3050#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0c63 3051#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3052#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0c64 3053#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3054#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0c65 3055#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3056#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0c66 3057#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3058#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0c67 3059#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3060#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0c68 3061#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3062#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0c69 3063#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3064#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0c6a 3065#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3066 3067 3068// addressBlock: aid_mmhub_utcl2_vmsharedpfdec 3069// base address: 0x63200 3070#define regMC_VM_NB_MMIOBASE 0x0c80 3071#define regMC_VM_NB_MMIOBASE_BASE_IDX 0 3072#define regMC_VM_NB_MMIOLIMIT 0x0c81 3073#define regMC_VM_NB_MMIOLIMIT_BASE_IDX 0 3074#define regMC_VM_NB_PCI_CTRL 0x0c82 3075#define regMC_VM_NB_PCI_CTRL_BASE_IDX 0 3076#define regMC_VM_NB_PCI_ARB 0x0c83 3077#define regMC_VM_NB_PCI_ARB_BASE_IDX 0 3078#define regMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0c84 3079#define regMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 3080#define regMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0c85 3081#define regMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 3082#define regMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0c86 3083#define regMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 3084#define regMC_VM_FB_OFFSET 0x0c87 3085#define regMC_VM_FB_OFFSET_BASE_IDX 0 3086#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0c88 3087#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 3088#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0c89 3089#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 3090#define regMC_VM_STEERING 0x0c8a 3091#define regMC_VM_STEERING_BASE_IDX 0 3092#define regMC_SHARED_VIRT_RESET_REQ 0x0c8b 3093#define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 3094#define regMC_MEM_POWER_LS 0x0c8c 3095#define regMC_MEM_POWER_LS_BASE_IDX 0 3096#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0c8d 3097#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 3098#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0c8e 3099#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 3100#define regMC_VM_APT_CNTL 0x0c91 3101#define regMC_VM_APT_CNTL_BASE_IDX 0 3102#define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0c92 3103#define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 3104#define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0c93 3105#define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 3106#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0c94 3107#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 3108#define regUTCL2_CGTT_CLK_CTRL 0x0c95 3109#define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 3110#define regMC_VM_XGMI_LFB_CNTL 0x0c97 3111#define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 3112#define regMC_VM_XGMI_LFB_SIZE 0x0c98 3113#define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 3114#define regMC_VM_CACHEABLE_DRAM_CNTL 0x0c99 3115#define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 3116#define regMC_VM_HOST_MAPPING 0x0c9a 3117#define regMC_VM_HOST_MAPPING_BASE_IDX 0 3118 3119 3120// addressBlock: aid_mmhub_utcl2_vmsharedvcdec 3121// base address: 0x63270 3122#define regMC_VM_FB_LOCATION_BASE 0x0c9c 3123#define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0 3124#define regMC_VM_FB_LOCATION_TOP 0x0c9d 3125#define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0 3126#define regMC_VM_AGP_TOP 0x0c9e 3127#define regMC_VM_AGP_TOP_BASE_IDX 0 3128#define regMC_VM_AGP_BOT 0x0c9f 3129#define regMC_VM_AGP_BOT_BASE_IDX 0 3130#define regMC_VM_AGP_BASE 0x0ca0 3131#define regMC_VM_AGP_BASE_BASE_IDX 0 3132#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0ca1 3133#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 3134#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0ca2 3135#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 3136#define regMC_VM_MX_L1_TLB_CNTL 0x0ca3 3137#define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 3138 3139 3140// addressBlock: aid_mmhub_utcl2_vmsharedhvdec 3141// base address: 0x632b0 3142#define regMC_VM_FB_SIZE_OFFSET_VF0 0x0cac 3143#define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 3144#define regMC_VM_FB_SIZE_OFFSET_VF1 0x0cad 3145#define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 3146#define regMC_VM_FB_SIZE_OFFSET_VF2 0x0cae 3147#define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 3148#define regMC_VM_FB_SIZE_OFFSET_VF3 0x0caf 3149#define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 3150#define regMC_VM_FB_SIZE_OFFSET_VF4 0x0cb0 3151#define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 3152#define regMC_VM_FB_SIZE_OFFSET_VF5 0x0cb1 3153#define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 3154#define regMC_VM_FB_SIZE_OFFSET_VF6 0x0cb2 3155#define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 3156#define regMC_VM_FB_SIZE_OFFSET_VF7 0x0cb3 3157#define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 3158#define regMC_VM_FB_SIZE_OFFSET_VF8 0x0cb4 3159#define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 3160#define regMC_VM_FB_SIZE_OFFSET_VF9 0x0cb5 3161#define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 3162#define regMC_VM_FB_SIZE_OFFSET_VF10 0x0cb6 3163#define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 3164#define regMC_VM_FB_SIZE_OFFSET_VF11 0x0cb7 3165#define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 3166#define regMC_VM_FB_SIZE_OFFSET_VF12 0x0cb8 3167#define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 3168#define regMC_VM_FB_SIZE_OFFSET_VF13 0x0cb9 3169#define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 3170#define regMC_VM_FB_SIZE_OFFSET_VF14 0x0cba 3171#define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 3172#define regMC_VM_FB_SIZE_OFFSET_VF15 0x0cbb 3173#define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 3174#define regVM_IOMMU_MMIO_CNTRL_1 0x0cbc 3175#define regVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0 3176#define regMC_VM_MARC_BASE_LO_0 0x0cbd 3177#define regMC_VM_MARC_BASE_LO_0_BASE_IDX 0 3178#define regMC_VM_MARC_BASE_LO_1 0x0cbe 3179#define regMC_VM_MARC_BASE_LO_1_BASE_IDX 0 3180#define regMC_VM_MARC_BASE_LO_2 0x0cbf 3181#define regMC_VM_MARC_BASE_LO_2_BASE_IDX 0 3182#define regMC_VM_MARC_BASE_LO_3 0x0cc0 3183#define regMC_VM_MARC_BASE_LO_3_BASE_IDX 0 3184#define regMC_VM_MARC_BASE_HI_0 0x0cc1 3185#define regMC_VM_MARC_BASE_HI_0_BASE_IDX 0 3186#define regMC_VM_MARC_BASE_HI_1 0x0cc2 3187#define regMC_VM_MARC_BASE_HI_1_BASE_IDX 0 3188#define regMC_VM_MARC_BASE_HI_2 0x0cc3 3189#define regMC_VM_MARC_BASE_HI_2_BASE_IDX 0 3190#define regMC_VM_MARC_BASE_HI_3 0x0cc4 3191#define regMC_VM_MARC_BASE_HI_3_BASE_IDX 0 3192#define regMC_VM_MARC_RELOC_LO_0 0x0cc5 3193#define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 3194#define regMC_VM_MARC_RELOC_LO_1 0x0cc6 3195#define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 3196#define regMC_VM_MARC_RELOC_LO_2 0x0cc7 3197#define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 3198#define regMC_VM_MARC_RELOC_LO_3 0x0cc8 3199#define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 3200#define regMC_VM_MARC_RELOC_HI_0 0x0cc9 3201#define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 3202#define regMC_VM_MARC_RELOC_HI_1 0x0cca 3203#define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 3204#define regMC_VM_MARC_RELOC_HI_2 0x0ccb 3205#define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 3206#define regMC_VM_MARC_RELOC_HI_3 0x0ccc 3207#define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 3208#define regMC_VM_MARC_LEN_LO_0 0x0ccd 3209#define regMC_VM_MARC_LEN_LO_0_BASE_IDX 0 3210#define regMC_VM_MARC_LEN_LO_1 0x0cce 3211#define regMC_VM_MARC_LEN_LO_1_BASE_IDX 0 3212#define regMC_VM_MARC_LEN_LO_2 0x0ccf 3213#define regMC_VM_MARC_LEN_LO_2_BASE_IDX 0 3214#define regMC_VM_MARC_LEN_LO_3 0x0cd0 3215#define regMC_VM_MARC_LEN_LO_3_BASE_IDX 0 3216#define regMC_VM_MARC_LEN_HI_0 0x0cd1 3217#define regMC_VM_MARC_LEN_HI_0_BASE_IDX 0 3218#define regMC_VM_MARC_LEN_HI_1 0x0cd2 3219#define regMC_VM_MARC_LEN_HI_1_BASE_IDX 0 3220#define regMC_VM_MARC_LEN_HI_2 0x0cd3 3221#define regMC_VM_MARC_LEN_HI_2_BASE_IDX 0 3222#define regMC_VM_MARC_LEN_HI_3 0x0cd4 3223#define regMC_VM_MARC_LEN_HI_3_BASE_IDX 0 3224#define regVM_IOMMU_CONTROL_REGISTER 0x0cd5 3225#define regVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 3226#define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0cd6 3227#define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 3228#define regVM_PCIE_ATS_CNTL 0x0cd7 3229#define regVM_PCIE_ATS_CNTL_BASE_IDX 0 3230#define regVM_PCIE_ATS_CNTL_VF_0 0x0cd8 3231#define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 3232#define regVM_PCIE_ATS_CNTL_VF_1 0x0cd9 3233#define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 3234#define regVM_PCIE_ATS_CNTL_VF_2 0x0cda 3235#define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 3236#define regVM_PCIE_ATS_CNTL_VF_3 0x0cdb 3237#define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 3238#define regVM_PCIE_ATS_CNTL_VF_4 0x0cdc 3239#define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 3240#define regVM_PCIE_ATS_CNTL_VF_5 0x0cdd 3241#define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 3242#define regVM_PCIE_ATS_CNTL_VF_6 0x0cde 3243#define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 3244#define regVM_PCIE_ATS_CNTL_VF_7 0x0cdf 3245#define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 3246#define regVM_PCIE_ATS_CNTL_VF_8 0x0ce0 3247#define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 3248#define regVM_PCIE_ATS_CNTL_VF_9 0x0ce1 3249#define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 3250#define regVM_PCIE_ATS_CNTL_VF_10 0x0ce2 3251#define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 3252#define regVM_PCIE_ATS_CNTL_VF_11 0x0ce3 3253#define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 3254#define regVM_PCIE_ATS_CNTL_VF_12 0x0ce4 3255#define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 3256#define regVM_PCIE_ATS_CNTL_VF_13 0x0ce5 3257#define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 3258#define regVM_PCIE_ATS_CNTL_VF_14 0x0ce6 3259#define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 3260#define regVM_PCIE_ATS_CNTL_VF_15 0x0ce7 3261#define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 3262#define regMC_SHARED_ACTIVE_FCN_ID 0x0ce8 3263#define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 3264#define regMC_VM_XGMI_GPUIOV_ENABLE 0x0ce9 3265#define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 0 3266 3267 3268// addressBlock: aid_mmhub_utcl2_atcl2pfcntrdec 3269// base address: 0x633b0 3270#define regATC_L2_PERFCOUNTER_LO 0x0cec 3271#define regATC_L2_PERFCOUNTER_LO_BASE_IDX 0 3272#define regATC_L2_PERFCOUNTER_HI 0x0ced 3273#define regATC_L2_PERFCOUNTER_HI_BASE_IDX 0 3274 3275 3276// addressBlock: aid_mmhub_utcl2_atcl2pfcntldec 3277// base address: 0x633b8 3278#define regATC_L2_PERFCOUNTER0_CFG 0x0cee 3279#define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 3280#define regATC_L2_PERFCOUNTER1_CFG 0x0cef 3281#define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 3282#define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x0cf0 3283#define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 3284 3285 3286// addressBlock: aid_mmhub_utcl2_vml2pldec 3287// base address: 0x633d0 3288#define regMC_VM_L2_PERFCOUNTER0_CFG 0x0cf4 3289#define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 3290#define regMC_VM_L2_PERFCOUNTER1_CFG 0x0cf5 3291#define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 3292#define regMC_VM_L2_PERFCOUNTER2_CFG 0x0cf6 3293#define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 3294#define regMC_VM_L2_PERFCOUNTER3_CFG 0x0cf7 3295#define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 3296#define regMC_VM_L2_PERFCOUNTER4_CFG 0x0cf8 3297#define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 3298#define regMC_VM_L2_PERFCOUNTER5_CFG 0x0cf9 3299#define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 3300#define regMC_VM_L2_PERFCOUNTER6_CFG 0x0cfa 3301#define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 3302#define regMC_VM_L2_PERFCOUNTER7_CFG 0x0cfb 3303#define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 3304#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x0d04 3305#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 3306 3307 3308// addressBlock: aid_mmhub_utcl2_vml2prdec 3309// base address: 0x63430 3310#define regMC_VM_L2_PERFCOUNTER_LO 0x0d0c 3311#define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 3312#define regMC_VM_L2_PERFCOUNTER_HI 0x0d0d 3313#define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 3314 3315 3316// addressBlock: aid_mmhub_utcl2_l2tlbdec 3317// base address: 0x63470 3318#define regL2TLB_TLB0_STATUS 0x0d1d 3319#define regL2TLB_TLB0_STATUS_BASE_IDX 0 3320#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0d1f 3321#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 3322#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0d20 3323#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 3324#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0d21 3325#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 3326#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0d22 3327#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 3328 3329 3330// addressBlock: aid_mmhub_utcl2_l2tlbpldec 3331// base address: 0x63490 3332#define regL2TLB_PERFCOUNTER0_CFG 0x0d24 3333#define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 0 3334#define regL2TLB_PERFCOUNTER1_CFG 0x0d25 3335#define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 0 3336#define regL2TLB_PERFCOUNTER2_CFG 0x0d26 3337#define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 0 3338#define regL2TLB_PERFCOUNTER3_CFG 0x0d27 3339#define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 0 3340#define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x0d28 3341#define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 3342 3343 3344// addressBlock: aid_mmhub_utcl2_l2tlbprdec 3345// base address: 0x634b0 3346#define regL2TLB_PERFCOUNTER_LO 0x0d2c 3347#define regL2TLB_PERFCOUNTER_LO_BASE_IDX 0 3348#define regL2TLB_PERFCOUNTER_HI 0x0d2d 3349#define regL2TLB_PERFCOUNTER_HI_BASE_IDX 0 3350 3351// addressBlock: aid_mmhub_mm_cane_mmcanedec 3352// base address: 0x635f0 3353#define regMM_CANE_ICG_CTRL 0x0d8a 3354#define regMM_CANE_ICG_CTRL_BASE_IDX 0 3355#define regMM_CANE_ERR_STATUS 0x0d8c 3356#define regMM_CANE_ERR_STATUS_BASE_IDX 0 3357#define regMM_CANE_UE_ERR_STATUS_LO 0x0d8d 3358#define regMM_CANE_UE_ERR_STATUS_LO_BASE_IDX 0 3359#define regMM_CANE_UE_ERR_STATUS_HI 0x0d8e 3360#define regMM_CANE_UE_ERR_STATUS_HI_BASE_IDX 0 3361#define regMM_CANE_CE_ERR_STATUS_LO 0x0d8f 3362#define regMM_CANE_CE_ERR_STATUS_LO_BASE_IDX 0 3363#define regMM_CANE_CE_ERR_STATUS_HI 0x0d90 3364#define regMM_CANE_CE_ERR_STATUS_HI_BASE_IDX 0 3365 3366#endif 3367