1/* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _dpcs_2_0_0_OFFSET_HEADER 22#define _dpcs_2_0_0_OFFSET_HEADER 23 24 25 26// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec 27// base address: 0x0 28#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928 29#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 30#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929 31#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2 32#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a 33#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2 34#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b 35#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 36#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c 37#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 38#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d 39#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 40#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e 41#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 42 43 44// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec 45// base address: 0x0 46#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930 47#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 48#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 49#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 50#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 51#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 52#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933 53#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 54#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 55#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 56#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 57#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 58#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936 59#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 60#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL 0x2937 61#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2 62#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL2 0x2938 63#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2 64#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2939 65#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2 66#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c 67#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 68#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d 69#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 70#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 71#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 72#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 73#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 74#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 75#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 76#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 77#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 78#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 79#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 80#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 81#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 82#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 83#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 84#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 85#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 86#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 87#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 88#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 89#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 90#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a 91#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 92#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b 93#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 94#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c 95#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 96#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d 97#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 98#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e 99#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 100#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f 101#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2 102#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950 103#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2 104#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951 105#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2 106#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952 107#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2 108#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953 109#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 110#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954 111#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 112#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955 113#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 114#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956 115#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 116 117 118// addressBlock: dpcssys_dpcssys_cr0_dispdec 119// base address: 0x0 120#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934 121#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2 122#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935 123#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2 124 125 126// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec 127// base address: 0x360 128#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00 129#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 130#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01 131#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2 132#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02 133#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2 134#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03 135#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 136#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04 137#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 138#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05 139#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 140#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x2a06 141#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 142 143 144// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec 145// base address: 0x360 146#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08 147#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 148#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 149#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 150#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a 151#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 152#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b 153#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 154#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c 155#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 156#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d 157#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 158#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e 159#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 160#define mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL 0x2a0f 161#define mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2 162#define mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL2 0x2a10 163#define mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2 164#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a11 165#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2 166#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14 167#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 168#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15 169#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 170#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 171#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 172#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 173#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 174#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a 175#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 176#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b 177#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 178#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c 179#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 180#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d 181#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 182#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e 183#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 184#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f 185#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 186#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 187#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 188#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 189#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 190#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 191#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 192#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 193#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 194#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 195#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 196#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 197#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 198#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 199#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 200#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27 201#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2 202#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28 203#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2 204#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29 205#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2 206#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a 207#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2 208#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b 209#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 210#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c 211#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 212#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d 213#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 214#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e 215#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 216 217 218// addressBlock: dpcssys_dpcssys_cr1_dispdec 219// base address: 0x360 220#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c 221#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2 222#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d 223#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2 224 225 226// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec 227// base address: 0x6c0 228#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x2ad8 229#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 230#define mmDPCSTX2_DPCSTX_TX_CNTL 0x2ad9 231#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX 2 232#define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x2ada 233#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX 2 234#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL 0x2adb 235#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 236#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x2adc 237#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 238#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x2add 239#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 240#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x2ade 241#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 242 243 244// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec 245// base address: 0x6c0 246#define mmRDPCSTX2_RDPCSTX_CNTL 0x2ae0 247#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2 248#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1 249#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 250#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2 251#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 252#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA 0x2ae3 253#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 254#define mmRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4 255#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2 256#define mmRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5 257#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2 258#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6 259#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 260#define mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL 0x2ae7 261#define mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2 262#define mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL2 0x2ae8 263#define mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2 264#define mmRDPCSTX2_RDPCSTX_SCRATCH 0x2ae9 265#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2 266#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec 267#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 268#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed 269#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 270#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0 271#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2 272#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1 273#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2 274#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2 275#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2 276#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3 277#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2 278#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4 279#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2 280#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5 281#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2 282#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6 283#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2 284#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7 285#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2 286#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8 287#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2 288#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9 289#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2 290#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa 291#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2 292#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb 293#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2 294#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc 295#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2 296#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd 297#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2 298#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe 299#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2 300#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff 301#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2 302#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00 303#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2 304#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01 305#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2 306#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02 307#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2 308#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03 309#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 310#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04 311#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 312#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05 313#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 314#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06 315#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 316 317 318// addressBlock: dpcssys_dpcssys_cr2_dispdec 319// base address: 0x6c0 320#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4 321#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2 322#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5 323#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2 324 325 326// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec 327// base address: 0xa20 328#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x2bb0 329#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 330#define mmDPCSTX3_DPCSTX_TX_CNTL 0x2bb1 331#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX 2 332#define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x2bb2 333#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX 2 334#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL 0x2bb3 335#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 336#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x2bb4 337#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 338#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x2bb5 339#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 340#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x2bb6 341#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 342 343 344// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec 345// base address: 0xa20 346#define mmRDPCSTX3_RDPCSTX_CNTL 0x2bb8 347#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2 348#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9 349#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 350#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba 351#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 352#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA 0x2bbb 353#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 354#define mmRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc 355#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2 356#define mmRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd 357#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2 358#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe 359#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 360#define mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL 0x2bbf 361#define mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2 362#define mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL2 0x2bc0 363#define mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2 364#define mmRDPCSTX3_RDPCSTX_SCRATCH 0x2bc1 365#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2 366#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4 367#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 368#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5 369#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 370#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8 371#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2 372#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9 373#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2 374#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca 375#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2 376#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb 377#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2 378#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc 379#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2 380#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd 381#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2 382#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce 383#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2 384#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf 385#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2 386#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0 387#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2 388#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1 389#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2 390#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2 391#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2 392#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3 393#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2 394#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4 395#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2 396#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5 397#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2 398#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6 399#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2 400#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7 401#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2 402#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8 403#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2 404#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9 405#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2 406#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda 407#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2 408#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb 409#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 410#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc 411#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 412#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd 413#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 414#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde 415#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 416 417 418// addressBlock: dpcssys_dpcssys_cr3_dispdec 419// base address: 0xa20 420#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc 421#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2 422#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd 423#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2 424 425 426// addressBlock: dpcssys_dpcs0_dpcsrx_dispdec 427// base address: 0x0 428#define mmDPCSRX_PHY_CNTL 0x2c76 429#define mmDPCSRX_PHY_CNTL_BASE_IDX 2 430#define mmDPCSRX_RX_CLOCK_CNTL 0x2c78 431#define mmDPCSRX_RX_CLOCK_CNTL_BASE_IDX 2 432#define mmDPCSRX_RX_CNTL 0x2c7a 433#define mmDPCSRX_RX_CNTL_BASE_IDX 2 434#define mmDPCSRX_CBUS_CNTL 0x2c7b 435#define mmDPCSRX_CBUS_CNTL_BASE_IDX 2 436#define mmDPCSRX_REG_ERROR_STATUS 0x2c7c 437#define mmDPCSRX_REG_ERROR_STATUS_BASE_IDX 2 438#define mmDPCSRX_RX_ERROR_STATUS 0x2c7d 439#define mmDPCSRX_RX_ERROR_STATUS_BASE_IDX 2 440#define mmDPCSRX_INDEX_MODE_ADDR 0x2c80 441#define mmDPCSRX_INDEX_MODE_ADDR_BASE_IDX 2 442#define mmDPCSRX_INDEX_MODE_DATA 0x2c81 443#define mmDPCSRX_INDEX_MODE_DATA_BASE_IDX 2 444#define mmDPCSRX_DEBUG_CONFIG 0x2c82 445#define mmDPCSRX_DEBUG_CONFIG_BASE_IDX 2 446 447 448// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec 449// base address: 0xd80 450#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x2c88 451#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 452#define mmDPCSTX4_DPCSTX_TX_CNTL 0x2c89 453#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX 2 454#define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x2c8a 455#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX 2 456#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL 0x2c8b 457#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 458#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x2c8c 459#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 460#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x2c8d 461#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 462#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x2c8e 463#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 464 465 466// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec 467// base address: 0xd80 468#define mmRDPCSTX4_RDPCSTX_CNTL 0x2c90 469#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2 470#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91 471#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 472#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92 473#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 474#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA 0x2c93 475#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 476#define mmRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94 477#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2 478#define mmRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95 479#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2 480#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96 481#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 482#define mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL 0x2c97 483#define mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2 484#define mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL2 0x2c98 485#define mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2 486#define mmRDPCSTX4_RDPCSTX_SCRATCH 0x2c99 487#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2 488#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c 489#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 490#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d 491#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 492#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0 493#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2 494#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1 495#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2 496#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2 497#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2 498#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3 499#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2 500#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4 501#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2 502#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5 503#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2 504#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6 505#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2 506#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7 507#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2 508#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8 509#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2 510#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9 511#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2 512#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa 513#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2 514#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab 515#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2 516#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac 517#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2 518#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad 519#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2 520#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae 521#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2 522#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf 523#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2 524#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0 525#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2 526#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1 527#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2 528#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2 529#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2 530#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3 531#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 532#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4 533#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 534#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5 535#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 536#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6 537#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 538 539 540// addressBlock: dpcssys_dpcssys_cr4_dispdec 541// base address: 0xd80 542#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94 543#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2 544#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95 545#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2 546 547 548// addressBlock: dpcssys_dpcs0_dpcstx5_dispdec 549// base address: 0x10e0 550#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL 0x2d60 551#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 552#define mmDPCSTX5_DPCSTX_TX_CNTL 0x2d61 553#define mmDPCSTX5_DPCSTX_TX_CNTL_BASE_IDX 2 554#define mmDPCSTX5_DPCSTX_CBUS_CNTL 0x2d62 555#define mmDPCSTX5_DPCSTX_CBUS_CNTL_BASE_IDX 2 556#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL 0x2d63 557#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 558#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR 0x2d64 559#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 560#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA 0x2d65 561#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 562#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG 0x2d66 563#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 564 565 566// addressBlock: dpcssys_dpcs0_rdpcstx5_dispdec 567// base address: 0x10e0 568#define mmRDPCSTX5_RDPCSTX_CNTL 0x2d68 569#define mmRDPCSTX5_RDPCSTX_CNTL_BASE_IDX 2 570#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL 0x2d69 571#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 572#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL 0x2d6a 573#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 574#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA 0x2d6b 575#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 576#define mmRDPCSTX5_RDPCS_TX_CR_ADDR 0x2d6c 577#define mmRDPCSTX5_RDPCS_TX_CR_ADDR_BASE_IDX 2 578#define mmRDPCSTX5_RDPCS_TX_CR_DATA 0x2d6d 579#define mmRDPCSTX5_RDPCS_TX_CR_DATA_BASE_IDX 2 580#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL 0x2d6e 581#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 582#define mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL 0x2d6f 583#define mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2 584#define mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL2 0x2d70 585#define mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2 586#define mmRDPCSTX5_RDPCSTX_SCRATCH 0x2d71 587#define mmRDPCSTX5_RDPCSTX_SCRATCH_BASE_IDX 2 588#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2d74 589#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 590#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG 0x2d75 591#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 592#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0 0x2d78 593#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0_BASE_IDX 2 594#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1 0x2d79 595#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1_BASE_IDX 2 596#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2 0x2d7a 597#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2_BASE_IDX 2 598#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3 0x2d7b 599#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3_BASE_IDX 2 600#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4 0x2d7c 601#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4_BASE_IDX 2 602#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5 0x2d7d 603#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5_BASE_IDX 2 604#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6 0x2d7e 605#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6_BASE_IDX 2 606#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7 0x2d7f 607#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7_BASE_IDX 2 608#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8 0x2d80 609#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8_BASE_IDX 2 610#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9 0x2d81 611#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9_BASE_IDX 2 612#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10 0x2d82 613#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10_BASE_IDX 2 614#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11 0x2d83 615#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11_BASE_IDX 2 616#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12 0x2d84 617#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12_BASE_IDX 2 618#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13 0x2d85 619#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13_BASE_IDX 2 620#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14 0x2d86 621#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14_BASE_IDX 2 622#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0 0x2d87 623#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0_BASE_IDX 2 624#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1 0x2d88 625#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1_BASE_IDX 2 626#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2 0x2d89 627#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2_BASE_IDX 2 628#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3 0x2d8a 629#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3_BASE_IDX 2 630#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL 0x2d8b 631#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 632#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2d8c 633#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 634#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2d8d 635#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 636#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG 0x2d8e 637#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 638 639 640// addressBlock: dpcssys_dpcssys_cr5_dispdec 641// base address: 0x10e0 642#define mmDPCSSYS_CR5_DPCSSYS_CR_ADDR 0x2d6c 643#define mmDPCSSYS_CR5_DPCSSYS_CR_ADDR_BASE_IDX 2 644#define mmDPCSSYS_CR5_DPCSSYS_CR_DATA 0x2d6d 645#define mmDPCSSYS_CR5_DPCSSYS_CR_DATA_BASE_IDX 2 646 647#endif 648