183828Sdfr/* 283828Sdfr * Copyright 2012-15 Advanced Micro Devices, Inc. 3164010Smarcel * 483828Sdfr * Permission is hereby granted, free of charge, to any person obtaining a 583828Sdfr * copy of this software and associated documentation files (the "Software"), 683828Sdfr * to deal in the Software without restriction, including without limitation 783828Sdfr * the rights to use, copy, modify, merge, publish, distribute, sublicense, 883828Sdfr * and/or sell copies of the Software, and to permit persons to whom the 983828Sdfr * Software is furnished to do so, subject to the following conditions: 1083828Sdfr * 1183828Sdfr * The above copyright notice and this permission notice shall be included in 1283828Sdfr * all copies or substantial portions of the Software. 1383828Sdfr * 1483828Sdfr * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1583828Sdfr * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1683828Sdfr * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1783828Sdfr * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1883828Sdfr * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1983828Sdfr * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2083828Sdfr * OTHER DEALINGS IN THE SOFTWARE. 2183828Sdfr * 2283828Sdfr * Authors: AMD 2383828Sdfr * 2483828Sdfr */ 2583828Sdfr 2683828Sdfr#ifndef __DC_LINK_ENCODER__DCN31_H__ 2783828Sdfr#define __DC_LINK_ENCODER__DCN31_H__ 28124140Sobrien 29124140Sobrien#include "dcn30/dcn30_dio_link_encoder.h" 30124140Sobrien 3183828Sdfr 3283828Sdfr#define LE_DCN31_REG_LIST(id)\ 3383828Sdfr LE_DCN3_REG_LIST(id),\ 3483828Sdfr SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 3583828Sdfr SR(DIO_LINKA_CNTL), \ 3683828Sdfr SR(DIO_LINKB_CNTL), \ 3783828Sdfr SR(DIO_LINKC_CNTL), \ 3883828Sdfr SR(DIO_LINKD_CNTL), \ 3983828Sdfr SR(DIO_LINKE_CNTL), \ 40164010Smarcel SR(DIO_LINKF_CNTL) 4183828Sdfr 4283828Sdfr#define LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh) \ 4383828Sdfr LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\ 4483828Sdfr LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ 4583828Sdfr LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ 4683828Sdfr LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ 4783828Sdfr LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ 48164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ 49164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ 5083828Sdfr LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ 51164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ 52164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ 53164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ 54164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ 55164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ 56164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ 57164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ 58164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\ 59164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\ 60164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ 61164010Smarcel LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\ 62164010Smarcel LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\ 6383828Sdfr LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\ 6483828Sdfr LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh) 65164010Smarcel 66164010Smarcel#define DPCS_DCN31_REG_LIST(id) \ 67164010Smarcel SRI(TMDS_CTL_BITS, DIG, id), \ 68164010Smarcel SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \ 69164010Smarcel SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \ 7083828Sdfr SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \ 7183828Sdfr SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \ 7283828Sdfr SRI(RDPCSPIPE_PHY_CNTL6, RDPCSPIPE, id), \ 7383828Sdfr SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \ 74164010Smarcel SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \ 75164010Smarcel SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \ 76164010Smarcel SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \ 77164010Smarcel SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \ 78164010Smarcel SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \ 79164010Smarcel SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \ 80164010Smarcel SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \ 81164010Smarcel SRI(RDPCSTX_CNTL, RDPCSTX, id), \ 82164010Smarcel SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \ 83164010Smarcel SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \ 84164010Smarcel SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \ 85164010Smarcel SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \ 86164010Smarcel SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \ 87164010Smarcel SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \ 88164010Smarcel SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \ 89164010Smarcel SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \ 90164010Smarcel SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \ 91164010Smarcel SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \ 92164010Smarcel SR(RDPCSTX0_RDPCSTX_SCRATCH), \ 93164010Smarcel SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\ 94164010Smarcel SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id) 95164010Smarcel 96164010Smarcel#define DPCS_DCN31_MASK_SH_LIST(mask_sh)\ 9783828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\ 98164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\ 9983828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\ 100164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\ 101164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\ 10283828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\ 10383828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\ 10483828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\ 10583828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\ 10683828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\ 10783828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\ 10883828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\ 10983828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\ 110164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\ 11183828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\ 112164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\ 113164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\ 114164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\ 115164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\ 116164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\ 117164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\ 118164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\ 119164010Smarcel LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\ 120164010Smarcel LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\ 121164010Smarcel LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\ 122164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\ 123164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\ 124164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\ 125164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\ 126164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\ 127164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\ 128164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\ 129164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\ 130164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\ 131164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\ 132164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\ 133164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\ 134164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\ 135164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\ 13683828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\ 137164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\ 138164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\ 139164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\ 140164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\ 14183828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\ 14283828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\ 14383828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\ 14483828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\ 14583828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\ 14683828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\ 14783828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\ 14883828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\ 14983828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\ 15083828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\ 15183828Sdfr LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\ 15283828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\ 15383828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\ 15483828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\ 15583828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\ 15683828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\ 15783828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\ 15883828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\ 15983828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\ 16083828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\ 161164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\ 16283828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\ 16383828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\ 16483828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\ 16583828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\ 16683828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\ 16783828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\ 168164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\ 16983828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\ 17083828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\ 17183828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\ 17283828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\ 17383828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\ 17483828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\ 17583828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\ 17683828Sdfr LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\ 17783828Sdfr LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\ 17883828Sdfr LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\ 179164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\ 18083828Sdfr LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\ 18183828Sdfr LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\ 18283828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\ 18383828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\ 18483828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\ 18583828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\ 18683828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\ 18783828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\ 18883828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\ 189164010Smarcel LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\ 19083828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\ 19183828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\ 19283828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\ 19383828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\ 19483828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\ 19583828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\ 19683828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\ 19783828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\ 19883828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\ 19983828Sdfr LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh) 20083828Sdfr 201164010Smarcel#define DPCS_DCN314_REG_LIST(id) \ 202164010Smarcel SRI(TMDS_CTL_BITS, DIG, id), \ 20383828Sdfr SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \ 204164010Smarcel SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \ 205164010Smarcel SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \ 206164010Smarcel SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \ 207164010Smarcel SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \ 208164010Smarcel SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \ 209164010Smarcel SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \ 210164010Smarcel SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \ 211164010Smarcel SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \ 212164010Smarcel SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \ 213164010Smarcel SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \ 214164010Smarcel SRI(RDPCSTX_CNTL, RDPCSTX, id), \ 215164010Smarcel SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \ 216164010Smarcel SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \ 217164010Smarcel SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \ 218164010Smarcel SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \ 219164010Smarcel SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \ 22083828Sdfr SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \ 22183828Sdfr SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \ 22283828Sdfr SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \ 223158467Sjhb SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \ 22483828Sdfr SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \ 22583828Sdfr SR(RDPCSTX0_RDPCSTX_SCRATCH), \ 22683828Sdfr SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\ 22783828Sdfr SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id) 22883828Sdfr 229219691Smarcelvoid dcn31_link_encoder_construct( 23083828Sdfr struct dcn20_link_encoder *enc20, 231164010Smarcel const struct encoder_init_data *init_data, 232164010Smarcel const struct encoder_feature_support *enc_features, 233164010Smarcel const struct dcn10_link_enc_registers *link_regs, 234164010Smarcel const struct dcn10_link_enc_aux_registers *aux_regs, 235164010Smarcel const struct dcn10_link_enc_hpd_registers *hpd_regs, 236164010Smarcel const struct dcn10_link_enc_shift *link_shift, 237219691Smarcel const struct dcn10_link_enc_mask *link_mask); 23883828Sdfr 239219691Smarcel/* 240164010Smarcel * Create a minimal link encoder object with no dc_link object associated with it. 241164010Smarcel */ 242164010Smarcelvoid dcn31_link_encoder_construct_minimal( 243164010Smarcel struct dcn20_link_encoder *enc20, 24483828Sdfr struct dc_context *ctx, 245164010Smarcel const struct encoder_feature_support *enc_features, 246164010Smarcel const struct dcn10_link_enc_registers *link_regs, 247164010Smarcel enum engine_id eng_id); 248164010Smarcel 249164010Smarcelvoid dcn31_link_encoder_set_dio_phy_mux( 250164010Smarcel struct link_encoder *enc, 251164010Smarcel enum encoder_type_select sel, 252164010Smarcel uint32_t hpo_inst); 253164010Smarcel 254164010Smarcel/* 255164010Smarcel * Enable DP transmitter and its encoder. 256164010Smarcel */ 25783828Sdfrvoid dcn31_link_encoder_enable_dp_output( 258164010Smarcel struct link_encoder *enc, 259164010Smarcel const struct dc_link_settings *link_settings, 260164010Smarcel enum clock_source_id clock_source); 261164010Smarcel 262164010Smarcel/* 263164010Smarcel * Enable DP transmitter and its encoder in MST mode. 264164010Smarcel */ 265164010Smarcelvoid dcn31_link_encoder_enable_dp_mst_output( 26683828Sdfr struct link_encoder *enc, 267164010Smarcel const struct dc_link_settings *link_settings, 268164010Smarcel enum clock_source_id clock_source); 269164010Smarcel 270164010Smarcel/* 271164010Smarcel * Disable transmitter and its encoder. 272164010Smarcel */ 27383828Sdfrvoid dcn31_link_encoder_disable_output( 274164010Smarcel struct link_encoder *enc, 27583828Sdfr enum signal_type signal); 276164010Smarcel 277164010Smarcel/* 278164010Smarcel * Check whether USB-C DP Alt mode is disabled 279164010Smarcel */ 280164010Smarcelbool dcn31_link_encoder_is_in_alt_mode( 281164010Smarcel struct link_encoder *enc); 282164010Smarcel 28383828Sdfrvoid dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc, 284164010Smarcel struct dc_link_settings *link_settings); 28583828Sdfr 286164010Smarcel#endif /* __DC_LINK_ENCODER__DCN31_H__ */ 287164010Smarcel