1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#ifndef DC_DDC_TYPES_H_
26#define DC_DDC_TYPES_H_
27
28enum aux_transaction_type {
29	AUX_TRANSACTION_TYPE_DP,
30	AUX_TRANSACTION_TYPE_I2C
31};
32
33
34enum i2caux_transaction_action {
35	I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00,
36	I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10,
37	I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20,
38
39	I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40,
40	I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT = 0x50,
41	I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60,
42
43	I2CAUX_TRANSACTION_ACTION_DP_WRITE = 0x80,
44	I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90
45};
46
47struct aux_request_transaction_data {
48	enum aux_transaction_type type;
49	enum i2caux_transaction_action action;
50	/* 20-bit AUX channel transaction address */
51	uint32_t address;
52	/* delay, in 100-microsecond units */
53	uint8_t delay;
54	uint32_t length;
55	uint8_t *data;
56};
57
58enum aux_transaction_reply {
59	AUX_TRANSACTION_REPLY_AUX_ACK = 0x00,
60	AUX_TRANSACTION_REPLY_AUX_NACK = 0x01,
61	AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02,
62	AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK = 0x04,
63	AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER = 0x08,
64
65	AUX_TRANSACTION_REPLY_I2C_ACK = 0x00,
66	AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
67	AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20,
68
69	AUX_TRANSACTION_REPLY_HPD_DISCON = 0x40,
70
71	AUX_TRANSACTION_REPLY_INVALID = 0xFF
72};
73
74struct aux_reply_transaction_data {
75	enum aux_transaction_reply status;
76	uint32_t length;
77	uint8_t *data;
78};
79
80struct aux_payload {
81	/* set following flag to read/write I2C data,
82	 * reset it to read/write DPCD data */
83	bool i2c_over_aux;
84	/* set following flag to write data,
85	 * reset it to read data */
86	bool write;
87	bool mot;
88	bool write_status_update;
89
90	uint32_t address;
91	uint32_t length;
92	uint8_t *data;
93	/*
94	 * used to return the reply type of the transaction
95	 * ignored if NULL
96	 */
97	uint8_t *reply;
98	/* expressed in milliseconds
99	 * zero means "use default value"
100	 */
101	uint32_t defer_delay;
102
103};
104#define DEFAULT_AUX_MAX_DATA_SIZE 16
105
106struct i2c_payload {
107	bool write;
108	uint8_t address;
109	uint32_t length;
110	uint8_t *data;
111};
112
113enum i2c_command_engine {
114	I2C_COMMAND_ENGINE_DEFAULT,
115	I2C_COMMAND_ENGINE_SW,
116	I2C_COMMAND_ENGINE_HW
117};
118
119#define DDC_I2C_COMMAND_ENGINE I2C_COMMAND_ENGINE_SW
120
121struct i2c_command {
122	struct i2c_payload *payloads;
123	uint8_t number_of_payloads;
124
125	enum i2c_command_engine engine;
126
127	/* expressed in KHz
128	 * zero means "use default value" */
129	uint32_t speed;
130};
131
132struct gpio_ddc_hw_info {
133	bool hw_supported;
134	uint32_t ddc_channel;
135};
136
137struct ddc {
138	struct gpio *pin_data;
139	struct gpio *pin_clock;
140	struct gpio_ddc_hw_info hw_info;
141	struct dc_context *ctx;
142};
143
144union ddc_wa {
145	struct {
146		uint32_t DP_SKIP_POWER_OFF:1;
147		uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
148	} bits;
149	uint32_t raw;
150};
151
152struct ddc_flags {
153	uint8_t EDID_QUERY_DONE_ONCE:1;
154	uint8_t IS_INTERNAL_DISPLAY:1;
155	uint8_t FORCE_READ_REPEATED_START:1;
156	uint8_t EDID_STRESS_READ:1;
157
158};
159
160enum ddc_transaction_type {
161	DDC_TRANSACTION_TYPE_NONE = 0,
162	DDC_TRANSACTION_TYPE_I2C,
163	DDC_TRANSACTION_TYPE_I2C_OVER_AUX,
164	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER,
165	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER
166};
167
168enum display_dongle_type {
169	DISPLAY_DONGLE_NONE = 0,
170	/* Active converter types*/
171	DISPLAY_DONGLE_DP_VGA_CONVERTER,
172	DISPLAY_DONGLE_DP_DVI_CONVERTER,
173	DISPLAY_DONGLE_DP_HDMI_CONVERTER,
174	/* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/
175	DISPLAY_DONGLE_DP_DVI_DONGLE,
176	DISPLAY_DONGLE_DP_HDMI_DONGLE,
177	/* Other types of dongle*/
178	DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE,
179};
180
181#define DC_MAX_EDID_BUFFER_SIZE 2048
182#define DC_EDID_BLOCK_SIZE 128
183
184struct ddc_service {
185	struct ddc *ddc_pin;
186	struct ddc_flags flags;
187	union ddc_wa wa;
188	enum ddc_transaction_type transaction_type;
189	enum display_dongle_type dongle_type;
190	struct dc_context *ctx;
191	struct dc_link *link;
192
193	uint32_t address;
194	uint32_t edid_buf_len;
195	uint8_t edid_buf[DC_MAX_EDID_BUFFER_SIZE];
196};
197
198#endif /* DC_DDC_TYPES_H_ */
199