1243789Sdim/* 2243789Sdim * Copyright 2016 Advanced Micro Devices, Inc. 3243789Sdim * 4243789Sdim * Permission is hereby granted, free of charge, to any person obtaining a 5243789Sdim * copy of this software and associated documentation files (the "Software"), 6243789Sdim * to deal in the Software without restriction, including without limitation 7243789Sdim * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8243789Sdim * and/or sell copies of the Software, and to permit persons to whom the 9243789Sdim * Software is furnished to do so, subject to the following conditions: 10243789Sdim * 11243789Sdim * The above copyright notice and this permission notice shall be included in 12243789Sdim * all copies or substantial portions of the Software. 13243789Sdim * 14243789Sdim * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15243789Sdim * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16243789Sdim * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17243789Sdim * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18243789Sdim * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19252723Sdim * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20243789Sdim * OTHER DEALINGS IN THE SOFTWARE. 21252723Sdim * 22252723Sdim */ 23252723Sdim#include "amdgpu.h" 24243789Sdim#include "athub_v1_0.h" 25243789Sdim 26243789Sdim#include "athub/athub_1_0_offset.h" 27243789Sdim#include "athub/athub_1_0_sh_mask.h" 28243789Sdim#include "vega10_enum.h" 29243789Sdim 30243789Sdim#include "soc15_common.h" 31243789Sdim 32243789Sdimstatic void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, 33243789Sdim bool enable) 34243789Sdim{ 35243789Sdim uint32_t def, data; 36243789Sdim 37243789Sdim def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 38243789Sdim 39243789Sdim if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 40243789Sdim data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; 41243789Sdim else 42243789Sdim data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; 43243789Sdim 44243789Sdim if (def != data) 45243789Sdim WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 46243789Sdim} 47243789Sdim 48243789Sdimstatic void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, 49243789Sdim bool enable) 50243789Sdim{ 51243789Sdim uint32_t def, data; 52243789Sdim 53243789Sdim def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 54243789Sdim 55243789Sdim if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && 56243789Sdim (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 57243789Sdim data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 58243789Sdim else 59243789Sdim data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 60243789Sdim 61243789Sdim if(def != data) 62243789Sdim WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 63243789Sdim} 64243789Sdim 65243789Sdimint athub_v1_0_set_clockgating(struct amdgpu_device *adev, 66243789Sdim enum amd_clockgating_state state) 67243789Sdim{ 68243789Sdim if (amdgpu_sriov_vf(adev)) 69243789Sdim return 0; 70243789Sdim 71243789Sdim switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { 72243789Sdim case IP_VERSION(9, 0, 0): 73243789Sdim case IP_VERSION(9, 1, 0): 74243789Sdim case IP_VERSION(9, 2, 0): 75243789Sdim case IP_VERSION(9, 3, 0): 76243789Sdim case IP_VERSION(9, 4, 0): 77243789Sdim case IP_VERSION(1, 5, 0): 78243789Sdim athub_update_medium_grain_clock_gating(adev, 79243789Sdim state == AMD_CG_STATE_GATE); 80243789Sdim athub_update_medium_grain_light_sleep(adev, 81243789Sdim state == AMD_CG_STATE_GATE); 82243789Sdim break; 83243789Sdim default: 84243789Sdim break; 85243789Sdim } 86243789Sdim 87243789Sdim return 0; 88243789Sdim} 89243789Sdim 90243789Sdimvoid athub_v1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 91243789Sdim{ 92243789Sdim int data; 93243789Sdim 94243789Sdim if (amdgpu_sriov_vf(adev)) 95243789Sdim *flags = 0; 96243789Sdim 97243789Sdim /* AMD_CG_SUPPORT_ATHUB_MGCG */ 98243789Sdim data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 99243789Sdim if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) 100243789Sdim *flags |= AMD_CG_SUPPORT_ATHUB_MGCG; 101243789Sdim 102243789Sdim /* AMD_CG_SUPPORT_ATHUB_LS */ 103243789Sdim if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK) 104243789Sdim *flags |= AMD_CG_SUPPORT_ATHUB_LS; 105243789Sdim} 106243789Sdim