1// SPDX-License-Identifier: GPL-2.0+ 2 3#include <drm/drm_atomic_helper.h> 4#include <drm/drm_edid.h> 5#include <drm/drm_simple_kms_helper.h> 6#include <drm/drm_vblank.h> 7 8#include "amdgpu.h" 9#ifdef CONFIG_DRM_AMDGPU_SI 10#include "dce_v6_0.h" 11#endif 12#ifdef CONFIG_DRM_AMDGPU_CIK 13#include "dce_v8_0.h" 14#endif 15#include "dce_v10_0.h" 16#include "dce_v11_0.h" 17#include "ivsrcid/ivsrcid_vislands30.h" 18#include "amdgpu_vkms.h" 19#include "amdgpu_display.h" 20#include "atom.h" 21#include "amdgpu_irq.h" 22 23/** 24 * DOC: amdgpu_vkms 25 * 26 * The amdgpu vkms interface provides a virtual KMS interface for several use 27 * cases: devices without display hardware, platforms where the actual display 28 * hardware is not useful (e.g., servers), SR-IOV virtual functions, device 29 * emulation/simulation, and device bring up prior to display hardware being 30 * usable. We previously emulated a legacy KMS interface, but there was a desire 31 * to move to the atomic KMS interface. The vkms driver did everything we 32 * needed, but we wanted KMS support natively in the driver without buffer 33 * sharing and the ability to support an instance of VKMS per device. We first 34 * looked at splitting vkms into a stub driver and a helper module that other 35 * drivers could use to implement a virtual display, but this strategy ended up 36 * being messy due to driver specific callbacks needed for buffer management. 37 * Ultimately, it proved easier to import the vkms code as it mostly used core 38 * drm helpers anyway. 39 */ 40 41static const u32 amdgpu_vkms_formats[] = { 42 DRM_FORMAT_XRGB8888, 43}; 44 45static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) 46{ 47 struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); 48 struct drm_crtc *crtc = &amdgpu_crtc->base; 49 struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); 50 u64 ret_overrun; 51 bool ret; 52 53 ret_overrun = hrtimer_forward_now(&amdgpu_crtc->vblank_timer, 54 output->period_ns); 55 if (ret_overrun != 1) 56 DRM_WARN("%s: vblank timer overrun\n", __func__); 57 58 ret = drm_crtc_handle_vblank(crtc); 59 /* Don't queue timer again when vblank is disabled. */ 60 if (!ret) 61 return HRTIMER_NORESTART; 62 63 return HRTIMER_RESTART; 64} 65 66static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc) 67{ 68 struct drm_device *dev = crtc->dev; 69 unsigned int pipe = drm_crtc_index(crtc); 70 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; 71 struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc); 72 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 73 74 drm_calc_timestamping_constants(crtc, &crtc->mode); 75 76 out->period_ns = ktime_set(0, vblank->framedur_ns); 77 hrtimer_start(&amdgpu_crtc->vblank_timer, out->period_ns, HRTIMER_MODE_REL); 78 79 return 0; 80} 81 82static void amdgpu_vkms_disable_vblank(struct drm_crtc *crtc) 83{ 84 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 85 86 hrtimer_try_to_cancel(&amdgpu_crtc->vblank_timer); 87} 88 89static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, 90 int *max_error, 91 ktime_t *vblank_time, 92 bool in_vblank_irq) 93{ 94 struct drm_device *dev = crtc->dev; 95 unsigned int pipe = crtc->index; 96 struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); 97 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; 98 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 99 100 if (!READ_ONCE(vblank->enabled)) { 101 *vblank_time = ktime_get(); 102 return true; 103 } 104 105 *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); 106 107 if (WARN_ON(*vblank_time == vblank->time)) 108 return true; 109 110 /* 111 * To prevent races we roll the hrtimer forward before we do any 112 * interrupt processing - this is how real hw works (the interrupt is 113 * only generated after all the vblank registers are updated) and what 114 * the vblank core expects. Therefore we need to always correct the 115 * timestampe by one frame. 116 */ 117 *vblank_time -= output->period_ns; 118 119 return true; 120} 121 122static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { 123 .set_config = drm_atomic_helper_set_config, 124 .destroy = drm_crtc_cleanup, 125 .page_flip = drm_atomic_helper_page_flip, 126 .reset = drm_atomic_helper_crtc_reset, 127 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 128 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 129 .enable_vblank = amdgpu_vkms_enable_vblank, 130 .disable_vblank = amdgpu_vkms_disable_vblank, 131 .get_vblank_timestamp = amdgpu_vkms_get_vblank_timestamp, 132}; 133 134static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, 135 struct drm_atomic_state *state) 136{ 137 drm_crtc_vblank_on(crtc); 138} 139 140static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc, 141 struct drm_atomic_state *state) 142{ 143 drm_crtc_vblank_off(crtc); 144} 145 146static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, 147 struct drm_atomic_state *state) 148{ 149 unsigned long flags; 150 if (crtc->state->event) { 151 spin_lock_irqsave(&crtc->dev->event_lock, flags); 152 153 if (drm_crtc_vblank_get(crtc) != 0) 154 drm_crtc_send_vblank_event(crtc, crtc->state->event); 155 else 156 drm_crtc_arm_vblank_event(crtc, crtc->state->event); 157 158 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 159 160 crtc->state->event = NULL; 161 } 162} 163 164static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { 165 .atomic_flush = amdgpu_vkms_crtc_atomic_flush, 166 .atomic_enable = amdgpu_vkms_crtc_atomic_enable, 167 .atomic_disable = amdgpu_vkms_crtc_atomic_disable, 168}; 169 170static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, 171 struct drm_plane *primary, struct drm_plane *cursor) 172{ 173 struct amdgpu_device *adev = drm_to_adev(dev); 174 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 175 int ret; 176 177 ret = drm_crtc_init_with_planes(dev, crtc, primary, cursor, 178 &amdgpu_vkms_crtc_funcs, NULL); 179 if (ret) { 180 DRM_ERROR("Failed to init CRTC\n"); 181 return ret; 182 } 183 184 drm_crtc_helper_add(crtc, &amdgpu_vkms_crtc_helper_funcs); 185 186 amdgpu_crtc->crtc_id = drm_crtc_index(crtc); 187 adev->mode_info.crtcs[drm_crtc_index(crtc)] = amdgpu_crtc; 188 189 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 190 amdgpu_crtc->encoder = NULL; 191 amdgpu_crtc->connector = NULL; 192 amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; 193 194 hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 195 amdgpu_crtc->vblank_timer.function = &amdgpu_vkms_vblank_simulate; 196 197 return ret; 198} 199 200static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = { 201 .fill_modes = drm_helper_probe_single_connector_modes, 202 .destroy = drm_connector_cleanup, 203 .reset = drm_atomic_helper_connector_reset, 204 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 205 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 206}; 207 208static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector) 209{ 210 struct drm_device *dev = connector->dev; 211 struct drm_display_mode *mode = NULL; 212 unsigned i; 213 static const struct mode_size { 214 int w; 215 int h; 216 } common_modes[] = { 217 { 640, 480}, 218 { 720, 480}, 219 { 800, 600}, 220 { 848, 480}, 221 {1024, 768}, 222 {1152, 768}, 223 {1280, 720}, 224 {1280, 800}, 225 {1280, 854}, 226 {1280, 960}, 227 {1280, 1024}, 228 {1440, 900}, 229 {1400, 1050}, 230 {1680, 1050}, 231 {1600, 1200}, 232 {1920, 1080}, 233 {1920, 1200}, 234 {2560, 1440}, 235 {4096, 3112}, 236 {3656, 2664}, 237 {3840, 2160}, 238 {4096, 2160}, 239 }; 240 241 for (i = 0; i < ARRAY_SIZE(common_modes); i++) { 242 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 243 if (!mode) 244 continue; 245 drm_mode_probed_add(connector, mode); 246 } 247 248 drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF); 249 250 return ARRAY_SIZE(common_modes); 251} 252 253static const struct drm_connector_helper_funcs amdgpu_vkms_conn_helper_funcs = { 254 .get_modes = amdgpu_vkms_conn_get_modes, 255}; 256 257static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = { 258 .update_plane = drm_atomic_helper_update_plane, 259 .disable_plane = drm_atomic_helper_disable_plane, 260 .destroy = drm_plane_cleanup, 261 .reset = drm_atomic_helper_plane_reset, 262 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 263 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 264}; 265 266static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane, 267 struct drm_atomic_state *old_state) 268{ 269 return; 270} 271 272static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, 273 struct drm_atomic_state *state) 274{ 275 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 276 plane); 277 struct drm_crtc_state *crtc_state; 278 int ret; 279 280 if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc)) 281 return 0; 282 283 crtc_state = drm_atomic_get_crtc_state(state, 284 new_plane_state->crtc); 285 if (IS_ERR(crtc_state)) 286 return PTR_ERR(crtc_state); 287 288 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 289 DRM_PLANE_NO_SCALING, 290 DRM_PLANE_NO_SCALING, 291 false, true); 292 if (ret != 0) 293 return ret; 294 295 /* for now primary plane must be visible and full screen */ 296 if (!new_plane_state->visible) 297 return -EINVAL; 298 299 return 0; 300} 301 302static int amdgpu_vkms_prepare_fb(struct drm_plane *plane, 303 struct drm_plane_state *new_state) 304{ 305 struct amdgpu_framebuffer *afb; 306 struct drm_gem_object *obj; 307 struct amdgpu_device *adev; 308 struct amdgpu_bo *rbo; 309 uint32_t domain; 310 int r; 311 312 if (!new_state->fb) { 313 DRM_DEBUG_KMS("No FB bound\n"); 314 return 0; 315 } 316 afb = to_amdgpu_framebuffer(new_state->fb); 317 obj = new_state->fb->obj[0]; 318 rbo = gem_to_amdgpu_bo(obj); 319 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 320 321 r = amdgpu_bo_reserve(rbo, true); 322 if (r) { 323 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 324 return r; 325 } 326 327 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); 328 if (r) { 329 dev_err(adev->dev, "allocating fence slot failed (%d)\n", r); 330 goto error_unlock; 331 } 332 333 if (plane->type != DRM_PLANE_TYPE_CURSOR) 334 domain = amdgpu_display_supported_domains(adev, rbo->flags); 335 else 336 domain = AMDGPU_GEM_DOMAIN_VRAM; 337 338 r = amdgpu_bo_pin(rbo, domain); 339 if (unlikely(r != 0)) { 340 if (r != -ERESTARTSYS) 341 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 342 goto error_unlock; 343 } 344 345 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 346 if (unlikely(r != 0)) { 347 DRM_ERROR("%p bind failed\n", rbo); 348 goto error_unpin; 349 } 350 351 amdgpu_bo_unreserve(rbo); 352 353 afb->address = amdgpu_bo_gpu_offset(rbo); 354 355 amdgpu_bo_ref(rbo); 356 357 return 0; 358 359error_unpin: 360 amdgpu_bo_unpin(rbo); 361 362error_unlock: 363 amdgpu_bo_unreserve(rbo); 364 return r; 365} 366 367static void amdgpu_vkms_cleanup_fb(struct drm_plane *plane, 368 struct drm_plane_state *old_state) 369{ 370 struct amdgpu_bo *rbo; 371 int r; 372 373 if (!old_state->fb) 374 return; 375 376 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 377 r = amdgpu_bo_reserve(rbo, false); 378 if (unlikely(r)) { 379 DRM_ERROR("failed to reserve rbo before unpin\n"); 380 return; 381 } 382 383 amdgpu_bo_unpin(rbo); 384 amdgpu_bo_unreserve(rbo); 385 amdgpu_bo_unref(&rbo); 386} 387 388static const struct drm_plane_helper_funcs amdgpu_vkms_primary_helper_funcs = { 389 .atomic_update = amdgpu_vkms_plane_atomic_update, 390 .atomic_check = amdgpu_vkms_plane_atomic_check, 391 .prepare_fb = amdgpu_vkms_prepare_fb, 392 .cleanup_fb = amdgpu_vkms_cleanup_fb, 393}; 394 395static struct drm_plane *amdgpu_vkms_plane_init(struct drm_device *dev, 396 enum drm_plane_type type, 397 int index) 398{ 399 struct drm_plane *plane; 400 int ret; 401 402 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 403 if (!plane) 404 return ERR_PTR(-ENOMEM); 405 406 ret = drm_universal_plane_init(dev, plane, 1 << index, 407 &amdgpu_vkms_plane_funcs, 408 amdgpu_vkms_formats, 409 ARRAY_SIZE(amdgpu_vkms_formats), 410 NULL, type, NULL); 411 if (ret) { 412 kfree(plane); 413 return ERR_PTR(ret); 414 } 415 416 drm_plane_helper_add(plane, &amdgpu_vkms_primary_helper_funcs); 417 418 return plane; 419} 420 421static int amdgpu_vkms_output_init(struct drm_device *dev, struct 422 amdgpu_vkms_output *output, int index) 423{ 424 struct drm_connector *connector = &output->connector; 425 struct drm_encoder *encoder = &output->encoder; 426 struct drm_crtc *crtc = &output->crtc.base; 427 struct drm_plane *primary, *cursor = NULL; 428 int ret; 429 430 primary = amdgpu_vkms_plane_init(dev, DRM_PLANE_TYPE_PRIMARY, index); 431 if (IS_ERR(primary)) 432 return PTR_ERR(primary); 433 434 ret = amdgpu_vkms_crtc_init(dev, crtc, primary, cursor); 435 if (ret) 436 goto err_crtc; 437 438 ret = drm_connector_init(dev, connector, &amdgpu_vkms_connector_funcs, 439 DRM_MODE_CONNECTOR_VIRTUAL); 440 if (ret) { 441 DRM_ERROR("Failed to init connector\n"); 442 goto err_connector; 443 } 444 445 drm_connector_helper_add(connector, &amdgpu_vkms_conn_helper_funcs); 446 447 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_VIRTUAL); 448 if (ret) { 449 DRM_ERROR("Failed to init encoder\n"); 450 goto err_encoder; 451 } 452 encoder->possible_crtcs = 1 << index; 453 454 ret = drm_connector_attach_encoder(connector, encoder); 455 if (ret) { 456 DRM_ERROR("Failed to attach connector to encoder\n"); 457 goto err_attach; 458 } 459 460 drm_mode_config_reset(dev); 461 462 return 0; 463 464err_attach: 465 drm_encoder_cleanup(encoder); 466 467err_encoder: 468 drm_connector_cleanup(connector); 469 470err_connector: 471 drm_crtc_cleanup(crtc); 472 473err_crtc: 474 drm_plane_cleanup(primary); 475 476 return ret; 477} 478 479const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { 480 .fb_create = amdgpu_display_user_framebuffer_create, 481 .atomic_check = drm_atomic_helper_check, 482 .atomic_commit = drm_atomic_helper_commit, 483}; 484 485static int amdgpu_vkms_sw_init(void *handle) 486{ 487 int r, i; 488 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 489 490 adev->amdgpu_vkms_output = kcalloc(adev->mode_info.num_crtc, 491 sizeof(struct amdgpu_vkms_output), GFP_KERNEL); 492 if (!adev->amdgpu_vkms_output) 493 return -ENOMEM; 494 495 adev_to_drm(adev)->max_vblank_count = 0; 496 497 adev_to_drm(adev)->mode_config.funcs = &amdgpu_vkms_mode_funcs; 498 499 adev_to_drm(adev)->mode_config.max_width = XRES_MAX; 500 adev_to_drm(adev)->mode_config.max_height = YRES_MAX; 501 502 adev_to_drm(adev)->mode_config.preferred_depth = 24; 503 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 504 505 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 506 507 r = amdgpu_display_modeset_create_props(adev); 508 if (r) 509 return r; 510 511 /* allocate crtcs, encoders, connectors */ 512 for (i = 0; i < adev->mode_info.num_crtc; i++) { 513 r = amdgpu_vkms_output_init(adev_to_drm(adev), &adev->amdgpu_vkms_output[i], i); 514 if (r) 515 return r; 516 } 517 518 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 519 if (r) 520 return r; 521 522 drm_kms_helper_poll_init(adev_to_drm(adev)); 523 524 adev->mode_info.mode_config_initialized = true; 525 return 0; 526} 527 528static int amdgpu_vkms_sw_fini(void *handle) 529{ 530 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 531 int i = 0; 532 533 for (i = 0; i < adev->mode_info.num_crtc; i++) 534 if (adev->mode_info.crtcs[i]) 535 hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer); 536 537 drm_kms_helper_poll_fini(adev_to_drm(adev)); 538 drm_mode_config_cleanup(adev_to_drm(adev)); 539 540 adev->mode_info.mode_config_initialized = false; 541 542 kfree(adev->mode_info.bios_hardcoded_edid); 543 kfree(adev->amdgpu_vkms_output); 544 return 0; 545} 546 547static int amdgpu_vkms_hw_init(void *handle) 548{ 549 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 550 551 switch (adev->asic_type) { 552#ifdef CONFIG_DRM_AMDGPU_SI 553 case CHIP_TAHITI: 554 case CHIP_PITCAIRN: 555 case CHIP_VERDE: 556 case CHIP_OLAND: 557 dce_v6_0_disable_dce(adev); 558 break; 559#endif 560#ifdef CONFIG_DRM_AMDGPU_CIK 561 case CHIP_BONAIRE: 562 case CHIP_HAWAII: 563 case CHIP_KAVERI: 564 case CHIP_KABINI: 565 case CHIP_MULLINS: 566 dce_v8_0_disable_dce(adev); 567 break; 568#endif 569 case CHIP_FIJI: 570 case CHIP_TONGA: 571 dce_v10_0_disable_dce(adev); 572 break; 573 case CHIP_CARRIZO: 574 case CHIP_STONEY: 575 case CHIP_POLARIS10: 576 case CHIP_POLARIS11: 577 case CHIP_VEGAM: 578 dce_v11_0_disable_dce(adev); 579 break; 580 case CHIP_TOPAZ: 581#ifdef CONFIG_DRM_AMDGPU_SI 582 case CHIP_HAINAN: 583#endif 584 /* no DCE */ 585 break; 586 default: 587 break; 588 } 589 return 0; 590} 591 592static int amdgpu_vkms_hw_fini(void *handle) 593{ 594 return 0; 595} 596 597static int amdgpu_vkms_suspend(void *handle) 598{ 599 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 600 int r; 601 602 r = drm_mode_config_helper_suspend(adev_to_drm(adev)); 603 if (r) 604 return r; 605 return amdgpu_vkms_hw_fini(handle); 606} 607 608static int amdgpu_vkms_resume(void *handle) 609{ 610 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 611 int r; 612 613 r = amdgpu_vkms_hw_init(handle); 614 if (r) 615 return r; 616 return drm_mode_config_helper_resume(adev_to_drm(adev)); 617} 618 619static bool amdgpu_vkms_is_idle(void *handle) 620{ 621 return true; 622} 623 624static int amdgpu_vkms_wait_for_idle(void *handle) 625{ 626 return 0; 627} 628 629static int amdgpu_vkms_soft_reset(void *handle) 630{ 631 return 0; 632} 633 634static int amdgpu_vkms_set_clockgating_state(void *handle, 635 enum amd_clockgating_state state) 636{ 637 return 0; 638} 639 640static int amdgpu_vkms_set_powergating_state(void *handle, 641 enum amd_powergating_state state) 642{ 643 return 0; 644} 645 646static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = { 647 .name = "amdgpu_vkms", 648 .early_init = NULL, 649 .late_init = NULL, 650 .sw_init = amdgpu_vkms_sw_init, 651 .sw_fini = amdgpu_vkms_sw_fini, 652 .hw_init = amdgpu_vkms_hw_init, 653 .hw_fini = amdgpu_vkms_hw_fini, 654 .suspend = amdgpu_vkms_suspend, 655 .resume = amdgpu_vkms_resume, 656 .is_idle = amdgpu_vkms_is_idle, 657 .wait_for_idle = amdgpu_vkms_wait_for_idle, 658 .soft_reset = amdgpu_vkms_soft_reset, 659 .set_clockgating_state = amdgpu_vkms_set_clockgating_state, 660 .set_powergating_state = amdgpu_vkms_set_powergating_state, 661}; 662 663const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = { 664 .type = AMD_IP_BLOCK_TYPE_DCE, 665 .major = 1, 666 .minor = 0, 667 .rev = 0, 668 .funcs = &amdgpu_vkms_ip_funcs, 669}; 670 671