1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef __AMDGPU_TTM_H__ 25#define __AMDGPU_TTM_H__ 26 27#include <linux/dma-direction.h> 28#include <drm/gpu_scheduler.h> 29#include "amdgpu_vram_mgr.h" 30#include "amdgpu.h" 31 32#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) 33#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) 34#define AMDGPU_PL_OA (TTM_PL_PRIV + 2) 35#define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) 36#define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4) 37 38#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 39#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 40 41#define AMDGPU_POISON 0xd0bed0be 42 43extern const struct attribute_group amdgpu_vram_mgr_attr_group; 44extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 45 46struct hmm_range; 47 48struct amdgpu_gtt_mgr { 49 struct ttm_resource_manager manager; 50 struct drm_mm mm; 51 spinlock_t lock; 52}; 53 54struct amdgpu_mman { 55 struct ttm_device bdev; 56 struct ttm_pool *ttm_pools; 57 bool initialized; 58 void __iomem *aper_base_kaddr; 59 60 /* buffer handling */ 61 const struct amdgpu_buffer_funcs *buffer_funcs; 62 struct amdgpu_ring *buffer_funcs_ring; 63 bool buffer_funcs_enabled; 64 65 struct mutex gtt_window_lock; 66 /* High priority scheduler entity for buffer moves */ 67 struct drm_sched_entity high_pr; 68 /* Low priority scheduler entity for VRAM clearing */ 69 struct drm_sched_entity low_pr; 70 71 struct amdgpu_vram_mgr vram_mgr; 72 struct amdgpu_gtt_mgr gtt_mgr; 73 struct ttm_resource_manager preempt_mgr; 74 75 uint64_t stolen_vga_size; 76 struct amdgpu_bo *stolen_vga_memory; 77 uint64_t stolen_extended_size; 78 struct amdgpu_bo *stolen_extended_memory; 79 bool keep_stolen_vga_memory; 80 81 struct amdgpu_bo *stolen_reserved_memory; 82 uint64_t stolen_reserved_offset; 83 uint64_t stolen_reserved_size; 84 85 /* discovery */ 86 uint8_t *discovery_bin; 87 uint32_t discovery_tmr_size; 88 /* fw reserved memory */ 89 struct amdgpu_bo *fw_reserved_memory; 90 91 /* firmware VRAM reservation */ 92 u64 fw_vram_usage_start_offset; 93 u64 fw_vram_usage_size; 94 struct amdgpu_bo *fw_vram_usage_reserved_bo; 95 void *fw_vram_usage_va; 96 97 /* driver VRAM reservation */ 98 u64 drv_vram_usage_start_offset; 99 u64 drv_vram_usage_size; 100 struct amdgpu_bo *drv_vram_usage_reserved_bo; 101 void *drv_vram_usage_va; 102 103 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */ 104 struct amdgpu_bo *sdma_access_bo; 105 void *sdma_access_ptr; 106}; 107 108struct amdgpu_copy_mem { 109 struct ttm_buffer_object *bo; 110 struct ttm_resource *mem; 111 unsigned long offset; 112}; 113 114int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); 115void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); 116int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); 117void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); 118int amdgpu_vram_mgr_init(struct amdgpu_device *adev); 119void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); 120 121bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); 122void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr); 123 124uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man); 125 126u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); 127int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 128 struct ttm_resource *mem, 129 u64 offset, u64 size, 130 struct device *dev, 131 enum dma_data_direction dir, 132 struct sg_table **sgt); 133void amdgpu_vram_mgr_free_sgt(struct device *dev, 134 enum dma_data_direction dir, 135 struct sg_table *sgt); 136uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr); 137int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, 138 uint64_t start, uint64_t size); 139int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr, 140 uint64_t start); 141 142bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, 143 struct ttm_resource *res); 144 145int amdgpu_ttm_init(struct amdgpu_device *adev); 146void amdgpu_ttm_fini(struct amdgpu_device *adev); 147void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, 148 bool enable); 149 150int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 151 uint64_t dst_offset, uint32_t byte_count, 152 struct dma_resv *resv, 153 struct dma_fence **fence, bool direct_submit, 154 bool vm_needs_flush, bool tmz); 155int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 156 const struct amdgpu_copy_mem *src, 157 const struct amdgpu_copy_mem *dst, 158 uint64_t size, bool tmz, 159 struct dma_resv *resv, 160 struct dma_fence **f); 161int amdgpu_fill_buffer(struct amdgpu_bo *bo, 162 uint32_t src_data, 163 struct dma_resv *resv, 164 struct dma_fence **fence, 165 bool delayed); 166 167int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); 168void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); 169uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); 170 171#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 172int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, 173 struct hmm_range **range); 174void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, 175 struct hmm_range *range); 176bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, 177 struct hmm_range *range); 178#else 179static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 180 struct page **pages, 181 struct hmm_range **range) 182{ 183 return -EPERM; 184} 185static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, 186 struct hmm_range *range) 187{ 188} 189static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, 190 struct hmm_range *range) 191{ 192 return false; 193} 194#endif 195 196void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); 197int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 198 uint64_t *user_addr); 199int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 200 uint64_t addr, uint32_t flags); 201bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 202struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 203bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 204 unsigned long end, unsigned long *userptr); 205bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 206 int *last_invalidated); 207bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); 208bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 209uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); 210uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 211 struct ttm_resource *mem); 212int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type); 213 214void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 215 216#endif 217