1// SPDX-License-Identifier: GPL-2.0
2/* Driver for IDT/Renesas 79RC3243x Interrupt Controller  */
3
4#include <linux/bitops.h>
5#include <linux/gpio/driver.h>
6#include <linux/irq.h>
7#include <linux/module.h>
8#include <linux/mod_devicetable.h>
9#include <linux/platform_device.h>
10#include <linux/spinlock.h>
11
12#define IDT_PIC_IRQ_PEND	0x00
13#define IDT_PIC_IRQ_MASK	0x08
14
15#define IDT_GPIO_DIR		0x00
16#define IDT_GPIO_DATA		0x04
17#define IDT_GPIO_ILEVEL		0x08
18#define IDT_GPIO_ISTAT		0x0C
19
20struct idt_gpio_ctrl {
21	struct gpio_chip gc;
22	void __iomem *pic;
23	void __iomem *gpio;
24	u32 mask_cache;
25};
26
27static void idt_gpio_dispatch(struct irq_desc *desc)
28{
29	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
30	struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
31	struct irq_chip *host_chip = irq_desc_get_chip(desc);
32	unsigned int bit, virq;
33	unsigned long pending;
34
35	chained_irq_enter(host_chip, desc);
36
37	pending = readl(ctrl->pic + IDT_PIC_IRQ_PEND);
38	pending &= ~ctrl->mask_cache;
39	for_each_set_bit(bit, &pending, gc->ngpio) {
40		virq = irq_linear_revmap(gc->irq.domain, bit);
41		if (virq)
42			generic_handle_irq(virq);
43	}
44
45	chained_irq_exit(host_chip, desc);
46}
47
48static int idt_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
49{
50	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
51	struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
52	unsigned int sense = flow_type & IRQ_TYPE_SENSE_MASK;
53	unsigned long flags;
54	u32 ilevel;
55
56	/* hardware only supports level triggered */
57	if (sense == IRQ_TYPE_NONE || (sense & IRQ_TYPE_EDGE_BOTH))
58		return -EINVAL;
59
60	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
61
62	ilevel = readl(ctrl->gpio + IDT_GPIO_ILEVEL);
63	if (sense & IRQ_TYPE_LEVEL_HIGH)
64		ilevel |= BIT(d->hwirq);
65	else if (sense & IRQ_TYPE_LEVEL_LOW)
66		ilevel &= ~BIT(d->hwirq);
67
68	writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL);
69	irq_set_handler_locked(d, handle_level_irq);
70
71	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
72	return 0;
73}
74
75static void idt_gpio_ack(struct irq_data *d)
76{
77	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
78	struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
79
80	writel(~BIT(d->hwirq), ctrl->gpio + IDT_GPIO_ISTAT);
81}
82
83static void idt_gpio_mask(struct irq_data *d)
84{
85	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
86	struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
87	unsigned long flags;
88
89	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
90
91	ctrl->mask_cache |= BIT(d->hwirq);
92	writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
93
94	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
95
96	gpiochip_disable_irq(gc, irqd_to_hwirq(d));
97}
98
99static void idt_gpio_unmask(struct irq_data *d)
100{
101	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
102	struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
103	unsigned long flags;
104
105	gpiochip_enable_irq(gc, irqd_to_hwirq(d));
106	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
107
108	ctrl->mask_cache &= ~BIT(d->hwirq);
109	writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
110
111	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
112}
113
114static int idt_gpio_irq_init_hw(struct gpio_chip *gc)
115{
116	struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
117
118	/* Mask interrupts. */
119	ctrl->mask_cache = 0xffffffff;
120	writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
121
122	return 0;
123}
124
125static const struct irq_chip idt_gpio_irqchip = {
126	.name = "IDTGPIO",
127	.irq_mask = idt_gpio_mask,
128	.irq_ack = idt_gpio_ack,
129	.irq_unmask = idt_gpio_unmask,
130	.irq_set_type = idt_gpio_irq_set_type,
131	.flags = IRQCHIP_IMMUTABLE,
132	GPIOCHIP_IRQ_RESOURCE_HELPERS,
133};
134
135static int idt_gpio_probe(struct platform_device *pdev)
136{
137	struct device *dev = &pdev->dev;
138	struct gpio_irq_chip *girq;
139	struct idt_gpio_ctrl *ctrl;
140	int parent_irq;
141	int ngpios;
142	int ret;
143
144
145	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
146	if (!ctrl)
147		return -ENOMEM;
148
149	ctrl->gpio = devm_platform_ioremap_resource_byname(pdev, "gpio");
150	if (IS_ERR(ctrl->gpio))
151		return PTR_ERR(ctrl->gpio);
152
153	ctrl->gc.parent = dev;
154
155	ret = bgpio_init(&ctrl->gc, &pdev->dev, 4, ctrl->gpio + IDT_GPIO_DATA,
156			 NULL, NULL, ctrl->gpio + IDT_GPIO_DIR, NULL, 0);
157	if (ret) {
158		dev_err(dev, "bgpio_init failed\n");
159		return ret;
160	}
161
162	ret = device_property_read_u32(dev, "ngpios", &ngpios);
163	if (!ret)
164		ctrl->gc.ngpio = ngpios;
165
166	if (device_property_read_bool(dev, "interrupt-controller")) {
167		ctrl->pic = devm_platform_ioremap_resource_byname(pdev, "pic");
168		if (IS_ERR(ctrl->pic))
169			return PTR_ERR(ctrl->pic);
170
171		parent_irq = platform_get_irq(pdev, 0);
172		if (parent_irq < 0)
173			return parent_irq;
174
175		girq = &ctrl->gc.irq;
176		gpio_irq_chip_set_chip(girq, &idt_gpio_irqchip);
177		girq->init_hw = idt_gpio_irq_init_hw;
178		girq->parent_handler = idt_gpio_dispatch;
179		girq->num_parents = 1;
180		girq->parents = devm_kcalloc(dev, girq->num_parents,
181					     sizeof(*girq->parents),
182					     GFP_KERNEL);
183		if (!girq->parents)
184			return -ENOMEM;
185
186		girq->parents[0] = parent_irq;
187		girq->default_type = IRQ_TYPE_NONE;
188		girq->handler = handle_bad_irq;
189	}
190
191	return devm_gpiochip_add_data(&pdev->dev, &ctrl->gc, ctrl);
192}
193
194static const struct of_device_id idt_gpio_of_match[] = {
195	{ .compatible = "idt,32434-gpio" },
196	{ }
197};
198MODULE_DEVICE_TABLE(of, idt_gpio_of_match);
199
200static struct platform_driver idt_gpio_driver = {
201	.probe = idt_gpio_probe,
202	.driver = {
203		.name = "idt3243x-gpio",
204		.of_match_table = idt_gpio_of_match,
205	},
206};
207module_platform_driver(idt_gpio_driver);
208
209MODULE_DESCRIPTION("IDT 79RC3243x GPIO/PIC Driver");
210MODULE_AUTHOR("Thomas Bogendoerfer <tsbogend@alpha.franken.de>");
211MODULE_LICENSE("GPL");
212