1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
4 *
5 * Copyright (C) 2010 Extreme Engineering Solutions.
6 */
7
8#include <linux/bitops.h>
9#include <linux/gpio/driver.h>
10#include <linux/ioport.h>
11#include <linux/mfd/lpc_ich.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14
15#define DRV_NAME "gpio_ich"
16
17/*
18 * GPIO register offsets in GPIO I/O space.
19 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
20 * LVLx registers.  Logic in the read/write functions takes a register and
21 * an absolute bit number and determines the proper register offset and bit
22 * number in that register.  For example, to read the value of GPIO bit 50
23 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
24 * bit 18 (50%32).
25 */
26enum GPIO_REG {
27	GPIO_USE_SEL = 0,
28	GPIO_IO_SEL,
29	GPIO_LVL,
30	GPO_BLINK
31};
32
33static const u8 ichx_regs[4][3] = {
34	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
35	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
36	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
37	{0x18, 0x18, 0x18},	/* BLINK offset */
38};
39
40static const u8 ichx_reglen[3] = {
41	0x30, 0x10, 0x10,
42};
43
44static const u8 avoton_regs[4][3] = {
45	{0x00, 0x80, 0x00},
46	{0x04, 0x84, 0x00},
47	{0x08, 0x88, 0x00},
48};
49
50static const u8 avoton_reglen[3] = {
51	0x10, 0x10, 0x00,
52};
53
54#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
55#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)
56
57struct ichx_desc {
58	/* Max GPIO pins the chipset can have */
59	uint ngpio;
60
61	/* chipset registers */
62	const u8 (*regs)[3];
63	const u8 *reglen;
64
65	/* GPO_BLINK is available on this chipset */
66	bool have_blink;
67
68	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
69	bool uses_gpe0;
70
71	/* USE_SEL is bogus on some chipsets, eg 3100 */
72	u32 use_sel_ignore[3];
73
74	/* Some chipsets have quirks, let these use their own request/get */
75	int (*request)(struct gpio_chip *chip, unsigned int offset);
76	int (*get)(struct gpio_chip *chip, unsigned int offset);
77
78	/*
79	 * Some chipsets don't let reading output values on GPIO_LVL register
80	 * this option allows driver caching written output values
81	 */
82	bool use_outlvl_cache;
83};
84
85static struct {
86	spinlock_t lock;
87	struct device *dev;
88	struct gpio_chip chip;
89	struct resource *gpio_base;	/* GPIO IO base */
90	struct resource *pm_base;	/* Power Management IO base */
91	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
92	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
93	u8 use_gpio;		/* Which GPIO groups are usable */
94	int outlvl_cache[3];	/* cached output values */
95} ichx_priv;
96
97static int modparam_gpiobase = -1;	/* dynamic */
98module_param_named(gpiobase, modparam_gpiobase, int, 0444);
99MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");
100
101static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)
102{
103	unsigned long flags;
104	u32 data, tmp;
105	int reg_nr = nr / 32;
106	int bit = nr & 0x1f;
107
108	spin_lock_irqsave(&ichx_priv.lock, flags);
109
110	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
111		data = ichx_priv.outlvl_cache[reg_nr];
112	else
113		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
114				 ichx_priv.gpio_base);
115
116	if (val)
117		data |= BIT(bit);
118	else
119		data &= ~BIT(bit);
120	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
121			 ichx_priv.gpio_base);
122	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
123		ichx_priv.outlvl_cache[reg_nr] = data;
124
125	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
126			ichx_priv.gpio_base);
127
128	spin_unlock_irqrestore(&ichx_priv.lock, flags);
129
130	return (verify && data != tmp) ? -EPERM : 0;
131}
132
133static int ichx_read_bit(int reg, unsigned int nr)
134{
135	unsigned long flags;
136	u32 data;
137	int reg_nr = nr / 32;
138	int bit = nr & 0x1f;
139
140	spin_lock_irqsave(&ichx_priv.lock, flags);
141
142	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
143			 ichx_priv.gpio_base);
144
145	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
146		data = ichx_priv.outlvl_cache[reg_nr] | data;
147
148	spin_unlock_irqrestore(&ichx_priv.lock, flags);
149
150	return !!(data & BIT(bit));
151}
152
153static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned int nr)
154{
155	return !!(ichx_priv.use_gpio & BIT(nr / 32));
156}
157
158static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
159{
160	if (ichx_read_bit(GPIO_IO_SEL, nr))
161		return GPIO_LINE_DIRECTION_IN;
162
163	return GPIO_LINE_DIRECTION_OUT;
164}
165
166static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
167{
168	/*
169	 * Try setting pin as an input and verify it worked since many pins
170	 * are output-only.
171	 */
172	return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);
173}
174
175static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
176					int val)
177{
178	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
179	if (nr < 32 && ichx_priv.desc->have_blink)
180		ichx_write_bit(GPO_BLINK, nr, 0, 0);
181
182	/* Set GPIO output value. */
183	ichx_write_bit(GPIO_LVL, nr, val, 0);
184
185	/*
186	 * Try setting pin as an output and verify it worked since many pins
187	 * are input-only.
188	 */
189	return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);
190}
191
192static int ichx_gpio_get(struct gpio_chip *chip, unsigned int nr)
193{
194	return ichx_read_bit(GPIO_LVL, nr);
195}
196
197static int ich6_gpio_get(struct gpio_chip *chip, unsigned int nr)
198{
199	unsigned long flags;
200	u32 data;
201
202	/*
203	 * GPI 0 - 15 need to be read from the power management registers on
204	 * a ICH6/3100 bridge.
205	 */
206	if (nr < 16) {
207		if (!ichx_priv.pm_base)
208			return -ENXIO;
209
210		spin_lock_irqsave(&ichx_priv.lock, flags);
211
212		/* GPI 0 - 15 are latched, write 1 to clear*/
213		ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
214		data = ICHX_READ(0, ichx_priv.pm_base);
215
216		spin_unlock_irqrestore(&ichx_priv.lock, flags);
217
218		return !!((data >> 16) & BIT(nr));
219	} else {
220		return ichx_gpio_get(chip, nr);
221	}
222}
223
224static int ichx_gpio_request(struct gpio_chip *chip, unsigned int nr)
225{
226	if (!ichx_gpio_check_available(chip, nr))
227		return -ENXIO;
228
229	/*
230	 * Note we assume the BIOS properly set a bridge's USE value.  Some
231	 * chips (eg Intel 3100) have bogus USE values though, so first see if
232	 * the chipset's USE value can be trusted for this specific bit.
233	 * If it can't be trusted, assume that the pin can be used as a GPIO.
234	 */
235	if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
236		return 0;
237
238	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
239}
240
241static int ich6_gpio_request(struct gpio_chip *chip, unsigned int nr)
242{
243	/*
244	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
245	 * bridge as they are controlled by USE register bits 0 and 1.  See
246	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
247	 * additional info.
248	 */
249	if (nr == 16 || nr == 17)
250		nr -= 16;
251
252	return ichx_gpio_request(chip, nr);
253}
254
255static void ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)
256{
257	ichx_write_bit(GPIO_LVL, nr, val, 0);
258}
259
260static void ichx_gpiolib_setup(struct gpio_chip *chip)
261{
262	chip->owner = THIS_MODULE;
263	chip->label = DRV_NAME;
264	chip->parent = ichx_priv.dev;
265
266	/* Allow chip-specific overrides of request()/get() */
267	chip->request = ichx_priv.desc->request ?
268		ichx_priv.desc->request : ichx_gpio_request;
269	chip->get = ichx_priv.desc->get ?
270		ichx_priv.desc->get : ichx_gpio_get;
271
272	chip->set = ichx_gpio_set;
273	chip->get_direction = ichx_gpio_get_direction;
274	chip->direction_input = ichx_gpio_direction_input;
275	chip->direction_output = ichx_gpio_direction_output;
276	chip->base = modparam_gpiobase;
277	chip->ngpio = ichx_priv.desc->ngpio;
278	chip->can_sleep = false;
279	chip->dbg_show = NULL;
280}
281
282/* ICH6-based, 631xesb-based */
283static struct ichx_desc ich6_desc = {
284	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
285	.request = ich6_gpio_request,
286	.get = ich6_gpio_get,
287
288	/* GPIO 0-15 are read in the GPE0_STS PM register */
289	.uses_gpe0 = true,
290
291	.ngpio = 50,
292	.have_blink = true,
293	.regs = ichx_regs,
294	.reglen = ichx_reglen,
295};
296
297/* Intel 3100 */
298static struct ichx_desc i3100_desc = {
299	/*
300	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
301	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
302	 * Datasheet for more info.
303	 */
304	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
305
306	/* The 3100 needs fixups for GPIO 0 - 17 */
307	.request = ich6_gpio_request,
308	.get = ich6_gpio_get,
309
310	/* GPIO 0-15 are read in the GPE0_STS PM register */
311	.uses_gpe0 = true,
312
313	.ngpio = 50,
314	.regs = ichx_regs,
315	.reglen = ichx_reglen,
316};
317
318/* ICH7 and ICH8-based */
319static struct ichx_desc ich7_desc = {
320	.ngpio = 50,
321	.have_blink = true,
322	.regs = ichx_regs,
323	.reglen = ichx_reglen,
324};
325
326/* ICH9-based */
327static struct ichx_desc ich9_desc = {
328	.ngpio = 61,
329	.have_blink = true,
330	.regs = ichx_regs,
331	.reglen = ichx_reglen,
332};
333
334/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
335static struct ichx_desc ich10_cons_desc = {
336	.ngpio = 61,
337	.have_blink = true,
338	.regs = ichx_regs,
339	.reglen = ichx_reglen,
340};
341static struct ichx_desc ich10_corp_desc = {
342	.ngpio = 72,
343	.have_blink = true,
344	.regs = ichx_regs,
345	.reglen = ichx_reglen,
346};
347
348/* Intel 5 series, 6 series, 3400 series, and C200 series */
349static struct ichx_desc intel5_desc = {
350	.ngpio = 76,
351	.regs = ichx_regs,
352	.reglen = ichx_reglen,
353};
354
355/* Avoton */
356static struct ichx_desc avoton_desc = {
357	/* Avoton has only 59 GPIOs, but we assume the first set of register
358	 * (Core) has 32 instead of 31 to keep gpio-ich compliance
359	 */
360	.ngpio = 60,
361	.regs = avoton_regs,
362	.reglen = avoton_reglen,
363	.use_outlvl_cache = true,
364};
365
366static int ichx_gpio_request_regions(struct device *dev,
367	struct resource *res_base, const char *name, u8 use_gpio)
368{
369	int i;
370
371	if (!res_base || !res_base->start || !res_base->end)
372		return -ENODEV;
373
374	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
375		if (!(use_gpio & BIT(i)))
376			continue;
377		if (!devm_request_region(dev,
378				res_base->start + ichx_priv.desc->regs[0][i],
379				ichx_priv.desc->reglen[i], name))
380			return -EBUSY;
381	}
382	return 0;
383}
384
385static int ichx_gpio_probe(struct platform_device *pdev)
386{
387	struct device *dev = &pdev->dev;
388	struct lpc_ich_info *ich_info = dev_get_platdata(dev);
389	struct resource *res_base, *res_pm;
390	int err;
391
392	if (!ich_info)
393		return -ENODEV;
394
395	switch (ich_info->gpio_version) {
396	case ICH_I3100_GPIO:
397		ichx_priv.desc = &i3100_desc;
398		break;
399	case ICH_V5_GPIO:
400		ichx_priv.desc = &intel5_desc;
401		break;
402	case ICH_V6_GPIO:
403		ichx_priv.desc = &ich6_desc;
404		break;
405	case ICH_V7_GPIO:
406		ichx_priv.desc = &ich7_desc;
407		break;
408	case ICH_V9_GPIO:
409		ichx_priv.desc = &ich9_desc;
410		break;
411	case ICH_V10CORP_GPIO:
412		ichx_priv.desc = &ich10_corp_desc;
413		break;
414	case ICH_V10CONS_GPIO:
415		ichx_priv.desc = &ich10_cons_desc;
416		break;
417	case AVOTON_GPIO:
418		ichx_priv.desc = &avoton_desc;
419		break;
420	default:
421		return -ENODEV;
422	}
423
424	ichx_priv.dev = dev;
425	spin_lock_init(&ichx_priv.lock);
426
427	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
428	err = ichx_gpio_request_regions(dev, res_base, pdev->name,
429					ich_info->use_gpio);
430	if (err)
431		return err;
432
433	ichx_priv.gpio_base = res_base;
434	ichx_priv.use_gpio = ich_info->use_gpio;
435
436	/*
437	 * If necessary, determine the I/O address of ACPI/power management
438	 * registers which are needed to read the GPE0 register for GPI pins
439	 * 0 - 15 on some chipsets.
440	 */
441	if (!ichx_priv.desc->uses_gpe0)
442		goto init;
443
444	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
445	if (!res_pm) {
446		dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
447		goto init;
448	}
449
450	if (!devm_request_region(dev, res_pm->start, resource_size(res_pm),
451				 pdev->name)) {
452		dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n");
453		goto init;
454	}
455
456	ichx_priv.pm_base = res_pm;
457
458init:
459	ichx_gpiolib_setup(&ichx_priv.chip);
460	err = devm_gpiochip_add_data(dev, &ichx_priv.chip, NULL);
461	if (err) {
462		dev_err(dev, "Failed to register GPIOs\n");
463		return err;
464	}
465
466	dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,
467		 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);
468
469	return 0;
470}
471
472static struct platform_driver ichx_gpio_driver = {
473	.driver		= {
474		.name	= DRV_NAME,
475	},
476	.probe		= ichx_gpio_probe,
477};
478
479module_platform_driver(ichx_gpio_driver);
480
481MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
482MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
483MODULE_LICENSE("GPL");
484MODULE_ALIAS("platform:"DRV_NAME);
485