1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * UEFI Common Platform Error Record (CPER) support for CXL Section.
4 *
5 * Copyright (C) 2022 Advanced Micro Devices, Inc.
6 *
7 * Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
8 */
9
10#ifndef LINUX_CPER_CXL_H
11#define LINUX_CPER_CXL_H
12
13/* CXL Protocol Error Section */
14#define CPER_SEC_CXL_PROT_ERR						\
15	GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78,	\
16		  0x4B, 0x77, 0x10, 0x48)
17
18#pragma pack(1)
19
20/* Compute Express Link Protocol Error Section, UEFI v2.10 sec N.2.13 */
21struct cper_sec_prot_err {
22	u64 valid_bits;
23	u8 agent_type;
24	u8 reserved[7];
25
26	/*
27	 * Except for RCH Downstream Port, all the remaining CXL Agent
28	 * types are uniquely identified by the PCIe compatible SBDF number.
29	 */
30	union {
31		u64 rcrb_base_addr;
32		struct {
33			u8 function;
34			u8 device;
35			u8 bus;
36			u16 segment;
37			u8 reserved_1[3];
38		};
39	} agent_addr;
40
41	struct {
42		u16 vendor_id;
43		u16 device_id;
44		u16 subsystem_vendor_id;
45		u16 subsystem_id;
46		u8 class_code[2];
47		u16 slot;
48		u8 reserved_1[4];
49	} device_id;
50
51	struct {
52		u32 lower_dw;
53		u32 upper_dw;
54	} dev_serial_num;
55
56	u8 capability[60];
57	u16 dvsec_len;
58	u16 err_len;
59	u8 reserved_2[4];
60};
61
62#pragma pack()
63
64void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_err);
65
66#endif //__CPER_CXL_
67