1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2/* Copyright(c) 2020 Intel Corporation */ 3#ifndef ADF_GEN4_HW_CSR_DATA_H_ 4#define ADF_GEN4_HW_CSR_DATA_H_ 5 6#include <linux/units.h> 7 8#include "adf_accel_devices.h" 9#include "adf_cfg_common.h" 10 11/* PCIe configuration space */ 12#define ADF_GEN4_BAR_MASK (BIT(0) | BIT(2) | BIT(4)) 13#define ADF_GEN4_SRAM_BAR 0 14#define ADF_GEN4_PMISC_BAR 1 15#define ADF_GEN4_ETR_BAR 2 16 17/* Clocks frequency */ 18#define ADF_GEN4_KPT_COUNTER_FREQ (100 * HZ_PER_MHZ) 19 20/* Physical function fuses */ 21#define ADF_GEN4_FUSECTL0_OFFSET 0x2C8 22#define ADF_GEN4_FUSECTL1_OFFSET 0x2CC 23#define ADF_GEN4_FUSECTL2_OFFSET 0x2D0 24#define ADF_GEN4_FUSECTL3_OFFSET 0x2D4 25#define ADF_GEN4_FUSECTL4_OFFSET 0x2D8 26#define ADF_GEN4_FUSECTL5_OFFSET 0x2DC 27 28/* Accelerators */ 29#define ADF_GEN4_ACCELERATORS_MASK 0x1 30#define ADF_GEN4_MAX_ACCELERATORS 1 31#define ADF_GEN4_ADMIN_ACCELENGINES 1 32 33/* MSIX interrupt */ 34#define ADF_GEN4_SMIAPF_RP_X0_MASK_OFFSET 0x41A040 35#define ADF_GEN4_SMIAPF_RP_X1_MASK_OFFSET 0x41A044 36#define ADF_GEN4_SMIAPF_MASK_OFFSET 0x41A084 37#define ADF_GEN4_MSIX_RTTABLE_OFFSET(i) (0x409000 + ((i) * 0x04)) 38 39/* Bank and ring configuration */ 40#define ADF_GEN4_MAX_RPS 64 41#define ADF_GEN4_NUM_RINGS_PER_BANK 2 42#define ADF_GEN4_NUM_BANKS_PER_VF 4 43#define ADF_GEN4_ETR_MAX_BANKS 64 44#define ADF_GEN4_RX_RINGS_OFFSET 1 45#define ADF_GEN4_TX_RINGS_MASK 0x1 46 47/* Arbiter configuration */ 48#define ADF_GEN4_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0)) 49#define ADF_GEN4_ARB_OFFSET 0x0 50#define ADF_GEN4_ARB_WRK_2_SER_MAP_OFFSET 0x400 51 52/* Admin Interface Reg Offset */ 53#define ADF_GEN4_ADMINMSGUR_OFFSET 0x500574 54#define ADF_GEN4_ADMINMSGLR_OFFSET 0x500578 55#define ADF_GEN4_MAILBOX_BASE_OFFSET 0x600970 56 57/* Transport access */ 58#define ADF_BANK_INT_SRC_SEL_MASK 0x44UL 59#define ADF_RING_CSR_RING_CONFIG 0x1000 60#define ADF_RING_CSR_RING_LBASE 0x1040 61#define ADF_RING_CSR_RING_UBASE 0x1080 62#define ADF_RING_CSR_RING_HEAD 0x0C0 63#define ADF_RING_CSR_RING_TAIL 0x100 64#define ADF_RING_CSR_E_STAT 0x14C 65#define ADF_RING_CSR_INT_FLAG 0x170 66#define ADF_RING_CSR_INT_SRCSEL 0x174 67#define ADF_RING_CSR_INT_COL_CTL 0x180 68#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 69#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 70#define ADF_RING_CSR_INT_COL_EN 0x17C 71#define ADF_RING_CSR_ADDR_OFFSET 0x100000 72#define ADF_RING_BUNDLE_SIZE 0x2000 73 74#define BUILD_RING_BASE_ADDR(addr, size) \ 75 ((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6) 76#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 77 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 78 ADF_RING_BUNDLE_SIZE * (bank) + \ 79 ADF_RING_CSR_RING_HEAD + ((ring) << 2)) 80#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 81 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 82 ADF_RING_BUNDLE_SIZE * (bank) + \ 83 ADF_RING_CSR_RING_TAIL + ((ring) << 2)) 84#define READ_CSR_E_STAT(csr_base_addr, bank) \ 85 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 86 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT) 87#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 88 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 89 ADF_RING_BUNDLE_SIZE * (bank) + \ 90 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value) 91#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 92do { \ 93 void __iomem *_csr_base_addr = csr_base_addr; \ 94 u32 _bank = bank; \ 95 u32 _ring = ring; \ 96 dma_addr_t _value = value; \ 97 u32 l_base = 0, u_base = 0; \ 98 l_base = lower_32_bits(_value); \ 99 u_base = upper_32_bits(_value); \ 100 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 101 ADF_RING_BUNDLE_SIZE * (_bank) + \ 102 ADF_RING_CSR_RING_LBASE + ((_ring) << 2), l_base); \ 103 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 104 ADF_RING_BUNDLE_SIZE * (_bank) + \ 105 ADF_RING_CSR_RING_UBASE + ((_ring) << 2), u_base); \ 106} while (0) 107 108#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 109 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 110 ADF_RING_BUNDLE_SIZE * (bank) + \ 111 ADF_RING_CSR_RING_HEAD + ((ring) << 2), value) 112#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 113 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 114 ADF_RING_BUNDLE_SIZE * (bank) + \ 115 ADF_RING_CSR_RING_TAIL + ((ring) << 2), value) 116#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 117 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 118 ADF_RING_BUNDLE_SIZE * (bank) + \ 119 ADF_RING_CSR_INT_FLAG, (value)) 120#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 121 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 122 ADF_RING_BUNDLE_SIZE * (bank) + \ 123 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK) 124#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 125 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 126 ADF_RING_BUNDLE_SIZE * (bank) + \ 127 ADF_RING_CSR_INT_COL_EN, (value)) 128#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 129 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 130 ADF_RING_BUNDLE_SIZE * (bank) + \ 131 ADF_RING_CSR_INT_COL_CTL, \ 132 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 133#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 134 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 135 ADF_RING_BUNDLE_SIZE * (bank) + \ 136 ADF_RING_CSR_INT_FLAG_AND_COL, (value)) 137 138/* Arbiter configuration */ 139#define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C 140 141#define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \ 142 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 143 ADF_RING_BUNDLE_SIZE * (bank) + \ 144 ADF_RING_CSR_RING_SRV_ARB_EN, (value)) 145 146/* Default ring mapping */ 147#define ADF_GEN4_DEFAULT_RING_TO_SRV_MAP \ 148 (ASYM << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \ 149 SYM << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \ 150 ASYM << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \ 151 SYM << ADF_CFG_SERV_RING_PAIR_3_SHIFT) 152 153/* WDT timers 154 * 155 * Timeout is in cycles. Clock speed may vary across products but this 156 * value should be a few milli-seconds. 157 */ 158#define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL 159#define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000 160#define ADF_SSMWDTL_OFFSET 0x54 161#define ADF_SSMWDTH_OFFSET 0x5C 162#define ADF_SSMWDTPKEL_OFFSET 0x58 163#define ADF_SSMWDTPKEH_OFFSET 0x60 164 165/* Ring reset */ 166#define ADF_RPRESET_POLL_TIMEOUT_US (5 * USEC_PER_SEC) 167#define ADF_RPRESET_POLL_DELAY_US 20 168#define ADF_WQM_CSR_RPRESETCTL_RESET BIT(0) 169#define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3)) 170#define ADF_WQM_CSR_RPRESETSTS_STATUS BIT(0) 171#define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4) 172 173/* Error source registers */ 174#define ADF_GEN4_ERRSOU0 (0x41A200) 175#define ADF_GEN4_ERRSOU1 (0x41A204) 176#define ADF_GEN4_ERRSOU2 (0x41A208) 177#define ADF_GEN4_ERRSOU3 (0x41A20C) 178 179/* Error source mask registers */ 180#define ADF_GEN4_ERRMSK0 (0x41A210) 181#define ADF_GEN4_ERRMSK1 (0x41A214) 182#define ADF_GEN4_ERRMSK2 (0x41A218) 183#define ADF_GEN4_ERRMSK3 (0x41A21C) 184 185#define ADF_GEN4_VFLNOTIFY BIT(7) 186 187/* Number of heartbeat counter pairs */ 188#define ADF_NUM_HB_CNT_PER_AE ADF_NUM_THREADS_PER_AE 189 190/* Rate Limiting */ 191#define ADF_GEN4_RL_R2L_OFFSET 0x508000 192#define ADF_GEN4_RL_L2C_OFFSET 0x509000 193#define ADF_GEN4_RL_C2S_OFFSET 0x508818 194#define ADF_GEN4_RL_TOKEN_PCIEIN_BUCKET_OFFSET 0x508800 195#define ADF_GEN4_RL_TOKEN_PCIEOUT_BUCKET_OFFSET 0x508804 196 197/* Arbiter threads mask with error value */ 198#define ADF_GEN4_ENA_THD_MASK_ERROR GENMASK(ADF_NUM_THREADS_PER_AE, 0) 199 200void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); 201 202enum icp_qat_gen4_slice_mask { 203 ICP_ACCEL_GEN4_MASK_CIPHER_SLICE = BIT(0), 204 ICP_ACCEL_GEN4_MASK_AUTH_SLICE = BIT(1), 205 ICP_ACCEL_GEN4_MASK_PKE_SLICE = BIT(2), 206 ICP_ACCEL_GEN4_MASK_COMPRESS_SLICE = BIT(3), 207 ICP_ACCEL_GEN4_MASK_UCS_SLICE = BIT(4), 208 ICP_ACCEL_GEN4_MASK_EIA3_SLICE = BIT(5), 209 ICP_ACCEL_GEN4_MASK_SMX_SLICE = BIT(7), 210 ICP_ACCEL_GEN4_MASK_WCP_WAT_SLICE = BIT(8), 211 ICP_ACCEL_GEN4_MASK_ZUC_256_SLICE = BIT(9), 212}; 213 214enum adf_gen4_rp_groups { 215 RP_GROUP_0, 216 RP_GROUP_1, 217 RP_GROUP_COUNT 218}; 219 220void adf_gen4_enable_error_correction(struct adf_accel_dev *accel_dev); 221void adf_gen4_enable_ints(struct adf_accel_dev *accel_dev); 222u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self); 223void adf_gen4_get_admin_info(struct admin_info *admin_csrs_info); 224void adf_gen4_get_arb_info(struct arb_info *arb_info); 225u32 adf_gen4_get_etr_bar_id(struct adf_hw_device_data *self); 226u32 adf_gen4_get_heartbeat_clock(struct adf_hw_device_data *self); 227u32 adf_gen4_get_misc_bar_id(struct adf_hw_device_data *self); 228u32 adf_gen4_get_num_accels(struct adf_hw_device_data *self); 229u32 adf_gen4_get_num_aes(struct adf_hw_device_data *self); 230enum dev_sku_info adf_gen4_get_sku(struct adf_hw_device_data *self); 231u32 adf_gen4_get_sram_bar_id(struct adf_hw_device_data *self); 232int adf_gen4_init_device(struct adf_accel_dev *accel_dev); 233void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops); 234int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number); 235void adf_gen4_set_msix_default_rttable(struct adf_accel_dev *accel_dev); 236void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); 237int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev); 238u16 adf_gen4_get_ring_to_svc_map(struct adf_accel_dev *accel_dev); 239 240#endif 241