1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Header file for NI general purpose counter support code (ni_tio.c and 4 * ni_tiocmd.c) 5 * 6 * COMEDI - Linux Control and Measurement Device Interface 7 */ 8 9#ifndef _COMEDI_NI_TIO_INTERNAL_H 10#define _COMEDI_NI_TIO_INTERNAL_H 11 12#include "ni_tio.h" 13 14#define NITIO_AUTO_INC_REG(x) (NITIO_G0_AUTO_INC + (x)) 15#define GI_AUTO_INC_MASK 0xff 16#define NITIO_CMD_REG(x) (NITIO_G0_CMD + (x)) 17#define GI_ARM BIT(0) 18#define GI_SAVE_TRACE BIT(1) 19#define GI_LOAD BIT(2) 20#define GI_DISARM BIT(4) 21#define GI_CNT_DIR(x) (((x) & 0x3) << 5) 22#define GI_CNT_DIR_MASK GI_CNT_DIR(3) 23#define GI_WRITE_SWITCH BIT(7) 24#define GI_SYNC_GATE BIT(8) 25#define GI_LITTLE_BIG_ENDIAN BIT(9) 26#define GI_BANK_SWITCH_START BIT(10) 27#define GI_BANK_SWITCH_MODE BIT(11) 28#define GI_BANK_SWITCH_ENABLE BIT(12) 29#define GI_ARM_COPY BIT(13) 30#define GI_SAVE_TRACE_COPY BIT(14) 31#define GI_DISARM_COPY BIT(15) 32#define NITIO_HW_SAVE_REG(x) (NITIO_G0_HW_SAVE + (x)) 33#define NITIO_SW_SAVE_REG(x) (NITIO_G0_SW_SAVE + (x)) 34#define NITIO_MODE_REG(x) (NITIO_G0_MODE + (x)) 35#define GI_GATING_MODE(x) (((x) & 0x3) << 0) 36#define GI_GATING_DISABLED GI_GATING_MODE(0) 37#define GI_LEVEL_GATING GI_GATING_MODE(1) 38#define GI_RISING_EDGE_GATING GI_GATING_MODE(2) 39#define GI_FALLING_EDGE_GATING GI_GATING_MODE(3) 40#define GI_GATING_MODE_MASK GI_GATING_MODE(3) 41#define GI_GATE_ON_BOTH_EDGES BIT(2) 42#define GI_EDGE_GATE_MODE(x) (((x) & 0x3) << 3) 43#define GI_EDGE_GATE_STARTS_STOPS GI_EDGE_GATE_MODE(0) 44#define GI_EDGE_GATE_STOPS_STARTS GI_EDGE_GATE_MODE(1) 45#define GI_EDGE_GATE_STARTS GI_EDGE_GATE_MODE(2) 46#define GI_EDGE_GATE_NO_STARTS_OR_STOPS GI_EDGE_GATE_MODE(3) 47#define GI_EDGE_GATE_MODE_MASK GI_EDGE_GATE_MODE(3) 48#define GI_STOP_MODE(x) (((x) & 0x3) << 5) 49#define GI_STOP_ON_GATE GI_STOP_MODE(0) 50#define GI_STOP_ON_GATE_OR_TC GI_STOP_MODE(1) 51#define GI_STOP_ON_GATE_OR_SECOND_TC GI_STOP_MODE(2) 52#define GI_STOP_MODE_MASK GI_STOP_MODE(3) 53#define GI_LOAD_SRC_SEL BIT(7) 54#define GI_OUTPUT_MODE(x) (((x) & 0x3) << 8) 55#define GI_OUTPUT_TC_PULSE GI_OUTPUT_MODE(1) 56#define GI_OUTPUT_TC_TOGGLE GI_OUTPUT_MODE(2) 57#define GI_OUTPUT_TC_OR_GATE_TOGGLE GI_OUTPUT_MODE(3) 58#define GI_OUTPUT_MODE_MASK GI_OUTPUT_MODE(3) 59#define GI_COUNTING_ONCE(x) (((x) & 0x3) << 10) 60#define GI_NO_HARDWARE_DISARM GI_COUNTING_ONCE(0) 61#define GI_DISARM_AT_TC GI_COUNTING_ONCE(1) 62#define GI_DISARM_AT_GATE GI_COUNTING_ONCE(2) 63#define GI_DISARM_AT_TC_OR_GATE GI_COUNTING_ONCE(3) 64#define GI_COUNTING_ONCE_MASK GI_COUNTING_ONCE(3) 65#define GI_LOADING_ON_TC BIT(12) 66#define GI_GATE_POL_INVERT BIT(13) 67#define GI_LOADING_ON_GATE BIT(14) 68#define GI_RELOAD_SRC_SWITCHING BIT(15) 69#define NITIO_LOADA_REG(x) (NITIO_G0_LOADA + (x)) 70#define NITIO_LOADB_REG(x) (NITIO_G0_LOADB + (x)) 71#define NITIO_INPUT_SEL_REG(x) (NITIO_G0_INPUT_SEL + (x)) 72#define GI_READ_ACKS_IRQ BIT(0) 73#define GI_WRITE_ACKS_IRQ BIT(1) 74#define GI_BITS_TO_SRC(x) (((x) >> 2) & 0x1f) 75#define GI_SRC_SEL(x) (((x) & 0x1f) << 2) 76#define GI_SRC_SEL_MASK GI_SRC_SEL(0x1f) 77#define GI_BITS_TO_GATE(x) (((x) >> 7) & 0x1f) 78#define GI_GATE_SEL(x) (((x) & 0x1f) << 7) 79#define GI_GATE_SEL_MASK GI_GATE_SEL(0x1f) 80#define GI_GATE_SEL_LOAD_SRC BIT(12) 81#define GI_OR_GATE BIT(13) 82#define GI_OUTPUT_POL_INVERT BIT(14) 83#define GI_SRC_POL_INVERT BIT(15) 84#define NITIO_CNT_MODE_REG(x) (NITIO_G0_CNT_MODE + (x)) 85#define GI_CNT_MODE(x) (((x) & 0x7) << 0) 86#define GI_CNT_MODE_NORMAL GI_CNT_MODE(0) 87#define GI_CNT_MODE_QUADX1 GI_CNT_MODE(1) 88#define GI_CNT_MODE_QUADX2 GI_CNT_MODE(2) 89#define GI_CNT_MODE_QUADX4 GI_CNT_MODE(3) 90#define GI_CNT_MODE_TWO_PULSE GI_CNT_MODE(4) 91#define GI_CNT_MODE_SYNC_SRC GI_CNT_MODE(6) 92#define GI_CNT_MODE_MASK GI_CNT_MODE(7) 93#define GI_INDEX_MODE BIT(4) 94#define GI_INDEX_PHASE(x) (((x) & 0x3) << 5) 95#define GI_INDEX_PHASE_MASK GI_INDEX_PHASE(3) 96#define GI_HW_ARM_ENA BIT(7) 97#define GI_HW_ARM_SEL(x) ((x) << 8) 98#define GI_660X_HW_ARM_SEL_MASK GI_HW_ARM_SEL(0x7) 99#define GI_M_HW_ARM_SEL_MASK GI_HW_ARM_SEL(0x1f) 100#define GI_660X_PRESCALE_X8 BIT(12) 101#define GI_M_PRESCALE_X8 BIT(13) 102#define GI_660X_ALT_SYNC BIT(13) 103#define GI_M_ALT_SYNC BIT(14) 104#define GI_660X_PRESCALE_X2 BIT(14) 105#define GI_M_PRESCALE_X2 BIT(15) 106#define NITIO_GATE2_REG(x) (NITIO_G0_GATE2 + (x)) 107#define GI_GATE2_MODE BIT(0) 108#define GI_BITS_TO_GATE2(x) (((x) >> 7) & 0x1f) 109#define GI_GATE2_SEL(x) (((x) & 0x1f) << 7) 110#define GI_GATE2_SEL_MASK GI_GATE2_SEL(0x1f) 111#define GI_GATE2_POL_INVERT BIT(13) 112#define GI_GATE2_SUBSEL BIT(14) 113#define GI_SRC_SUBSEL BIT(15) 114#define NITIO_SHARED_STATUS_REG(x) (NITIO_G01_STATUS + ((x) / 2)) 115#define GI_SAVE(x) (((x) % 2) ? BIT(1) : BIT(0)) 116#define GI_COUNTING(x) (((x) % 2) ? BIT(3) : BIT(2)) 117#define GI_NEXT_LOAD_SRC(x) (((x) % 2) ? BIT(5) : BIT(4)) 118#define GI_STALE_DATA(x) (((x) % 2) ? BIT(7) : BIT(6)) 119#define GI_ARMED(x) (((x) % 2) ? BIT(9) : BIT(8)) 120#define GI_NO_LOAD_BETWEEN_GATES(x) (((x) % 2) ? BIT(11) : BIT(10)) 121#define GI_TC_ERROR(x) (((x) % 2) ? BIT(13) : BIT(12)) 122#define GI_GATE_ERROR(x) (((x) % 2) ? BIT(15) : BIT(14)) 123#define NITIO_RESET_REG(x) (NITIO_G01_RESET + ((x) / 2)) 124#define GI_RESET(x) BIT(2 + ((x) % 2)) 125#define NITIO_STATUS1_REG(x) (NITIO_G01_STATUS1 + ((x) / 2)) 126#define NITIO_STATUS2_REG(x) (NITIO_G01_STATUS2 + ((x) / 2)) 127#define GI_OUTPUT(x) (((x) % 2) ? BIT(1) : BIT(0)) 128#define GI_HW_SAVE(x) (((x) % 2) ? BIT(13) : BIT(12)) 129#define GI_PERMANENT_STALE(x) (((x) % 2) ? BIT(15) : BIT(14)) 130#define NITIO_DMA_CFG_REG(x) (NITIO_G0_DMA_CFG + (x)) 131#define GI_DMA_ENABLE BIT(0) 132#define GI_DMA_WRITE BIT(1) 133#define GI_DMA_INT_ENA BIT(2) 134#define GI_DMA_RESET BIT(3) 135#define GI_DMA_BANKSW_ERROR BIT(4) 136#define NITIO_DMA_STATUS_REG(x) (NITIO_G0_DMA_STATUS + (x)) 137#define GI_DMA_READBANK BIT(13) 138#define GI_DRQ_ERROR BIT(14) 139#define GI_DRQ_STATUS BIT(15) 140#define NITIO_ABZ_REG(x) (NITIO_G0_ABZ + (x)) 141#define NITIO_INT_ACK_REG(x) (NITIO_G0_INT_ACK + (x)) 142#define GI_GATE_ERROR_CONFIRM(x) (((x) % 2) ? BIT(1) : BIT(5)) 143#define GI_TC_ERROR_CONFIRM(x) (((x) % 2) ? BIT(2) : BIT(6)) 144#define GI_TC_INTERRUPT_ACK BIT(14) 145#define GI_GATE_INTERRUPT_ACK BIT(15) 146#define NITIO_STATUS_REG(x) (NITIO_G0_STATUS + (x)) 147#define GI_GATE_INTERRUPT BIT(2) 148#define GI_TC BIT(3) 149#define GI_INTERRUPT BIT(15) 150#define NITIO_INT_ENA_REG(x) (NITIO_G0_INT_ENA + (x)) 151#define GI_TC_INTERRUPT_ENABLE(x) (((x) % 2) ? BIT(9) : BIT(6)) 152#define GI_GATE_INTERRUPT_ENABLE(x) (((x) % 2) ? BIT(10) : BIT(8)) 153 154void ni_tio_write(struct ni_gpct *counter, unsigned int value, 155 enum ni_gpct_register); 156unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register); 157 158static inline bool 159ni_tio_counting_mode_registers_present(const struct ni_gpct_device *counter_dev) 160{ 161 /* m series and 660x variants have counting mode registers */ 162 return counter_dev->variant != ni_gpct_variant_e_series; 163} 164 165void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg, 166 unsigned int mask, unsigned int value); 167unsigned int ni_tio_get_soft_copy(const struct ni_gpct *counter, 168 enum ni_gpct_register reg); 169 170int ni_tio_arm(struct ni_gpct *counter, bool arm, unsigned int start_trigger); 171int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned int gate, 172 unsigned int src); 173int ni_tio_set_gate_src_raw(struct ni_gpct *counter, unsigned int gate, 174 unsigned int src); 175 176#endif /* _COMEDI_NI_TIO_INTERNAL_H */ 177