1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 4 * https://www.samsung.com 5 * Copyright (c) 2017-2022 Tesla, Inc. 6 * https://www.tesla.com 7 * 8 * Common Clock Framework support for FSD SoC. 9 */ 10 11#include <linux/clk.h> 12#include <linux/clk-provider.h> 13#include <linux/init.h> 14#include <linux/kernel.h> 15#include <linux/of.h> 16#include <linux/platform_device.h> 17 18#include <dt-bindings/clock/fsd-clk.h> 19 20#include "clk.h" 21#include "clk-exynos-arm64.h" 22 23/* Register Offset definitions for CMU_CMU (0x11c10000) */ 24#define PLL_LOCKTIME_PLL_SHARED0 0x0 25#define PLL_LOCKTIME_PLL_SHARED1 0x4 26#define PLL_LOCKTIME_PLL_SHARED2 0x8 27#define PLL_LOCKTIME_PLL_SHARED3 0xc 28#define PLL_CON0_PLL_SHARED0 0x100 29#define PLL_CON0_PLL_SHARED1 0x120 30#define PLL_CON0_PLL_SHARED2 0x140 31#define PLL_CON0_PLL_SHARED3 0x160 32#define MUX_CMU_CIS0_CLKMUX 0x1000 33#define MUX_CMU_CIS1_CLKMUX 0x1004 34#define MUX_CMU_CIS2_CLKMUX 0x1008 35#define MUX_CMU_CPUCL_SWITCHMUX 0x100c 36#define MUX_CMU_FSYS1_ACLK_MUX 0x1014 37#define MUX_PLL_SHARED0_MUX 0x1020 38#define MUX_PLL_SHARED1_MUX 0x1024 39#define DIV_CMU_CIS0_CLK 0x1800 40#define DIV_CMU_CIS1_CLK 0x1804 41#define DIV_CMU_CIS2_CLK 0x1808 42#define DIV_CMU_CMU_ACLK 0x180c 43#define DIV_CMU_CPUCL_SWITCH 0x1810 44#define DIV_CMU_FSYS0_SHARED0DIV4 0x181c 45#define DIV_CMU_FSYS0_SHARED1DIV3 0x1820 46#define DIV_CMU_FSYS0_SHARED1DIV4 0x1824 47#define DIV_CMU_FSYS1_SHARED0DIV4 0x1828 48#define DIV_CMU_FSYS1_SHARED0DIV8 0x182c 49#define DIV_CMU_IMEM_ACLK 0x1834 50#define DIV_CMU_IMEM_DMACLK 0x1838 51#define DIV_CMU_IMEM_TCUCLK 0x183c 52#define DIV_CMU_PERIC_SHARED0DIV20 0x1844 53#define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848 54#define DIV_CMU_PERIC_SHARED1DIV36 0x184c 55#define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850 56#define DIV_PLL_SHARED0_DIV2 0x1858 57#define DIV_PLL_SHARED0_DIV3 0x185c 58#define DIV_PLL_SHARED0_DIV4 0x1860 59#define DIV_PLL_SHARED0_DIV6 0x1864 60#define DIV_PLL_SHARED1_DIV3 0x1868 61#define DIV_PLL_SHARED1_DIV36 0x186c 62#define DIV_PLL_SHARED1_DIV4 0x1870 63#define DIV_PLL_SHARED1_DIV9 0x1874 64#define GAT_CMU_CIS0_CLKGATE 0x2000 65#define GAT_CMU_CIS1_CLKGATE 0x2004 66#define GAT_CMU_CIS2_CLKGATE 0x2008 67#define GAT_CMU_CPUCL_SWITCH_GATE 0x200c 68#define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018 69#define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c 70#define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020 71#define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024 72#define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028 73#define GAT_CMU_IMEM_ACLK_GATE 0x2030 74#define GAT_CMU_IMEM_DMACLK_GATE 0x2034 75#define GAT_CMU_IMEM_TCUCLK_GATE 0x2038 76#define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040 77#define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044 78#define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048 79#define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c 80#define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054 81#define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058 82#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c 83#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060 84 85static const unsigned long cmu_clk_regs[] __initconst = { 86 PLL_LOCKTIME_PLL_SHARED0, 87 PLL_LOCKTIME_PLL_SHARED1, 88 PLL_LOCKTIME_PLL_SHARED2, 89 PLL_LOCKTIME_PLL_SHARED3, 90 PLL_CON0_PLL_SHARED0, 91 PLL_CON0_PLL_SHARED1, 92 PLL_CON0_PLL_SHARED2, 93 PLL_CON0_PLL_SHARED3, 94 MUX_CMU_CIS0_CLKMUX, 95 MUX_CMU_CIS1_CLKMUX, 96 MUX_CMU_CIS2_CLKMUX, 97 MUX_CMU_CPUCL_SWITCHMUX, 98 MUX_CMU_FSYS1_ACLK_MUX, 99 MUX_PLL_SHARED0_MUX, 100 MUX_PLL_SHARED1_MUX, 101 DIV_CMU_CIS0_CLK, 102 DIV_CMU_CIS1_CLK, 103 DIV_CMU_CIS2_CLK, 104 DIV_CMU_CMU_ACLK, 105 DIV_CMU_CPUCL_SWITCH, 106 DIV_CMU_FSYS0_SHARED0DIV4, 107 DIV_CMU_FSYS0_SHARED1DIV3, 108 DIV_CMU_FSYS0_SHARED1DIV4, 109 DIV_CMU_FSYS1_SHARED0DIV4, 110 DIV_CMU_FSYS1_SHARED0DIV8, 111 DIV_CMU_IMEM_ACLK, 112 DIV_CMU_IMEM_DMACLK, 113 DIV_CMU_IMEM_TCUCLK, 114 DIV_CMU_PERIC_SHARED0DIV20, 115 DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 116 DIV_CMU_PERIC_SHARED1DIV36, 117 DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 118 DIV_PLL_SHARED0_DIV2, 119 DIV_PLL_SHARED0_DIV3, 120 DIV_PLL_SHARED0_DIV4, 121 DIV_PLL_SHARED0_DIV6, 122 DIV_PLL_SHARED1_DIV3, 123 DIV_PLL_SHARED1_DIV36, 124 DIV_PLL_SHARED1_DIV4, 125 DIV_PLL_SHARED1_DIV9, 126 GAT_CMU_CIS0_CLKGATE, 127 GAT_CMU_CIS1_CLKGATE, 128 GAT_CMU_CIS2_CLKGATE, 129 GAT_CMU_CPUCL_SWITCH_GATE, 130 GAT_CMU_FSYS0_SHARED0DIV4_GATE, 131 GAT_CMU_FSYS0_SHARED1DIV4_CLK, 132 GAT_CMU_FSYS0_SHARED1DIV4_GATE, 133 GAT_CMU_FSYS1_SHARED0DIV4_GATE, 134 GAT_CMU_FSYS1_SHARED1DIV4_GATE, 135 GAT_CMU_IMEM_ACLK_GATE, 136 GAT_CMU_IMEM_DMACLK_GATE, 137 GAT_CMU_IMEM_TCUCLK_GATE, 138 GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 139 GAT_CMU_PERIC_SHARED0DIVE4_GATE, 140 GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 141 GAT_CMU_PERIC_SHARED1DIVE4_GATE, 142 GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 143 GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 144 GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 145 GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 146}; 147 148static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = { 149 PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0), 150}; 151 152static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = { 153 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0), 154}; 155 156static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = { 157 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0), 158}; 159 160static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = { 161 PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0), 162}; 163 164static const struct samsung_pll_clock cmu_pll_clks[] __initconst = { 165 PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0, 166 PLL_CON0_PLL_SHARED0, pll_shared0_rate_table), 167 PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1, 168 PLL_CON0_PLL_SHARED1, pll_shared1_rate_table), 169 PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2, 170 PLL_CON0_PLL_SHARED2, pll_shared2_rate_table), 171 PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3, 172 PLL_CON0_PLL_SHARED3, pll_shared3_rate_table), 173}; 174 175/* List of parent clocks for Muxes in CMU_CMU */ 176PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" }; 177PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" }; 178PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" }; 179PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" }; 180PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 181PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 182PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 183PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" }; 184PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" }; 185PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" }; 186PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" }; 187 188static const struct samsung_mux_clock cmu_mux_clks[] __initconst = { 189 MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1), 190 MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1), 191 MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1), 192 MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1), 193 MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1), 194 MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1), 195 MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1), 196 MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p, 197 MUX_CMU_CPUCL_SWITCHMUX, 0, 1), 198 MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1), 199 MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1), 200 MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1), 201}; 202 203static const struct samsung_div_clock cmu_div_clks[] __initconst = { 204 DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4), 205 DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4), 206 DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4), 207 DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4), 208 DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4), 209 DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate", 210 DIV_CMU_FSYS0_SHARED0DIV4, 0, 4), 211 DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk", 212 DIV_CMU_FSYS0_SHARED1DIV3, 0, 4), 213 DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate", 214 DIV_CMU_FSYS0_SHARED1DIV4, 0, 4), 215 DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate", 216 DIV_CMU_FSYS1_SHARED0DIV4, 0, 4), 217 DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate", 218 DIV_CMU_FSYS1_SHARED0DIV8, 0, 4), 219 DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate", 220 DIV_CMU_IMEM_ACLK, 0, 4), 221 DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate", 222 DIV_CMU_IMEM_DMACLK, 0, 4), 223 DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate", 224 DIV_CMU_IMEM_TCUCLK, 0, 4), 225 DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20", 226 "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4), 227 DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk", 228 "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4), 229 DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36", 230 "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4), 231 DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk", 232 "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4), 233 DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux", 234 DIV_PLL_SHARED0_DIV2, 0, 4), 235 DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux", 236 DIV_PLL_SHARED0_DIV3, 0, 4), 237 DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2", 238 DIV_PLL_SHARED0_DIV4, 0, 4), 239 DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3", 240 DIV_PLL_SHARED0_DIV6, 0, 4), 241 DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux", 242 DIV_PLL_SHARED1_DIV3, 0, 4), 243 DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9", 244 DIV_PLL_SHARED1_DIV36, 0, 4), 245 DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux", 246 DIV_PLL_SHARED1_DIV4, 0, 4), 247 DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3", 248 DIV_PLL_SHARED1_DIV9, 0, 4), 249}; 250 251static const struct samsung_gate_clock cmu_gate_clks[] __initconst = { 252 GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21, 253 CLK_IGNORE_UNUSED, 0), 254 GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21, 255 CLK_IGNORE_UNUSED, 0), 256 GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21, 257 CLK_IGNORE_UNUSED, 0), 258 GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux", 259 GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0), 260 GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4", 261 GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 262 GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3", 263 GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0), 264 GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4", 265 GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 266 GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux", 267 GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 268 GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4", 269 GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 270 GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21, 271 CLK_IGNORE_UNUSED, 0), 272 GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21, 273 CLK_IGNORE_UNUSED, 0), 274 GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21, 275 CLK_IGNORE_UNUSED, 0), 276 GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3", 277 GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0), 278 GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4", 279 GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), 280 GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4", 281 GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0), 282 GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36", 283 GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), 284 GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", 285 GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 286 GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk", 287 GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 288 GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk", 289 GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0), 290 GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", 291 GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 292}; 293 294static const struct samsung_cmu_info cmu_cmu_info __initconst = { 295 .pll_clks = cmu_pll_clks, 296 .nr_pll_clks = ARRAY_SIZE(cmu_pll_clks), 297 .mux_clks = cmu_mux_clks, 298 .nr_mux_clks = ARRAY_SIZE(cmu_mux_clks), 299 .div_clks = cmu_div_clks, 300 .nr_div_clks = ARRAY_SIZE(cmu_div_clks), 301 .gate_clks = cmu_gate_clks, 302 .nr_gate_clks = ARRAY_SIZE(cmu_gate_clks), 303 .nr_clk_ids = CMU_NR_CLK, 304 .clk_regs = cmu_clk_regs, 305 .nr_clk_regs = ARRAY_SIZE(cmu_clk_regs), 306}; 307 308static void __init fsd_clk_cmu_init(struct device_node *np) 309{ 310 samsung_cmu_register_one(np, &cmu_cmu_info); 311} 312 313CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init); 314 315/* Register Offset definitions for CMU_PERIC (0x14010000) */ 316#define PLL_CON0_PERIC_DMACLK_MUX 0x100 317#define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120 318#define PLL_CON0_PERIC_PCLK_MUX 0x140 319#define PLL_CON0_PERIC_TBUCLK_MUX 0x160 320#define PLL_CON0_SPI_CLK 0x180 321#define PLL_CON0_SPI_PCLK 0x1a0 322#define PLL_CON0_UART_CLK 0x1c0 323#define PLL_CON0_UART_PCLK 0x1e0 324#define MUX_PERIC_EQOS_PHYRXCLK 0x1000 325#define DIV_EQOS_BUSCLK 0x1800 326#define DIV_PERIC_MCAN_CLK 0x1804 327#define DIV_RGMII_CLK 0x1808 328#define DIV_RII_CLK 0x180c 329#define DIV_RMII_CLK 0x1810 330#define DIV_SPI_CLK 0x1814 331#define DIV_UART_CLK 0x1818 332#define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000 333#define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004 334#define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008 335#define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c 336#define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010 337#define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014 338#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018 339#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c 340#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020 341#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024 342#define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028 343#define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c 344#define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030 345#define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034 346#define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038 347#define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c 348#define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040 349#define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044 350#define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048 351#define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c 352#define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050 353#define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054 354#define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058 355#define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c 356#define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060 357#define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064 358#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068 359#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c 360#define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070 361#define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074 362#define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078 363#define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c 364#define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080 365#define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084 366#define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088 367#define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c 368#define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090 369#define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094 370#define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098 371#define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c 372#define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0 373#define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4 374#define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8 375#define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac 376#define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0 377#define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4 378#define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8 379#define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc 380#define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0 381#define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4 382#define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8 383#define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc 384#define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0 385#define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4 386#define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8 387#define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc 388#define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0 389#define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4 390#define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8 391#define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec 392#define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0 393#define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4 394#define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8 395#define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc 396#define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100 397#define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104 398 399static const unsigned long peric_clk_regs[] __initconst = { 400 PLL_CON0_PERIC_DMACLK_MUX, 401 PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 402 PLL_CON0_PERIC_PCLK_MUX, 403 PLL_CON0_PERIC_TBUCLK_MUX, 404 PLL_CON0_SPI_CLK, 405 PLL_CON0_SPI_PCLK, 406 PLL_CON0_UART_CLK, 407 PLL_CON0_UART_PCLK, 408 MUX_PERIC_EQOS_PHYRXCLK, 409 DIV_EQOS_BUSCLK, 410 DIV_PERIC_MCAN_CLK, 411 DIV_RGMII_CLK, 412 DIV_RII_CLK, 413 DIV_RMII_CLK, 414 DIV_SPI_CLK, 415 DIV_UART_CLK, 416 GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 417 GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, 418 GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 419 GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 420 GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 421 GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 422 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 423 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 424 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 425 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 426 GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 427 GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 428 GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 429 GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 430 GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 431 GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 432 GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 433 GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 434 GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 435 GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 436 GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 437 GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 438 GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 439 GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 440 GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 441 GAT_GPIO_PERIC_IPCLKPORT_PCLK, 442 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 443 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 444 GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 445 GAT_PERIC_DMA0_IPCLKPORT_ACLK, 446 GAT_PERIC_DMA1_IPCLKPORT_ACLK, 447 GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 448 GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 449 GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 450 GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 451 GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 452 GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 453 GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 454 GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 455 GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 456 GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 457 GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 458 GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 459 GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 460 GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 461 GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 462 GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 463 GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 464 GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 465 GAT_PERIC_SMMU_IPCLKPORT_CCLK, 466 GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 467 GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 468 GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 469 GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 470 GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 471 GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 472 GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 473 GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 474 GAT_PERIC_TDM0_IPCLKPORT_PCLK, 475 GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 476 GAT_PERIC_TDM1_IPCLKPORT_PCLK, 477 GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 478 GAT_PERIC_UART0_IPCLKPORT_PCLK, 479 GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 480 GAT_PERIC_UART1_IPCLKPORT_PCLK, 481 GAT_SYSREG_PERI_IPCLKPORT_PCLK, 482}; 483 484static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = { 485 FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000), 486}; 487 488/* List of parent clocks for Muxes in CMU_PERIC */ 489PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" }; 490PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 491PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; 492PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" }; 493PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" }; 494PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; 495PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" }; 496PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; 497PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" }; 498 499static const struct samsung_mux_clock peric_mux_clks[] __initconst = { 500 MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1), 501 MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p, 502 PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1), 503 MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1), 504 MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1), 505 MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1), 506 MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1), 507 MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1), 508 MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1), 509 MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p, 510 MUX_PERIC_EQOS_PHYRXCLK, 0, 1), 511}; 512 513static const struct samsung_div_clock peric_div_clks[] __initconst = { 514 DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4), 515 DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4), 516 DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk", 517 DIV_RGMII_CLK, 0, 4), 518 DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4), 519 DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4), 520 DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6), 521 DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6), 522}; 523 524static const struct samsung_gate_clock peric_gate_clks[] __initconst = { 525 GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i", 526 "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), 527 GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, 528 21, CLK_IGNORE_UNUSED, 0), 529 GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll", 530 GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 531 GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk", 532 GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 533 GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21, 534 CLK_IGNORE_UNUSED, 0), 535 GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21, 536 CLK_IGNORE_UNUSED, 0), 537 GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk", 538 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 539 GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk", 540 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 541 GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk", 542 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 543 GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk", 544 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 545 GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk", 546 GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 547 GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk", 548 GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 549 GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk", 550 GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 551 GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk", 552 GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0), 553 GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk", 554 "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), 555 GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk", 556 GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 557 GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk", 558 "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), 559 GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk", 560 GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 561 GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk", 562 GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0), 563 GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i", 564 "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0), 565 GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i", 566 "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0), 567 GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i", 568 "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0), 569 GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i", 570 "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 571 GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk", 572 GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 573 GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk", 574 GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 575 GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk", 576 GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 577 GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk", 578 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0), 579 GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk", 580 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0), 581 GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk", 582 GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), 583 GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk", 584 GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 585 GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk", 586 GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 587 GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk", 588 GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 589 GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk", 590 GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 591 GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk", 592 GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 593 GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk", 594 GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 595 GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk", 596 GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 597 GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk", 598 GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 599 GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk", 600 GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 601 GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk", 602 GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 603 GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk", 604 GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 605 GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk", 606 GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 607 GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk", 608 GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 609 GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk", 610 GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 611 GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk", 612 GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 613 GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk", 614 GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 615 GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk", 616 GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 617 GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk", 618 GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 619 GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk", 620 GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), 621 GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk", 622 GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), 623 GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk", 624 GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 625 GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk", 626 GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0), 627 GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk", 628 GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 629 GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk", 630 GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), 631 GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk", 632 GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 633 GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk", 634 GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), 635 GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk", 636 GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 637 GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk", 638 GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), 639 GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk", 640 GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), 641 GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk", 642 GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 643 GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk", 644 GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), 645 GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk", 646 GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 647 GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk", 648 GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), 649 GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk", 650 GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 651 GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk", 652 GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), 653 GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk", 654 GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 655 GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk", 656 GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 657}; 658 659static const struct samsung_cmu_info peric_cmu_info __initconst = { 660 .mux_clks = peric_mux_clks, 661 .nr_mux_clks = ARRAY_SIZE(peric_mux_clks), 662 .div_clks = peric_div_clks, 663 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 664 .gate_clks = peric_gate_clks, 665 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 666 .fixed_clks = peric_fixed_clks, 667 .nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks), 668 .nr_clk_ids = PERIC_NR_CLK, 669 .clk_regs = peric_clk_regs, 670 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 671 .clk_name = "dout_cmu_pll_shared0_div4", 672}; 673 674/* Register Offset definitions for CMU_FSYS0 (0x15010000) */ 675#define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100 676#define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140 677#define PLL_CON0_EQOS_RGMII_125_MUX1 0x160 678#define DIV_CLK_UNIPRO 0x1800 679#define DIV_EQS_RGMII_CLK_125 0x1804 680#define DIV_PERIBUS_GRP 0x1808 681#define DIV_EQOS_RII_CLK2O5 0x180c 682#define DIV_EQOS_RMIICLK_25 0x1810 683#define DIV_PCIE_PHY_OSCCLK 0x1814 684#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004 685#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008 686#define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c 687#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010 688#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014 689#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018 690#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c 691#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020 692#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024 693#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028 694#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c 695#define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038 696#define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c 697#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040 698#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044 699#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048 700#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c 701#define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050 702#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054 703#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058 704#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c 705#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060 706#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064 707#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068 708#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c 709#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070 710#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074 711#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078 712#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c 713#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080 714#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084 715#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088 716#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c 717#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090 718#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094 719#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098 720#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c 721#define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0 722#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4 723#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8 724#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac 725#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0 726#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4 727#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8 728#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc 729#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0 730#define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4 731 732static const unsigned long fsys0_clk_regs[] __initconst = { 733 PLL_CON0_CLKCMU_FSYS0_UNIPRO, 734 PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 735 PLL_CON0_EQOS_RGMII_125_MUX1, 736 DIV_CLK_UNIPRO, 737 DIV_EQS_RGMII_CLK_125, 738 DIV_PERIBUS_GRP, 739 DIV_EQOS_RII_CLK2O5, 740 DIV_EQOS_RMIICLK_25, 741 DIV_PCIE_PHY_OSCCLK, 742 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 743 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 744 GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 745 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 746 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 747 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 748 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 749 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 750 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 751 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 752 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 753 GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 754 GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 755 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 756 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 757 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 758 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 759 GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 760 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 761 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 762 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 763 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 764 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 765 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 766 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 767 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 768 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 769 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 770 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 771 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, 772 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 773 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 774 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 775 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 776 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 777 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 778 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 779 GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 780 GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 781 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 782 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 783 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 784 GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 785 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 786 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 787 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 788 GAT_FSYS0_RII_CLK_DIVGATE, 789}; 790 791static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = { 792 FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000), 793 FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000), 794 FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000), 795}; 796 797/* List of parent clocks for Muxes in CMU_FSYS0 */ 798PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" }; 799PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" }; 800PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" }; 801 802static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { 803 MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p, 804 PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1), 805 MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p, 806 PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1), 807 MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p, 808 PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1), 809}; 810 811static const struct samsung_div_clock fsys0_div_clks[] __initconst = { 812 DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4), 813 DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1", 814 DIV_EQS_RGMII_CLK_125, 0, 4), 815 DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp", 816 "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4), 817 DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4), 818 DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1", 819 DIV_EQOS_RMIICLK_25, 0, 5), 820 DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1", 821 DIV_PCIE_PHY_OSCCLK, 0, 4), 822}; 823 824static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { 825 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i", 826 "pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21, 827 CLK_IGNORE_UNUSED, 0), 828 GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC, 829 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll", 830 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21, 831 CLK_IGNORE_UNUSED, 0), 832 GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", 833 GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 834 GATE(0, 835 "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo", 836 "xtal_clk_pcie_phy", 837 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21, 838 CLK_IGNORE_UNUSED, 0), 839 GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24", 840 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, 841 CLK_IGNORE_UNUSED, 0), 842 GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26", 843 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, 844 CLK_IGNORE_UNUSED, 0), 845 GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24", 846 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, 847 CLK_IGNORE_UNUSED, 0), 848 GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26", 849 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, 850 CLK_IGNORE_UNUSED, 0), 851 GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp", 852 GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0), 853 GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp", 854 GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 855 GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk", 856 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 857 GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp", 858 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), 859 GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp", 860 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 861 GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1", 862 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), 863 GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk", 864 GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 865 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i", 866 "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21, 867 CLK_IGNORE_UNUSED, 0), 868 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i", 869 "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21, 870 CLK_IGNORE_UNUSED, 0), 871 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i", 872 "dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21, 873 CLK_IGNORE_UNUSED, 0), 874 GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5", 875 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 876 GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25", 877 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 878 GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", 879 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 880 GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll", 881 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 882 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d", 883 "mout_fsys0_clk_fsys0_slavebusclk", 884 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21, 885 CLK_IGNORE_UNUSED, 0), 886 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1", 887 "mout_fsys0_eqos_rgmii_125_mux1", 888 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21, 889 CLK_IGNORE_UNUSED, 0), 890 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p", 891 "dout_fsys0_peribus_grp", 892 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21, 893 CLK_IGNORE_UNUSED, 0), 894 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s", 895 "mout_fsys0_clk_fsys0_slavebusclk", 896 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21, 897 CLK_IGNORE_UNUSED, 0), 898 GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk", 899 "dout_fsys0_peribus_grp", 900 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21, 901 CLK_IGNORE_UNUSED, 0), 902 GATE(0, 903 "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll", 904 "dout_fsys0_pcie_phy_oscclk", 905 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, 906 21, CLK_IGNORE_UNUSED, 0), 907 GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp", 908 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0), 909 GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll", 910 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0), 911 GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC, 912 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc", 913 "dout_fsys0_peribus_grp", 914 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21, 915 CLK_IGNORE_UNUSED, 0), 916 GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk", 917 "dout_fsys0_peribus_grp", 918 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21, 919 CLK_IGNORE_UNUSED, 0), 920 GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC, 921 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc", 922 "mout_fsys0_clk_fsys0_slavebusclk", 923 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21, 924 CLK_IGNORE_UNUSED, 0), 925 GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC, 926 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc", 927 "mout_fsys0_clk_fsys0_slavebusclk", 928 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21, 929 CLK_IGNORE_UNUSED, 0), 930 GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1", 931 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 932 GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk", 933 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0), 934 GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", 935 GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 936 GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", 937 GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), 938 GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp", 939 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 940 GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", 941 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), 942 GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", 943 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), 944 GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", 945 GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), 946 GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp", 947 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 948 GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", 949 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), 950 GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", 951 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), 952 GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE, 953 21, CLK_IGNORE_UNUSED, 0), 954 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i", 955 "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), 956}; 957 958static const struct samsung_cmu_info fsys0_cmu_info __initconst = { 959 .mux_clks = fsys0_mux_clks, 960 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 961 .div_clks = fsys0_div_clks, 962 .nr_div_clks = ARRAY_SIZE(fsys0_div_clks), 963 .gate_clks = fsys0_gate_clks, 964 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 965 .fixed_clks = fsys0_fixed_clks, 966 .nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks), 967 .nr_clk_ids = FSYS0_NR_CLK, 968 .clk_regs = fsys0_clk_regs, 969 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 970 .clk_name = "dout_cmu_fsys0_shared1div4", 971}; 972 973/* Register Offset definitions for CMU_FSYS1 (0x16810000) */ 974#define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100 975#define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180 976#define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800 977#define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804 978#define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000 979#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004 980#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008 981#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c 982#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c 983#define GAT_FSYS1_PHY0_OSCCLLK 0x2034 984#define GAT_FSYS1_PHY1_OSCCLK 0x2038 985#define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c 986#define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040 987#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048 988#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c 989#define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054 990#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c 991#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064 992#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c 993#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070 994#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074 995#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078 996#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c 997#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080 998#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084 999#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088 1000#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c 1001#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4 1002#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8 1003#define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4 1004#define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8 1005 1006static const unsigned long fsys1_clk_regs[] __initconst = { 1007 PLL_CON0_ACLK_FSYS1_BUSP_MUX, 1008 PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 1009 DIV_CLK_FSYS1_PHY0_OSCCLK, 1010 DIV_CLK_FSYS1_PHY1_OSCCLK, 1011 GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 1012 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 1013 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 1014 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 1015 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 1016 GAT_FSYS1_PHY0_OSCCLLK, 1017 GAT_FSYS1_PHY1_OSCCLK, 1018 GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 1019 GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 1020 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 1021 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 1022 GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 1023 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 1024 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 1025 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 1026 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 1027 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 1028 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 1029 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 1030 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 1031 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 1032 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 1033 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 1034 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 1035 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 1036 GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 1037 GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 1038}; 1039 1040static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = { 1041 FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000), 1042 FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000), 1043}; 1044 1045/* List of parent clocks for Muxes in CMU_FSYS1 */ 1046PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" }; 1047PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" }; 1048 1049static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { 1050 MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p, 1051 PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1), 1052 MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p, 1053 PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1), 1054}; 1055 1056static const struct samsung_div_clock fsys1_div_clks[] __initconst = { 1057 DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk", 1058 DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4), 1059 DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk", 1060 DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4), 1061}; 1062 1063static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { 1064 GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", 1065 GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1066 GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref", 1067 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0), 1068 GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux", 1069 GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0), 1070 GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux", 1071 GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 1072 GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux", 1073 GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1074 GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", 1075 GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1076 GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1077 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0), 1078 GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", 1079 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1080 GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", 1081 GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1082 GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0", 1083 "mout_fsys1_aclk_fsys1_busp_mux", 1084 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21, 1085 CLK_IGNORE_UNUSED, 0), 1086 GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0", 1087 "mout_fsys1_aclk_fsys1_busp_mux", 1088 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21, 1089 CLK_IGNORE_UNUSED, 0), 1090 GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk", 1091 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21, 1092 CLK_IGNORE_UNUSED, 0), 1093 GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1094 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1095 GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll", 1096 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0), 1097 GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1098 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1099 GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk", 1100 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21, 1101 CLK_IGNORE_UNUSED, 0), 1102 GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk", 1103 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21, 1104 CLK_IGNORE_UNUSED, 0), 1105 GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk", 1106 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21, 1107 CLK_IGNORE_UNUSED, 0), 1108 GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1109 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1110 GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk", 1111 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21, 1112 CLK_IGNORE_UNUSED, 0), 1113 GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk", 1114 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21, 1115 CLK_IGNORE_UNUSED, 0), 1116 GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1117 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1118 GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll", 1119 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), 1120 GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll", 1121 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), 1122 GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk", 1123 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0), 1124 GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", 1125 GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1126 GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", 1127 GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1128}; 1129 1130static const struct samsung_cmu_info fsys1_cmu_info __initconst = { 1131 .mux_clks = fsys1_mux_clks, 1132 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 1133 .div_clks = fsys1_div_clks, 1134 .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), 1135 .gate_clks = fsys1_gate_clks, 1136 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 1137 .fixed_clks = fsys1_fixed_clks, 1138 .nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks), 1139 .nr_clk_ids = FSYS1_NR_CLK, 1140 .clk_regs = fsys1_clk_regs, 1141 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 1142 .clk_name = "dout_cmu_fsys1_shared0div4", 1143}; 1144 1145/* Register Offset definitions for CMU_IMEM (0x10010000) */ 1146#define PLL_CON0_CLK_IMEM_ACLK 0x100 1147#define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120 1148#define PLL_CON0_CLK_IMEM_TCUCLK 0x140 1149#define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800 1150#define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000 1151#define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004 1152#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008 1153#define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c 1154#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010 1155#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014 1156#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018 1157#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c 1158#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020 1159#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024 1160#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028 1161#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c 1162#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030 1163#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034 1164#define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038 1165#define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c 1166#define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040 1167#define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044 1168#define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048 1169#define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c 1170#define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050 1171#define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054 1172#define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058 1173#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c 1174#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060 1175#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064 1176#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068 1177#define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c 1178#define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070 1179#define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074 1180#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078 1181#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c 1182#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080 1183#define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084 1184#define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088 1185#define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c 1186#define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090 1187#define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094 1188#define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098 1189#define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c 1190#define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0 1191#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4 1192#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8 1193#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac 1194#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0 1195#define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4 1196#define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8 1197#define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc 1198#define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0 1199#define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4 1200#define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8 1201#define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc 1202#define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0 1203#define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4 1204#define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8 1205#define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc 1206 1207static const unsigned long imem_clk_regs[] __initconst = { 1208 PLL_CON0_CLK_IMEM_ACLK, 1209 PLL_CON0_CLK_IMEM_INTMEMCLK, 1210 PLL_CON0_CLK_IMEM_TCUCLK, 1211 DIV_OSCCLK_IMEM_TMUTSCLK, 1212 GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 1213 GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 1214 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 1215 GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 1216 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 1217 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 1218 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 1219 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 1220 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 1221 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 1222 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 1223 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 1224 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 1225 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 1226 GAT_IMEM_WDT0_IPCLKPORT_CLK, 1227 GAT_IMEM_WDT1_IPCLKPORT_CLK, 1228 GAT_IMEM_WDT2_IPCLKPORT_CLK, 1229 GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 1230 GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 1231 GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 1232 GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 1233 GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 1234 GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 1235 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 1236 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 1237 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 1238 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 1239 GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 1240 GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 1241 GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 1242 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 1243 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 1244 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 1245 GAT_IMEM_DMA0_IPCLKPORT_ACLK, 1246 GAT_IMEM_DMA1_IPCLKPORT_ACLK, 1247 GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 1248 GAT_IMEM_GIC_IPCLKPORT_CLK, 1249 GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 1250 GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 1251 GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 1252 GAT_IMEM_MCT_IPCLKPORT_PCLK, 1253 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 1254 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 1255 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 1256 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 1257 GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 1258 GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 1259 GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 1260 GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 1261 GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 1262 GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 1263 GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 1264 GAT_IMEM_TCU_IPCLKPORT_ACLK, 1265 GAT_IMEM_WDT0_IPCLKPORT_PCLK, 1266 GAT_IMEM_WDT1_IPCLKPORT_PCLK, 1267 GAT_IMEM_WDT2_IPCLKPORT_PCLK, 1268}; 1269 1270PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" }; 1271PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" }; 1272PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" }; 1273 1274static const struct samsung_mux_clock imem_mux_clks[] __initconst = { 1275 MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p, 1276 PLL_CON0_CLK_IMEM_TCUCLK, 4, 1), 1277 MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1), 1278 MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p, 1279 PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1), 1280}; 1281 1282static const struct samsung_div_clock imem_div_clks[] __initconst = { 1283 DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4), 1284}; 1285 1286static const struct samsung_gate_clock imem_gate_clks[] __initconst = { 1287 GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1288 GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1289 GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll", 1290 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 1291 GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll", 1292 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1293 GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll", 1294 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1295 GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll", 1296 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1297 GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll", 1298 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1299 GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll", 1300 GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0), 1301 GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll", 1302 GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1303 GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll", 1304 GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1305 GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll", 1306 GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1307 GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts", 1308 "dout_imem_oscclk_imem_tmutsclk", 1309 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1310 GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts", 1311 "dout_imem_oscclk_imem_tmutsclk", 1312 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1313 GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts", 1314 "dout_imem_oscclk_imem_tmutsclk", 1315 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1316 GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts", 1317 "dout_imem_oscclk_imem_tmutsclk", 1318 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1319 GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts", 1320 "dout_imem_oscclk_imem_tmutsclk", 1321 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1322 GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", 1323 GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), 1324 GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", 1325 GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), 1326 GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", 1327 GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), 1328 GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", 1329 GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), 1330 GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", 1331 GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), 1332 GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", 1333 GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), 1334 GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", 1335 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 1336 GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk", 1337 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 1338 GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", 1339 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 1340 GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk", 1341 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 1342 GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk", 1343 GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1344 GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk", 1345 GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1346 GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk", 1347 GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1348 GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk", 1349 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1350 GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk", 1351 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), 1352 GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk", 1353 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), 1354 GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1355 GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), 1356 GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1357 GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), 1358 GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk", 1359 GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1360 GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk", 1361 GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1362 GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk", 1363 GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1364 GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1365 GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1366 GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1367 GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1368 GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1369 GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1370 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d", 1371 "mout_imem_clk_imem_tcuclk", 1372 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0), 1373 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu", 1374 "mout_imem_clk_imem_tcuclk", 1375 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21, 1376 CLK_IGNORE_UNUSED, 0), 1377 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk", 1378 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0), 1379 GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1380 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1381 GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk", 1382 GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1383 GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll", 1384 GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1385 GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk", 1386 GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1387 GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk", 1388 GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1389 GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1390 GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1391 GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1392 GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1393 GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll", 1394 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1395 GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1396 GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1397 GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1398 GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1399 GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1400 GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1401 GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1402 GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1403 GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1404 GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1405 GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1406 GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1407}; 1408 1409static const struct samsung_cmu_info imem_cmu_info __initconst = { 1410 .mux_clks = imem_mux_clks, 1411 .nr_mux_clks = ARRAY_SIZE(imem_mux_clks), 1412 .div_clks = imem_div_clks, 1413 .nr_div_clks = ARRAY_SIZE(imem_div_clks), 1414 .gate_clks = imem_gate_clks, 1415 .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), 1416 .nr_clk_ids = IMEM_NR_CLK, 1417 .clk_regs = imem_clk_regs, 1418 .nr_clk_regs = ARRAY_SIZE(imem_clk_regs), 1419}; 1420 1421static void __init fsd_clk_imem_init(struct device_node *np) 1422{ 1423 samsung_cmu_register_one(np, &imem_cmu_info); 1424} 1425 1426CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init); 1427 1428/* Register Offset definitions for CMU_MFC (0x12810000) */ 1429#define PLL_LOCKTIME_PLL_MFC 0x0 1430#define PLL_CON0_PLL_MFC 0x100 1431#define MUX_MFC_BUSD 0x1000 1432#define MUX_MFC_BUSP 0x1008 1433#define DIV_MFC_BUSD_DIV4 0x1800 1434#define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000 1435#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004 1436#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008 1437#define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c 1438#define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010 1439#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018 1440#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c 1441#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028 1442#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c 1443#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030 1444#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034 1445#define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038 1446#define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c 1447#define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040 1448#define GAT_MFC_BUSD_DIV4_GATE 0x2044 1449#define GAT_MFC_BUSD_GATE 0x2048 1450 1451static const unsigned long mfc_clk_regs[] __initconst = { 1452 PLL_LOCKTIME_PLL_MFC, 1453 PLL_CON0_PLL_MFC, 1454 MUX_MFC_BUSD, 1455 MUX_MFC_BUSP, 1456 DIV_MFC_BUSD_DIV4, 1457 GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 1458 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 1459 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 1460 GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 1461 GAT_MFC_MFC_IPCLKPORT_ACLK, 1462 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 1463 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 1464 GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 1465 GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 1466 GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 1467 GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 1468 GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 1469 GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 1470 GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 1471 GAT_MFC_BUSD_DIV4_GATE, 1472 GAT_MFC_BUSD_GATE, 1473}; 1474 1475static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = { 1476 PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0), 1477}; 1478 1479static const struct samsung_pll_clock mfc_pll_clks[] __initconst = { 1480 PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll", 1481 PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table), 1482}; 1483 1484PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" }; 1485PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" }; 1486PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" }; 1487 1488static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 1489 MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1), 1490 MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1), 1491 MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1), 1492}; 1493 1494static const struct samsung_div_clock mfc_div_clks[] __initconst = { 1495 DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4), 1496}; 1497 1498static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 1499 GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp", 1500 GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1501 GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd", 1502 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 1503 GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp", 1504 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 1505 GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp", 1506 GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1507 GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd", 1508 GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1509 GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd", 1510 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0), 1511 GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp", 1512 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0), 1513 GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd", 1514 GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1515 GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp", 1516 GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1517 GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd", 1518 GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1519 GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp", 1520 GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1521 GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp", 1522 GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1523 GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd", 1524 GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1525 GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd", 1526 GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1527 GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll", 1528 GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 1529 GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0), 1530}; 1531 1532static const struct samsung_cmu_info mfc_cmu_info __initconst = { 1533 .pll_clks = mfc_pll_clks, 1534 .nr_pll_clks = ARRAY_SIZE(mfc_pll_clks), 1535 .mux_clks = mfc_mux_clks, 1536 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 1537 .div_clks = mfc_div_clks, 1538 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 1539 .gate_clks = mfc_gate_clks, 1540 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 1541 .nr_clk_ids = MFC_NR_CLK, 1542 .clk_regs = mfc_clk_regs, 1543 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 1544}; 1545 1546/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */ 1547#define PLL_LOCKTIME_PLL_CAM_CSI 0x0 1548#define PLL_CON0_PLL_CAM_CSI 0x100 1549#define DIV_CAM_CSI0_ACLK 0x1800 1550#define DIV_CAM_CSI1_ACLK 0x1804 1551#define DIV_CAM_CSI2_ACLK 0x1808 1552#define DIV_CAM_CSI_BUSD 0x180c 1553#define DIV_CAM_CSI_BUSP 0x1810 1554#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000 1555#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004 1556#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008 1557#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c 1558#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010 1559#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014 1560#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018 1561#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c 1562#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020 1563#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024 1564#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028 1565#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c 1566#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030 1567#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034 1568#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038 1569#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c 1570#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040 1571#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044 1572#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048 1573#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c 1574#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050 1575#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054 1576#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058 1577#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c 1578#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060 1579#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064 1580#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068 1581#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c 1582#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070 1583#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074 1584#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078 1585#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c 1586#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080 1587#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084 1588#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088 1589 1590static const unsigned long cam_csi_clk_regs[] __initconst = { 1591 PLL_LOCKTIME_PLL_CAM_CSI, 1592 PLL_CON0_PLL_CAM_CSI, 1593 DIV_CAM_CSI0_ACLK, 1594 DIV_CAM_CSI1_ACLK, 1595 DIV_CAM_CSI2_ACLK, 1596 DIV_CAM_CSI_BUSD, 1597 DIV_CAM_CSI_BUSP, 1598 GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 1599 GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 1600 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 1601 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 1602 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 1603 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 1604 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 1605 GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 1606 GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 1607 GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 1608 GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 1609 GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 1610 GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 1611 GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 1612 GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 1613 GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 1614 GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 1615 GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 1616 GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 1617 GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 1618 GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 1619 GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 1620 GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 1621 GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 1622 GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 1623 GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 1624 GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 1625 GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 1626 GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 1627 GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 1628 GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 1629 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 1630 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 1631 GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 1632 GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 1633}; 1634 1635static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = { 1636 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0), 1637}; 1638 1639static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = { 1640 PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll", 1641 PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table), 1642}; 1643 1644PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" }; 1645 1646static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = { 1647 MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1), 1648}; 1649 1650static const struct samsung_div_clock cam_csi_div_clks[] __initconst = { 1651 DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4), 1652 DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4), 1653 DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4), 1654 DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4), 1655 DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4), 1656}; 1657 1658static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = { 1659 GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", 1660 GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1661 GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp", 1662 GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1663 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk", 1664 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0), 1665 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk", 1666 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0), 1667 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk", 1668 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0), 1669 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd", 1670 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21, 1671 CLK_IGNORE_UNUSED, 0), 1672 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd", 1673 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0), 1674 GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1675 GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1676 GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp", 1677 GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1678 GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1679 GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1680 GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp", 1681 GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1682 GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1683 GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1684 GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp", 1685 GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1686 GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1687 GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1688 GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp", 1689 GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1690 GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1691 GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1692 GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp", 1693 GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1694 GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1695 GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1696 GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp", 1697 GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1698 GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1699 GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1700 GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp", 1701 GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1702 GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1703 GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1704 GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp", 1705 GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1706 GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1707 GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1708 GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp", 1709 GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1710 GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1711 GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1712 GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp", 1713 GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1714 GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1715 GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1716 GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp", 1717 GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1718 GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1719 GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1720 GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp", 1721 GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1722 GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d", 1723 "dout_cam_csi_busd", 1724 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21, 1725 CLK_IGNORE_UNUSED, 0), 1726 GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p", 1727 "dout_cam_csi_busp", 1728 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21, 1729 CLK_IGNORE_UNUSED, 0), 1730 GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", 1731 GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1732 GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd", 1733 GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1734}; 1735 1736static const struct samsung_cmu_info cam_csi_cmu_info __initconst = { 1737 .pll_clks = cam_csi_pll_clks, 1738 .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks), 1739 .mux_clks = cam_csi_mux_clks, 1740 .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks), 1741 .div_clks = cam_csi_div_clks, 1742 .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks), 1743 .gate_clks = cam_csi_gate_clks, 1744 .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks), 1745 .nr_clk_ids = CAM_CSI_NR_CLK, 1746 .clk_regs = cam_csi_clk_regs, 1747 .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs), 1748}; 1749 1750/** 1751 * fsd_cmu_probe - Probe function for FSD platform clocks 1752 * @pdev: Pointer to platform device 1753 * 1754 * Configure clock hierarchy for clock domains of FSD platform 1755 */ 1756static int __init fsd_cmu_probe(struct platform_device *pdev) 1757{ 1758 const struct samsung_cmu_info *info; 1759 struct device *dev = &pdev->dev; 1760 1761 info = of_device_get_match_data(dev); 1762 exynos_arm64_register_cmu(dev, dev->of_node, info); 1763 1764 return 0; 1765} 1766 1767/* CMUs which belong to Power Domains and need runtime PM to be implemented */ 1768static const struct of_device_id fsd_cmu_of_match[] = { 1769 { 1770 .compatible = "tesla,fsd-clock-peric", 1771 .data = &peric_cmu_info, 1772 }, { 1773 .compatible = "tesla,fsd-clock-fsys0", 1774 .data = &fsys0_cmu_info, 1775 }, { 1776 .compatible = "tesla,fsd-clock-fsys1", 1777 .data = &fsys1_cmu_info, 1778 }, { 1779 .compatible = "tesla,fsd-clock-mfc", 1780 .data = &mfc_cmu_info, 1781 }, { 1782 .compatible = "tesla,fsd-clock-cam_csi", 1783 .data = &cam_csi_cmu_info, 1784 }, { 1785 }, 1786}; 1787 1788static struct platform_driver fsd_cmu_driver __refdata = { 1789 .driver = { 1790 .name = "fsd-cmu", 1791 .of_match_table = fsd_cmu_of_match, 1792 .suppress_bind_attrs = true, 1793 }, 1794 .probe = fsd_cmu_probe, 1795}; 1796 1797static int __init fsd_cmu_init(void) 1798{ 1799 return platform_driver_register(&fsd_cmu_driver); 1800} 1801core_initcall(fsd_cmu_init); 1802