1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4 * Author: Chanwoo Choi <cw00.choi@samsung.com> 5 * 6 * Common Clock Framework support for Exynos5433 SoC. 7 */ 8 9#include <linux/clk.h> 10#include <linux/clk-provider.h> 11#include <linux/of.h> 12#include <linux/of_address.h> 13#include <linux/platform_device.h> 14#include <linux/pm_runtime.h> 15#include <linux/slab.h> 16 17#include <dt-bindings/clock/exynos5433.h> 18 19#include "clk.h" 20#include "clk-cpu.h" 21#include "clk-exynos-arm64.h" 22#include "clk-pll.h" 23 24/* NOTE: Must be equal to the last clock ID increased by one */ 25#define CLKS_NR_TOP (CLK_SCLK_HDMI_SPDIF_DISP + 1) 26#define CLKS_NR_CPIF (CLK_SCLK_UFS_MPHY + 1) 27#define CLKS_NR_MIF (CLK_SCLK_BUS_PLL_ATLAS + 1) 28#define CLKS_NR_PERIC (CLK_DIV_SCLK_SC_IN + 1) 29#define CLKS_NR_PERIS (CLK_SCLK_OTP_CON + 1) 30#define CLKS_NR_FSYS (CLK_PCIE + 1) 31#define CLKS_NR_G2D (CLK_PCLK_SMMU_G2D + 1) 32#define CLKS_NR_DISP (CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1) 33#define CLKS_NR_AUD (CLK_SCLK_AUD_I2S + 1) 34#define CLKS_NR_BUSX (CLK_ACLK_BUS2RTND_400 + 1) 35#define CLKS_NR_G3D (CLK_SCLK_HPM_G3D + 1) 36#define CLKS_NR_GSCL (CLK_PCLK_SMMU_GSCL2 + 1) 37#define CLKS_NR_APOLLO (CLK_SCLK_APOLLO + 1) 38#define CLKS_NR_ATLAS (CLK_SCLK_ATLAS + 1) 39#define CLKS_NR_MSCL (CLK_SCLK_JPEG + 1) 40#define CLKS_NR_MFC (CLK_PCLK_SMMU_MFC_0 + 1) 41#define CLKS_NR_HEVC (CLK_PCLK_SMMU_HEVC_0 + 1) 42#define CLKS_NR_ISP (CLK_SCLK_PIXELASYNCM_ISPC + 1) 43#define CLKS_NR_CAM0 (CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1) 44#define CLKS_NR_CAM1 (CLK_SCLK_ISP_CA5 + 1) 45#define CLKS_NR_IMEM (CLK_PCLK_SLIMSSS + 1) 46 47/* 48 * Register offset definitions for CMU_TOP 49 */ 50#define ISP_PLL_LOCK 0x0000 51#define AUD_PLL_LOCK 0x0004 52#define ISP_PLL_CON0 0x0100 53#define ISP_PLL_CON1 0x0104 54#define ISP_PLL_FREQ_DET 0x0108 55#define AUD_PLL_CON0 0x0110 56#define AUD_PLL_CON1 0x0114 57#define AUD_PLL_CON2 0x0118 58#define AUD_PLL_FREQ_DET 0x011c 59#define MUX_SEL_TOP0 0x0200 60#define MUX_SEL_TOP1 0x0204 61#define MUX_SEL_TOP2 0x0208 62#define MUX_SEL_TOP3 0x020c 63#define MUX_SEL_TOP4 0x0210 64#define MUX_SEL_TOP_MSCL 0x0220 65#define MUX_SEL_TOP_CAM1 0x0224 66#define MUX_SEL_TOP_DISP 0x0228 67#define MUX_SEL_TOP_FSYS0 0x0230 68#define MUX_SEL_TOP_FSYS1 0x0234 69#define MUX_SEL_TOP_PERIC0 0x0238 70#define MUX_SEL_TOP_PERIC1 0x023c 71#define MUX_ENABLE_TOP0 0x0300 72#define MUX_ENABLE_TOP1 0x0304 73#define MUX_ENABLE_TOP2 0x0308 74#define MUX_ENABLE_TOP3 0x030c 75#define MUX_ENABLE_TOP4 0x0310 76#define MUX_ENABLE_TOP_MSCL 0x0320 77#define MUX_ENABLE_TOP_CAM1 0x0324 78#define MUX_ENABLE_TOP_DISP 0x0328 79#define MUX_ENABLE_TOP_FSYS0 0x0330 80#define MUX_ENABLE_TOP_FSYS1 0x0334 81#define MUX_ENABLE_TOP_PERIC0 0x0338 82#define MUX_ENABLE_TOP_PERIC1 0x033c 83#define MUX_STAT_TOP0 0x0400 84#define MUX_STAT_TOP1 0x0404 85#define MUX_STAT_TOP2 0x0408 86#define MUX_STAT_TOP3 0x040c 87#define MUX_STAT_TOP4 0x0410 88#define MUX_STAT_TOP_MSCL 0x0420 89#define MUX_STAT_TOP_CAM1 0x0424 90#define MUX_STAT_TOP_FSYS0 0x0430 91#define MUX_STAT_TOP_FSYS1 0x0434 92#define MUX_STAT_TOP_PERIC0 0x0438 93#define MUX_STAT_TOP_PERIC1 0x043c 94#define DIV_TOP0 0x0600 95#define DIV_TOP1 0x0604 96#define DIV_TOP2 0x0608 97#define DIV_TOP3 0x060c 98#define DIV_TOP4 0x0610 99#define DIV_TOP_MSCL 0x0618 100#define DIV_TOP_CAM10 0x061c 101#define DIV_TOP_CAM11 0x0620 102#define DIV_TOP_FSYS0 0x062c 103#define DIV_TOP_FSYS1 0x0630 104#define DIV_TOP_FSYS2 0x0634 105#define DIV_TOP_PERIC0 0x0638 106#define DIV_TOP_PERIC1 0x063c 107#define DIV_TOP_PERIC2 0x0640 108#define DIV_TOP_PERIC3 0x0644 109#define DIV_TOP_PERIC4 0x0648 110#define DIV_TOP_PLL_FREQ_DET 0x064c 111#define DIV_STAT_TOP0 0x0700 112#define DIV_STAT_TOP1 0x0704 113#define DIV_STAT_TOP2 0x0708 114#define DIV_STAT_TOP3 0x070c 115#define DIV_STAT_TOP4 0x0710 116#define DIV_STAT_TOP_MSCL 0x0718 117#define DIV_STAT_TOP_CAM10 0x071c 118#define DIV_STAT_TOP_CAM11 0x0720 119#define DIV_STAT_TOP_FSYS0 0x072c 120#define DIV_STAT_TOP_FSYS1 0x0730 121#define DIV_STAT_TOP_FSYS2 0x0734 122#define DIV_STAT_TOP_PERIC0 0x0738 123#define DIV_STAT_TOP_PERIC1 0x073c 124#define DIV_STAT_TOP_PERIC2 0x0740 125#define DIV_STAT_TOP_PERIC3 0x0744 126#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c 127#define ENABLE_ACLK_TOP 0x0800 128#define ENABLE_SCLK_TOP 0x0a00 129#define ENABLE_SCLK_TOP_MSCL 0x0a04 130#define ENABLE_SCLK_TOP_CAM1 0x0a08 131#define ENABLE_SCLK_TOP_DISP 0x0a0c 132#define ENABLE_SCLK_TOP_FSYS 0x0a10 133#define ENABLE_SCLK_TOP_PERIC 0x0a14 134#define ENABLE_IP_TOP 0x0b00 135#define ENABLE_CMU_TOP 0x0c00 136#define ENABLE_CMU_TOP_DIV_STAT 0x0c04 137 138static const unsigned long top_clk_regs[] __initconst = { 139 ISP_PLL_LOCK, 140 AUD_PLL_LOCK, 141 ISP_PLL_CON0, 142 ISP_PLL_CON1, 143 ISP_PLL_FREQ_DET, 144 AUD_PLL_CON0, 145 AUD_PLL_CON1, 146 AUD_PLL_CON2, 147 AUD_PLL_FREQ_DET, 148 MUX_SEL_TOP0, 149 MUX_SEL_TOP1, 150 MUX_SEL_TOP2, 151 MUX_SEL_TOP3, 152 MUX_SEL_TOP4, 153 MUX_SEL_TOP_MSCL, 154 MUX_SEL_TOP_CAM1, 155 MUX_SEL_TOP_DISP, 156 MUX_SEL_TOP_FSYS0, 157 MUX_SEL_TOP_FSYS1, 158 MUX_SEL_TOP_PERIC0, 159 MUX_SEL_TOP_PERIC1, 160 MUX_ENABLE_TOP0, 161 MUX_ENABLE_TOP1, 162 MUX_ENABLE_TOP2, 163 MUX_ENABLE_TOP3, 164 MUX_ENABLE_TOP4, 165 MUX_ENABLE_TOP_MSCL, 166 MUX_ENABLE_TOP_CAM1, 167 MUX_ENABLE_TOP_DISP, 168 MUX_ENABLE_TOP_FSYS0, 169 MUX_ENABLE_TOP_FSYS1, 170 MUX_ENABLE_TOP_PERIC0, 171 MUX_ENABLE_TOP_PERIC1, 172 DIV_TOP0, 173 DIV_TOP1, 174 DIV_TOP2, 175 DIV_TOP3, 176 DIV_TOP4, 177 DIV_TOP_MSCL, 178 DIV_TOP_CAM10, 179 DIV_TOP_CAM11, 180 DIV_TOP_FSYS0, 181 DIV_TOP_FSYS1, 182 DIV_TOP_FSYS2, 183 DIV_TOP_PERIC0, 184 DIV_TOP_PERIC1, 185 DIV_TOP_PERIC2, 186 DIV_TOP_PERIC3, 187 DIV_TOP_PERIC4, 188 DIV_TOP_PLL_FREQ_DET, 189 ENABLE_ACLK_TOP, 190 ENABLE_SCLK_TOP, 191 ENABLE_SCLK_TOP_MSCL, 192 ENABLE_SCLK_TOP_CAM1, 193 ENABLE_SCLK_TOP_DISP, 194 ENABLE_SCLK_TOP_FSYS, 195 ENABLE_SCLK_TOP_PERIC, 196 ENABLE_IP_TOP, 197 ENABLE_CMU_TOP, 198 ENABLE_CMU_TOP_DIV_STAT, 199}; 200 201static const struct samsung_clk_reg_dump top_suspend_regs[] = { 202 /* force all aclk clocks enabled */ 203 { ENABLE_ACLK_TOP, 0x67ecffed }, 204 /* force all sclk_uart clocks enabled */ 205 { ENABLE_SCLK_TOP_PERIC, 0x38 }, 206 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ 207 { ISP_PLL_CON0, 0x85cc0502 }, 208 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ 209 { AUD_PLL_CON0, 0x84830202 }, 210}; 211 212/* list of all parent clock list */ 213PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; 214PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; 215PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", }; 216PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", }; 217PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", }; 218PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", }; 219PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", }; 220PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", }; 221 222PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",}; 223PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",}; 224PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", 225 "mout_mfc_pll_user", }; 226PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", }; 227 228PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b", 229 "mout_mphy_pll_user", }; 230PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a", 231 "mout_bus_pll_user", }; 232PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", }; 233 234PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user", 235 "mout_mphy_pll_user", }; 236PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a", 237 "mout_mphy_pll_user", }; 238PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a", 239 "mout_mphy_pll_user", }; 240 241PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",}; 242PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", }; 243 244PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",}; 245PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",}; 246PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", }; 247PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",}; 248PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", }; 249 250PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1", 251 "oscclk", "ioclk_spdif_extclk", }; 252PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk", 253 "mout_aud_pll_user_t",}; 254PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", 255 "mout_aud_pll_user_t",}; 256 257PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; 258 259static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { 260 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), 261}; 262 263static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = { 264 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 265 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), 266 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), 267 /* Xi2s1SDI input clock for SPDIF */ 268 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000), 269 /* XspiCLK[4:0] input clock for SPI */ 270 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000), 271 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000), 272 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000), 273 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000), 274 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000), 275 /* Xi2s1SCLK input clock for I2S1_BCLK */ 276 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), 277}; 278 279static const struct samsung_mux_clock top_mux_clks[] __initconst = { 280 /* MUX_SEL_TOP0 */ 281 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 282 4, 1), 283 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0, 284 0, 1), 285 286 /* MUX_SEL_TOP1 */ 287 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t", 288 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1), 289 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p, 290 MUX_SEL_TOP1, 8, 1), 291 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p, 292 MUX_SEL_TOP1, 4, 1), 293 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p, 294 MUX_SEL_TOP1, 0, 1), 295 296 /* MUX_SEL_TOP2 */ 297 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400", 298 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1), 299 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333", 300 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1), 301 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b", 302 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1), 303 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a", 304 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1), 305 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400", 306 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1), 307 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400", 308 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1), 309 310 /* MUX_SEL_TOP3 */ 311 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400", 312 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1), 313 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b", 314 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1), 315 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a", 316 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1), 317 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", 318 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1), 319 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b", 320 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1), 321 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a", 322 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1), 323 324 /* MUX_SEL_TOP4 */ 325 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c", 326 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1), 327 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b", 328 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1), 329 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a", 330 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1), 331 332 /* MUX_SEL_TOP_MSCL */ 333 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p, 334 MUX_SEL_TOP_MSCL, 8, 1), 335 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p, 336 MUX_SEL_TOP_MSCL, 4, 1), 337 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p, 338 MUX_SEL_TOP_MSCL, 0, 1), 339 340 /* MUX_SEL_TOP_CAM1 */ 341 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2", 342 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1), 343 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1", 344 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1), 345 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0", 346 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1), 347 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart", 348 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1), 349 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1", 350 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1), 351 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0", 352 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1), 353 354 /* MUX_SEL_TOP_FSYS0 */ 355 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p, 356 MUX_SEL_TOP_FSYS0, 28, 1), 357 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p, 358 MUX_SEL_TOP_FSYS0, 24, 1), 359 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p, 360 MUX_SEL_TOP_FSYS0, 20, 1), 361 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p, 362 MUX_SEL_TOP_FSYS0, 16, 1), 363 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p, 364 MUX_SEL_TOP_FSYS0, 12, 1), 365 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p, 366 MUX_SEL_TOP_FSYS0, 8, 1), 367 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p, 368 MUX_SEL_TOP_FSYS0, 4, 1), 369 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p, 370 MUX_SEL_TOP_FSYS0, 0, 1), 371 372 /* MUX_SEL_TOP_FSYS1 */ 373 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p, 374 MUX_SEL_TOP_FSYS1, 12, 1), 375 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro", 376 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1), 377 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30", 378 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1), 379 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30", 380 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1), 381 382 /* MUX_SEL_TOP_PERIC0 */ 383 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p, 384 MUX_SEL_TOP_PERIC0, 28, 1), 385 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p, 386 MUX_SEL_TOP_PERIC0, 24, 1), 387 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p, 388 MUX_SEL_TOP_PERIC0, 20, 1), 389 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p, 390 MUX_SEL_TOP_PERIC0, 16, 1), 391 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p, 392 MUX_SEL_TOP_PERIC0, 12, 1), 393 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p, 394 MUX_SEL_TOP_PERIC0, 8, 1), 395 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p, 396 MUX_SEL_TOP_PERIC0, 4, 1), 397 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p, 398 MUX_SEL_TOP_PERIC0, 0, 1), 399 400 /* MUX_SEL_TOP_PERIC1 */ 401 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p, 402 MUX_SEL_TOP_PERIC1, 16, 1), 403 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, 404 MUX_SEL_TOP_PERIC1, 12, 2), 405 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p, 406 MUX_SEL_TOP_PERIC1, 4, 2), 407 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p, 408 MUX_SEL_TOP_PERIC1, 0, 2), 409 410 /* MUX_SEL_TOP_DISP */ 411 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", 412 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), 413}; 414 415static const struct samsung_div_clock top_div_clks[] __initconst = { 416 /* DIV_TOP0 */ 417 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", 418 DIV_TOP0, 28, 3), 419 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user", 420 DIV_TOP0, 24, 3), 421 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b", 422 DIV_TOP0, 20, 3), 423 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user", 424 DIV_TOP0, 16, 3), 425 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user", 426 DIV_TOP0, 12, 3), 427 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll", 428 DIV_TOP0, 8, 3), 429 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400", 430 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4), 431 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400", 432 "mout_aclk_isp_400", DIV_TOP0, 0, 4), 433 434 /* DIV_TOP1 */ 435 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", 436 DIV_TOP1, 28, 3), 437 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333", 438 DIV_TOP1, 24, 3), 439 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400", 440 DIV_TOP1, 20, 3), 441 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c", 442 DIV_TOP1, 12, 3), 443 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user", 444 DIV_TOP1, 8, 3), 445 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b", 446 DIV_TOP1, 0, 3), 447 448 /* DIV_TOP2 */ 449 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b", 450 DIV_TOP2, 4, 3), 451 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", 452 DIV_TOP2, 0, 3), 453 454 /* DIV_TOP3 */ 455 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", 456 "mout_bus_pll_user", DIV_TOP3, 24, 3), 457 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200", 458 "mout_bus_pll_user", DIV_TOP3, 20, 3), 459 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266", 460 "mout_bus_pll_user", DIV_TOP3, 16, 3), 461 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b", 462 "div_aclk_peric_66_a", DIV_TOP3, 12, 3), 463 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a", 464 "mout_bus_pll_user", DIV_TOP3, 8, 3), 465 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b", 466 "div_aclk_peris_66_a", DIV_TOP3, 4, 3), 467 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a", 468 "mout_bus_pll_user", DIV_TOP3, 0, 3), 469 470 /* DIV_TOP4 */ 471 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user", 472 DIV_TOP4, 8, 3), 473 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400", 474 DIV_TOP4, 4, 3), 475 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user", 476 DIV_TOP4, 0, 3), 477 478 /* DIV_TOP_MSCL */ 479 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c", 480 DIV_TOP_MSCL, 0, 4), 481 482 /* DIV_TOP_CAM10 */ 483 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart", 484 DIV_TOP_CAM10, 24, 5), 485 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b", 486 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8), 487 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a", 488 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4), 489 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b", 490 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8), 491 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a", 492 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4), 493 494 /* DIV_TOP_CAM11 */ 495 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b", 496 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4), 497 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a", 498 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4), 499 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b", 500 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4), 501 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a", 502 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4), 503 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b", 504 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4), 505 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a", 506 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4), 507 508 /* DIV_TOP_FSYS0 */ 509 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", 510 DIV_TOP_FSYS0, 16, 8), 511 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b", 512 DIV_TOP_FSYS0, 12, 4), 513 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a", 514 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0), 515 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d", 516 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0), 517 518 /* DIV_TOP_FSYS1 */ 519 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a", 520 DIV_TOP_FSYS1, 4, 8), 521 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", 522 DIV_TOP_FSYS1, 0, 4), 523 524 /* DIV_TOP_FSYS2 */ 525 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100", 526 DIV_TOP_FSYS2, 12, 3), 527 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30", 528 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4), 529 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro", 530 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4), 531 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30", 532 DIV_TOP_FSYS2, 0, 4), 533 534 /* DIV_TOP_PERIC0 */ 535 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", 536 DIV_TOP_PERIC0, 16, 8), 537 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1", 538 DIV_TOP_PERIC0, 12, 4), 539 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a", 540 DIV_TOP_PERIC0, 4, 8), 541 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0", 542 DIV_TOP_PERIC0, 0, 4), 543 544 /* DIV_TOP_PERIC1 */ 545 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a", 546 DIV_TOP_PERIC1, 4, 8), 547 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2", 548 DIV_TOP_PERIC1, 0, 4), 549 550 /* DIV_TOP_PERIC2 */ 551 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2", 552 DIV_TOP_PERIC2, 8, 4), 553 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0", 554 DIV_TOP_PERIC2, 4, 4), 555 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1", 556 DIV_TOP_PERIC2, 0, 4), 557 558 /* DIV_TOP_PERIC3 */ 559 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1", 560 DIV_TOP_PERIC3, 16, 6), 561 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1", 562 DIV_TOP_PERIC3, 8, 8), 563 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1", 564 DIV_TOP_PERIC3, 4, 4), 565 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0", 566 DIV_TOP_PERIC3, 0, 4), 567 568 /* DIV_TOP_PERIC4 */ 569 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a", 570 DIV_TOP_PERIC4, 16, 8), 571 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4", 572 DIV_TOP_PERIC4, 12, 4), 573 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a", 574 DIV_TOP_PERIC4, 4, 8), 575 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3", 576 DIV_TOP_PERIC4, 0, 4), 577}; 578 579static const struct samsung_gate_clock top_gate_clks[] __initconst = { 580 /* ENABLE_ACLK_TOP */ 581 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", 582 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0), 583 GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266", 584 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP, 585 29, CLK_IGNORE_UNUSED, 0), 586 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400", 587 ENABLE_ACLK_TOP, 26, 588 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 589 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400", 590 ENABLE_ACLK_TOP, 25, 591 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 592 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200", 593 ENABLE_ACLK_TOP, 24, 594 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 595 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266", 596 ENABLE_ACLK_TOP, 23, 597 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 598 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", 599 ENABLE_ACLK_TOP, 22, 600 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 601 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", 602 ENABLE_ACLK_TOP, 21, 603 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 604 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400", 605 ENABLE_ACLK_TOP, 19, 606 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 607 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", 608 ENABLE_ACLK_TOP, 18, 609 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 610 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111", 611 ENABLE_ACLK_TOP, 15, 612 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 613 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", 614 ENABLE_ACLK_TOP, 14, 615 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 616 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333", 617 ENABLE_ACLK_TOP, 13, 618 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 619 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400", 620 ENABLE_ACLK_TOP, 12, 621 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 622 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552", 623 ENABLE_ACLK_TOP, 11, 624 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 625 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333", 626 ENABLE_ACLK_TOP, 10, 627 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 628 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400", 629 ENABLE_ACLK_TOP, 9, 630 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 631 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552", 632 ENABLE_ACLK_TOP, 8, 633 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 634 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400", 635 ENABLE_ACLK_TOP, 7, 636 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 637 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400", 638 ENABLE_ACLK_TOP, 6, 639 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 640 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400", 641 ENABLE_ACLK_TOP, 5, 642 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 643 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400", 644 ENABLE_ACLK_TOP, 3, 645 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 646 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", 647 ENABLE_ACLK_TOP, 2, 648 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 649 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", 650 ENABLE_ACLK_TOP, 0, 651 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 652 653 /* ENABLE_SCLK_TOP_MSCL */ 654 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg", 655 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0), 656 657 /* ENABLE_SCLK_TOP_CAM1 */ 658 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b", 659 ENABLE_SCLK_TOP_CAM1, 7, 0, 0), 660 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b", 661 ENABLE_SCLK_TOP_CAM1, 6, 0, 0), 662 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b", 663 ENABLE_SCLK_TOP_CAM1, 5, 0, 0), 664 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk", 665 ENABLE_SCLK_TOP_CAM1, 4, 0, 0), 666 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart", 667 ENABLE_SCLK_TOP_CAM1, 2, 0, 0), 668 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b", 669 ENABLE_SCLK_TOP_CAM1, 1, 0, 0), 670 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b", 671 ENABLE_SCLK_TOP_CAM1, 0, 0, 0), 672 673 /* ENABLE_SCLK_TOP_DISP */ 674 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", 675 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, 676 CLK_IGNORE_UNUSED, 0), 677 678 /* ENABLE_SCLK_TOP_FSYS */ 679 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", 680 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0), 681 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", 682 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), 683 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", 684 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), 685 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", 686 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), 687 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys", 688 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, 689 3, CLK_SET_RATE_PARENT, 0), 690 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys", 691 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, 692 1, CLK_SET_RATE_PARENT, 0), 693 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys", 694 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, 695 0, CLK_SET_RATE_PARENT, 0), 696 697 /* ENABLE_SCLK_TOP_PERIC */ 698 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", 699 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0), 700 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b", 701 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0), 702 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif", 703 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0), 704 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1", 705 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0), 706 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", 707 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), 708 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", 709 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT | 710 CLK_IGNORE_UNUSED, 0), 711 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", 712 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT | 713 CLK_IGNORE_UNUSED, 0), 714 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", 715 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT | 716 CLK_IGNORE_UNUSED, 0), 717 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", 718 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), 719 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", 720 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0), 721 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b", 722 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0), 723 724 /* MUX_ENABLE_TOP_PERIC1 */ 725 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus", 726 MUX_ENABLE_TOP_PERIC1, 16, 0, 0), 727 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1", 728 MUX_ENABLE_TOP_PERIC1, 4, 0, 0), 729 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0", 730 MUX_ENABLE_TOP_PERIC1, 0, 0, 0), 731}; 732 733/* 734 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL 735 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL 736 */ 737static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = { 738 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0), 739 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0), 740 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0), 741 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0), 742 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0), 743 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0), 744 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0), 745 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0), 746 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0), 747 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0), 748 PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0), 749 PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0), 750 PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0), 751 PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0), 752 PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5, 1), 753 PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6, 1), 754 PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4, 1), 755 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6, 1), 756 PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6, 1), 757 PLL_35XX_RATE(24 * MHZ, 933000000U, 311, 4, 1), 758 PLL_35XX_RATE(24 * MHZ, 921000000U, 307, 4, 1), 759 PLL_35XX_RATE(24 * MHZ, 900000000U, 375, 5, 1), 760 PLL_35XX_RATE(24 * MHZ, 825000000U, 275, 4, 1), 761 PLL_35XX_RATE(24 * MHZ, 800000000U, 400, 6, 1), 762 PLL_35XX_RATE(24 * MHZ, 733000000U, 733, 12, 1), 763 PLL_35XX_RATE(24 * MHZ, 700000000U, 175, 3, 1), 764 PLL_35XX_RATE(24 * MHZ, 666000000U, 222, 4, 1), 765 PLL_35XX_RATE(24 * MHZ, 633000000U, 211, 4, 1), 766 PLL_35XX_RATE(24 * MHZ, 600000000U, 500, 5, 2), 767 PLL_35XX_RATE(24 * MHZ, 552000000U, 460, 5, 2), 768 PLL_35XX_RATE(24 * MHZ, 550000000U, 550, 6, 2), 769 PLL_35XX_RATE(24 * MHZ, 543000000U, 362, 4, 2), 770 PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2), 771 PLL_35XX_RATE(24 * MHZ, 500000000U, 500, 6, 2), 772 PLL_35XX_RATE(24 * MHZ, 444000000U, 370, 5, 2), 773 PLL_35XX_RATE(24 * MHZ, 420000000U, 350, 5, 2), 774 PLL_35XX_RATE(24 * MHZ, 400000000U, 400, 6, 2), 775 PLL_35XX_RATE(24 * MHZ, 350000000U, 350, 6, 2), 776 PLL_35XX_RATE(24 * MHZ, 333000000U, 222, 4, 2), 777 PLL_35XX_RATE(24 * MHZ, 300000000U, 500, 5, 3), 778 PLL_35XX_RATE(24 * MHZ, 278000000U, 556, 6, 3), 779 PLL_35XX_RATE(24 * MHZ, 266000000U, 532, 6, 3), 780 PLL_35XX_RATE(24 * MHZ, 250000000U, 500, 6, 3), 781 PLL_35XX_RATE(24 * MHZ, 200000000U, 400, 6, 3), 782 PLL_35XX_RATE(24 * MHZ, 166000000U, 332, 6, 3), 783 PLL_35XX_RATE(24 * MHZ, 160000000U, 320, 6, 3), 784 PLL_35XX_RATE(24 * MHZ, 133000000U, 532, 6, 4), 785 PLL_35XX_RATE(24 * MHZ, 100000000U, 400, 6, 4), 786 { /* sentinel */ } 787}; 788 789/* AUD_PLL */ 790static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { 791 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 792 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 793 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0), 794 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729), 795 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148), 796 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816), 797 PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923), 798 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0), 799 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0), 800 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 801 { /* sentinel */ } 802}; 803 804static const struct samsung_pll_clock top_pll_clks[] __initconst = { 805 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", 806 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates), 807 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 808 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates), 809}; 810 811static const struct samsung_cmu_info top_cmu_info __initconst = { 812 .pll_clks = top_pll_clks, 813 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 814 .mux_clks = top_mux_clks, 815 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 816 .div_clks = top_div_clks, 817 .nr_div_clks = ARRAY_SIZE(top_div_clks), 818 .gate_clks = top_gate_clks, 819 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 820 .fixed_clks = top_fixed_clks, 821 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), 822 .fixed_factor_clks = top_fixed_factor_clks, 823 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), 824 .nr_clk_ids = CLKS_NR_TOP, 825 .clk_regs = top_clk_regs, 826 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 827 .suspend_regs = top_suspend_regs, 828 .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs), 829}; 830 831static void __init exynos5433_cmu_top_init(struct device_node *np) 832{ 833 samsung_cmu_register_one(np, &top_cmu_info); 834} 835CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", 836 exynos5433_cmu_top_init); 837 838/* 839 * Register offset definitions for CMU_CPIF 840 */ 841#define MPHY_PLL_LOCK 0x0000 842#define MPHY_PLL_CON0 0x0100 843#define MPHY_PLL_CON1 0x0104 844#define MPHY_PLL_FREQ_DET 0x010c 845#define MUX_SEL_CPIF0 0x0200 846#define DIV_CPIF 0x0600 847#define ENABLE_SCLK_CPIF 0x0a00 848 849static const unsigned long cpif_clk_regs[] __initconst = { 850 MPHY_PLL_LOCK, 851 MPHY_PLL_CON0, 852 MPHY_PLL_CON1, 853 MPHY_PLL_FREQ_DET, 854 MUX_SEL_CPIF0, 855 DIV_CPIF, 856 ENABLE_SCLK_CPIF, 857}; 858 859static const struct samsung_clk_reg_dump cpif_suspend_regs[] = { 860 /* force all sclk clocks enabled */ 861 { ENABLE_SCLK_CPIF, 0x3ff }, 862 /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */ 863 { MPHY_PLL_CON0, 0x81c70601 }, 864}; 865 866/* list of all parent clock list */ 867PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; 868 869static const struct samsung_pll_clock cpif_pll_clks[] __initconst = { 870 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", 871 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates), 872}; 873 874static const struct samsung_mux_clock cpif_mux_clks[] __initconst = { 875 /* MUX_SEL_CPIF0 */ 876 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 877 0, 1), 878}; 879 880static const struct samsung_div_clock cpif_div_clks[] __initconst = { 881 /* DIV_CPIF */ 882 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 883 0, 6), 884}; 885 886static const struct samsung_gate_clock cpif_gate_clks[] __initconst = { 887 /* ENABLE_SCLK_CPIF */ 888 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", 889 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0), 890 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", 891 ENABLE_SCLK_CPIF, 4, 0, 0), 892}; 893 894static const struct samsung_cmu_info cpif_cmu_info __initconst = { 895 .pll_clks = cpif_pll_clks, 896 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), 897 .mux_clks = cpif_mux_clks, 898 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks), 899 .div_clks = cpif_div_clks, 900 .nr_div_clks = ARRAY_SIZE(cpif_div_clks), 901 .gate_clks = cpif_gate_clks, 902 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), 903 .nr_clk_ids = CLKS_NR_CPIF, 904 .clk_regs = cpif_clk_regs, 905 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), 906 .suspend_regs = cpif_suspend_regs, 907 .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs), 908}; 909 910static void __init exynos5433_cmu_cpif_init(struct device_node *np) 911{ 912 samsung_cmu_register_one(np, &cpif_cmu_info); 913} 914CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", 915 exynos5433_cmu_cpif_init); 916 917/* 918 * Register offset definitions for CMU_MIF 919 */ 920#define MEM0_PLL_LOCK 0x0000 921#define MEM1_PLL_LOCK 0x0004 922#define BUS_PLL_LOCK 0x0008 923#define MFC_PLL_LOCK 0x000c 924#define MEM0_PLL_CON0 0x0100 925#define MEM0_PLL_CON1 0x0104 926#define MEM0_PLL_FREQ_DET 0x010c 927#define MEM1_PLL_CON0 0x0110 928#define MEM1_PLL_CON1 0x0114 929#define MEM1_PLL_FREQ_DET 0x011c 930#define BUS_PLL_CON0 0x0120 931#define BUS_PLL_CON1 0x0124 932#define BUS_PLL_FREQ_DET 0x012c 933#define MFC_PLL_CON0 0x0130 934#define MFC_PLL_CON1 0x0134 935#define MFC_PLL_FREQ_DET 0x013c 936#define MUX_SEL_MIF0 0x0200 937#define MUX_SEL_MIF1 0x0204 938#define MUX_SEL_MIF2 0x0208 939#define MUX_SEL_MIF3 0x020c 940#define MUX_SEL_MIF4 0x0210 941#define MUX_SEL_MIF5 0x0214 942#define MUX_SEL_MIF6 0x0218 943#define MUX_SEL_MIF7 0x021c 944#define MUX_ENABLE_MIF0 0x0300 945#define MUX_ENABLE_MIF1 0x0304 946#define MUX_ENABLE_MIF2 0x0308 947#define MUX_ENABLE_MIF3 0x030c 948#define MUX_ENABLE_MIF4 0x0310 949#define MUX_ENABLE_MIF5 0x0314 950#define MUX_ENABLE_MIF6 0x0318 951#define MUX_ENABLE_MIF7 0x031c 952#define MUX_STAT_MIF0 0x0400 953#define MUX_STAT_MIF1 0x0404 954#define MUX_STAT_MIF2 0x0408 955#define MUX_STAT_MIF3 0x040c 956#define MUX_STAT_MIF4 0x0410 957#define MUX_STAT_MIF5 0x0414 958#define MUX_STAT_MIF6 0x0418 959#define MUX_STAT_MIF7 0x041c 960#define DIV_MIF1 0x0604 961#define DIV_MIF2 0x0608 962#define DIV_MIF3 0x060c 963#define DIV_MIF4 0x0610 964#define DIV_MIF5 0x0614 965#define DIV_MIF_PLL_FREQ_DET 0x0618 966#define DIV_STAT_MIF1 0x0704 967#define DIV_STAT_MIF2 0x0708 968#define DIV_STAT_MIF3 0x070c 969#define DIV_STAT_MIF4 0x0710 970#define DIV_STAT_MIF5 0x0714 971#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 972#define ENABLE_ACLK_MIF0 0x0800 973#define ENABLE_ACLK_MIF1 0x0804 974#define ENABLE_ACLK_MIF2 0x0808 975#define ENABLE_ACLK_MIF3 0x080c 976#define ENABLE_PCLK_MIF 0x0900 977#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 978#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 979#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c 980#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 981#define ENABLE_SCLK_MIF 0x0a00 982#define ENABLE_IP_MIF0 0x0b00 983#define ENABLE_IP_MIF1 0x0b04 984#define ENABLE_IP_MIF2 0x0b08 985#define ENABLE_IP_MIF3 0x0b0c 986#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 987#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 988#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 989#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c 990#define CLKOUT_CMU_MIF 0x0c00 991#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 992#define DREX_FREQ_CTRL0 0x1000 993#define DREX_FREQ_CTRL1 0x1004 994#define PAUSE 0x1008 995#define DDRPHY_LOCK_CTRL 0x100c 996 997static const unsigned long mif_clk_regs[] __initconst = { 998 MEM0_PLL_LOCK, 999 MEM1_PLL_LOCK, 1000 BUS_PLL_LOCK, 1001 MFC_PLL_LOCK, 1002 MEM0_PLL_CON0, 1003 MEM0_PLL_CON1, 1004 MEM0_PLL_FREQ_DET, 1005 MEM1_PLL_CON0, 1006 MEM1_PLL_CON1, 1007 MEM1_PLL_FREQ_DET, 1008 BUS_PLL_CON0, 1009 BUS_PLL_CON1, 1010 BUS_PLL_FREQ_DET, 1011 MFC_PLL_CON0, 1012 MFC_PLL_CON1, 1013 MFC_PLL_FREQ_DET, 1014 MUX_SEL_MIF0, 1015 MUX_SEL_MIF1, 1016 MUX_SEL_MIF2, 1017 MUX_SEL_MIF3, 1018 MUX_SEL_MIF4, 1019 MUX_SEL_MIF5, 1020 MUX_SEL_MIF6, 1021 MUX_SEL_MIF7, 1022 MUX_ENABLE_MIF0, 1023 MUX_ENABLE_MIF1, 1024 MUX_ENABLE_MIF2, 1025 MUX_ENABLE_MIF3, 1026 MUX_ENABLE_MIF4, 1027 MUX_ENABLE_MIF5, 1028 MUX_ENABLE_MIF6, 1029 MUX_ENABLE_MIF7, 1030 DIV_MIF1, 1031 DIV_MIF2, 1032 DIV_MIF3, 1033 DIV_MIF4, 1034 DIV_MIF5, 1035 DIV_MIF_PLL_FREQ_DET, 1036 ENABLE_ACLK_MIF0, 1037 ENABLE_ACLK_MIF1, 1038 ENABLE_ACLK_MIF2, 1039 ENABLE_ACLK_MIF3, 1040 ENABLE_PCLK_MIF, 1041 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 1042 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 1043 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 1044 ENABLE_PCLK_MIF_SECURE_RTC, 1045 ENABLE_SCLK_MIF, 1046 ENABLE_IP_MIF0, 1047 ENABLE_IP_MIF1, 1048 ENABLE_IP_MIF2, 1049 ENABLE_IP_MIF3, 1050 ENABLE_IP_MIF_SECURE_DREX0_TZ, 1051 ENABLE_IP_MIF_SECURE_DREX1_TZ, 1052 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT, 1053 ENABLE_IP_MIF_SECURE_RTC, 1054 CLKOUT_CMU_MIF, 1055 CLKOUT_CMU_MIF_DIV_STAT, 1056 DREX_FREQ_CTRL0, 1057 DREX_FREQ_CTRL1, 1058 PAUSE, 1059 DDRPHY_LOCK_CTRL, 1060}; 1061 1062static const struct samsung_pll_clock mif_pll_clks[] __initconst = { 1063 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", 1064 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates), 1065 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", 1066 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates), 1067 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", 1068 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates), 1069 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", 1070 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates), 1071}; 1072 1073/* list of all parent clock list */ 1074PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", }; 1075PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", }; 1076PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", }; 1077PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", }; 1078PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", }; 1079PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", }; 1080PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", }; 1081PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", }; 1082 1083PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", }; 1084PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", }; 1085PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", }; 1086PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", }; 1087 1088PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", }; 1089PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",}; 1090 1091PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a", 1092 "mout_bus_pll_div2", }; 1093PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", }; 1094 1095PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b", 1096 "sclk_mphy_pll", }; 1097PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a", 1098 "mout_mfc_pll_div2", }; 1099PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", }; 1100PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b", 1101 "sclk_mphy_pll", }; 1102PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a", 1103 "mout_mfc_pll_div2", }; 1104 1105PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b", 1106 "sclk_mphy_pll", }; 1107PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a", 1108 "mout_mfc_pll_div2", }; 1109PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", }; 1110PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", }; 1111PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", }; 1112 1113PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", }; 1114PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" }; 1115 1116PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b", 1117 "sclk_mphy_pll", }; 1118PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", 1119 "mout_mfc_pll_div2", }; 1120PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; 1121PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; 1122 1123static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = { 1124 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ 1125 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), 1126 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), 1127 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0), 1128 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), 1129}; 1130 1131static const struct samsung_mux_clock mif_mux_clks[] __initconst = { 1132 /* MUX_SEL_MIF0 */ 1133 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, 1134 MUX_SEL_MIF0, 28, 1), 1135 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p, 1136 MUX_SEL_MIF0, 24, 1), 1137 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p, 1138 MUX_SEL_MIF0, 20, 1), 1139 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p, 1140 MUX_SEL_MIF0, 16, 1), 1141 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0, 1142 12, 1), 1143 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0, 1144 8, 1), 1145 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0, 1146 4, 1), 1147 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0, 1148 0, 1), 1149 1150 /* MUX_SEL_MIF1 */ 1151 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p, 1152 MUX_SEL_MIF1, 24, 1), 1153 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p, 1154 MUX_SEL_MIF1, 20, 1), 1155 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p, 1156 MUX_SEL_MIF1, 16, 1), 1157 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p, 1158 MUX_SEL_MIF1, 12, 1), 1159 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p, 1160 MUX_SEL_MIF1, 8, 1), 1161 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p, 1162 MUX_SEL_MIF1, 4, 1), 1163 1164 /* MUX_SEL_MIF2 */ 1165 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200", 1166 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1), 1167 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400", 1168 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1), 1169 1170 /* MUX_SEL_MIF3 */ 1171 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b", 1172 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1), 1173 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a", 1174 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1), 1175 1176 /* MUX_SEL_MIF4 */ 1177 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c", 1178 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1), 1179 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b", 1180 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1), 1181 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a", 1182 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1), 1183 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c", 1184 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1), 1185 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b", 1186 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1), 1187 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a", 1188 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1), 1189 1190 /* MUX_SEL_MIF5 */ 1191 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c", 1192 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1), 1193 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b", 1194 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1), 1195 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a", 1196 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1), 1197 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p, 1198 MUX_SEL_MIF5, 8, 1), 1199 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p, 1200 MUX_SEL_MIF5, 4, 1), 1201 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p, 1202 MUX_SEL_MIF5, 0, 1), 1203 1204 /* MUX_SEL_MIF6 */ 1205 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p, 1206 MUX_SEL_MIF6, 8, 1), 1207 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p, 1208 MUX_SEL_MIF6, 4, 1), 1209 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p, 1210 MUX_SEL_MIF6, 0, 1), 1211 1212 /* MUX_SEL_MIF7 */ 1213 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c", 1214 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1), 1215 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b", 1216 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1), 1217 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a", 1218 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1), 1219 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p, 1220 MUX_SEL_MIF7, 8, 1), 1221 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p, 1222 MUX_SEL_MIF7, 4, 1), 1223 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p, 1224 MUX_SEL_MIF7, 0, 1), 1225}; 1226 1227static const struct samsung_div_clock mif_div_clks[] __initconst = { 1228 /* DIV_MIF1 */ 1229 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", 1230 DIV_MIF1, 16, 2), 1231 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1, 1232 12, 2), 1233 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1, 1234 8, 2), 1235 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1, 1236 4, 4), 1237 1238 /* DIV_MIF2 */ 1239 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2", 1240 DIV_MIF2, 20, 3), 1241 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre", 1242 DIV_MIF2, 16, 4), 1243 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre", 1244 DIV_MIF2, 12, 4), 1245 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200", 1246 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3), 1247 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400", 1248 DIV_MIF2, 4, 2), 1249 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400", 1250 DIV_MIF2, 0, 3), 1251 1252 /* DIV_MIF3 */ 1253 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre", 1254 DIV_MIF3, 16, 4), 1255 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b", 1256 DIV_MIF3, 4, 3), 1257 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200", 1258 DIV_MIF3, 0, 3), 1259 1260 /* DIV_MIF4 */ 1261 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c", 1262 DIV_MIF4, 24, 4), 1263 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk", 1264 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4), 1265 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c", 1266 DIV_MIF4, 16, 4), 1267 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c", 1268 DIV_MIF4, 12, 4), 1269 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk", 1270 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4), 1271 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk", 1272 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4), 1273 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk", 1274 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4), 1275 1276 /* DIV_MIF5 */ 1277 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5, 1278 0, 3), 1279}; 1280 1281static const struct samsung_gate_clock mif_gate_clks[] __initconst = { 1282 /* ENABLE_ACLK_MIF0 */ 1283 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1284 19, CLK_IGNORE_UNUSED, 0), 1285 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1286 18, CLK_IGNORE_UNUSED, 0), 1287 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1288 17, CLK_IGNORE_UNUSED, 0), 1289 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1290 16, CLK_IGNORE_UNUSED, 0), 1291 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0, 1292 15, CLK_IGNORE_UNUSED, 0), 1293 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0, 1294 14, CLK_IGNORE_UNUSED, 0), 1295 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1", 1296 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0), 1297 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0", 1298 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0), 1299 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1", 1300 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0), 1301 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0", 1302 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0), 1303 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1", 1304 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0), 1305 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0", 1306 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0), 1307 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1", 1308 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0), 1309 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0", 1310 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0), 1311 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1", 1312 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0), 1313 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0", 1314 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0), 1315 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1", 1316 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0), 1317 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0", 1318 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1319 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1", 1320 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1321 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0", 1322 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0), 1323 1324 /* ENABLE_ACLK_MIF1 */ 1325 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem", 1326 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28, 1327 CLK_IGNORE_UNUSED, 0), 1328 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci", 1329 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 1330 27, CLK_IGNORE_UNUSED, 0), 1331 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci", 1332 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1333 26, CLK_IGNORE_UNUSED, 0), 1334 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1", 1335 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1336 25, CLK_IGNORE_UNUSED, 0), 1337 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1", 1338 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1339 24, CLK_IGNORE_UNUSED, 0), 1340 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0", 1341 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1342 23, CLK_IGNORE_UNUSED, 0), 1343 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0", 1344 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1345 22, CLK_IGNORE_UNUSED, 0), 1346 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3", 1347 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1348 21, CLK_IGNORE_UNUSED, 0), 1349 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3", 1350 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1351 20, CLK_IGNORE_UNUSED, 0), 1352 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1", 1353 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1354 19, CLK_IGNORE_UNUSED, 0), 1355 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1", 1356 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1357 18, CLK_IGNORE_UNUSED, 0), 1358 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0", 1359 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1360 17, CLK_IGNORE_UNUSED, 0), 1361 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0", 1362 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1363 16, CLK_IGNORE_UNUSED, 0), 1364 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3", 1365 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1366 15, CLK_IGNORE_UNUSED, 0), 1367 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3", 1368 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1369 14, CLK_IGNORE_UNUSED, 0), 1370 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1", 1371 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1372 13, CLK_IGNORE_UNUSED, 0), 1373 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1", 1374 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1375 12, CLK_IGNORE_UNUSED, 0), 1376 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0", 1377 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1378 11, CLK_IGNORE_UNUSED, 0), 1379 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0", 1380 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1381 10, CLK_IGNORE_UNUSED, 0), 1382 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133", 1383 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0), 1384 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133", 1385 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0), 1386 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133", 1387 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0), 1388 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400", 1389 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0), 1390 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200", 1391 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0), 1392 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133", 1393 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0), 1394 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200", 1395 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0), 1396 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133", 1397 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0), 1398 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400", 1399 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0), 1400 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1, 1401 0, CLK_IGNORE_UNUSED, 0), 1402 1403 /* ENABLE_ACLK_MIF2 */ 1404 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", 1405 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0), 1406 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", 1407 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), 1408 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", 1409 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0), 1410 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1", 1411 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0), 1412 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0", 1413 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0), 1414 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0", 1415 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0), 1416 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0", 1417 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0), 1418 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx", 1419 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7, 1420 CLK_IGNORE_UNUSED, 0), 1421 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci", 1422 "div_aclk_mif_400", ENABLE_ACLK_MIF2, 1423 5, CLK_IGNORE_UNUSED, 0), 1424 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400", 1425 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0), 1426 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d", 1427 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 1428 3, CLK_IGNORE_UNUSED, 0), 1429 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys", 1430 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0), 1431 1432 /* ENABLE_ACLK_MIF3 */ 1433 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", 1434 ENABLE_ACLK_MIF3, 4, 1435 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 1436 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", 1437 ENABLE_ACLK_MIF3, 1, 1438 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 1439 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", 1440 ENABLE_ACLK_MIF3, 0, 1441 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1442 1443 /* ENABLE_PCLK_MIF */ 1444 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1", 1445 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0), 1446 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1", 1447 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0), 1448 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1", 1449 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0), 1450 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0", 1451 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0), 1452 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0", 1453 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0), 1454 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0", 1455 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0), 1456 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci", 1457 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21, 1458 CLK_IGNORE_UNUSED, 0), 1459 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133", 1460 ENABLE_PCLK_MIF, 19, 0, 0), 1461 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133", 1462 ENABLE_PCLK_MIF, 18, 0, 0), 1463 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3", 1464 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0), 1465 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1", 1466 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0), 1467 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0", 1468 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0), 1469 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3", 1470 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0), 1471 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1", 1472 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0), 1473 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0", 1474 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0), 1475 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133", 1476 ENABLE_PCLK_MIF, 11, 0, 0), 1477 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133", 1478 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), 1479 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133", 1480 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1481 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133", 1482 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1483 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133", 1484 ENABLE_PCLK_MIF, 7, 0, 0), 1485 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133", 1486 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0), 1487 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133", 1488 ENABLE_PCLK_MIF, 5, 0, 0), 1489 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133", 1490 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1491 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133", 1492 ENABLE_PCLK_MIF, 2, 0, 0), 1493 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133", 1494 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1495 1496 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ 1497 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", 1498 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 1499 CLK_IGNORE_UNUSED, 0), 1500 1501 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ 1502 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", 1503 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 1504 CLK_IGNORE_UNUSED, 0), 1505 1506 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ 1507 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", 1508 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0), 1509 1510 /* ENABLE_PCLK_MIF_SECURE_RTC */ 1511 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", 1512 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), 1513 1514 /* ENABLE_SCLK_MIF */ 1515 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1", 1516 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0), 1517 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp", 1518 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 1519 14, CLK_IGNORE_UNUSED, 0), 1520 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0", 1521 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1522 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd", 1523 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1524 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp", 1525 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 1526 7, CLK_IGNORE_UNUSED, 0), 1527 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp", 1528 "div_sclk_decon_vclk", ENABLE_SCLK_MIF, 1529 6, CLK_IGNORE_UNUSED, 0), 1530 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp", 1531 "div_sclk_decon_eclk", ENABLE_SCLK_MIF, 1532 5, CLK_IGNORE_UNUSED, 0), 1533 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif", 1534 ENABLE_SCLK_MIF, 4, 1535 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1536 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2", 1537 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1538 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2", 1539 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0), 1540 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll", 1541 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), 1542 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", 1543 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1544}; 1545 1546static const struct samsung_cmu_info mif_cmu_info __initconst = { 1547 .pll_clks = mif_pll_clks, 1548 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1549 .mux_clks = mif_mux_clks, 1550 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), 1551 .div_clks = mif_div_clks, 1552 .nr_div_clks = ARRAY_SIZE(mif_div_clks), 1553 .gate_clks = mif_gate_clks, 1554 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), 1555 .fixed_factor_clks = mif_fixed_factor_clks, 1556 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), 1557 .nr_clk_ids = CLKS_NR_MIF, 1558 .clk_regs = mif_clk_regs, 1559 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1560}; 1561 1562static void __init exynos5433_cmu_mif_init(struct device_node *np) 1563{ 1564 samsung_cmu_register_one(np, &mif_cmu_info); 1565} 1566CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", 1567 exynos5433_cmu_mif_init); 1568 1569/* 1570 * Register offset definitions for CMU_PERIC 1571 */ 1572#define DIV_PERIC 0x0600 1573#define DIV_STAT_PERIC 0x0700 1574#define ENABLE_ACLK_PERIC 0x0800 1575#define ENABLE_PCLK_PERIC0 0x0900 1576#define ENABLE_PCLK_PERIC1 0x0904 1577#define ENABLE_SCLK_PERIC 0x0A00 1578#define ENABLE_IP_PERIC0 0x0B00 1579#define ENABLE_IP_PERIC1 0x0B04 1580#define ENABLE_IP_PERIC2 0x0B08 1581 1582static const unsigned long peric_clk_regs[] __initconst = { 1583 DIV_PERIC, 1584 ENABLE_ACLK_PERIC, 1585 ENABLE_PCLK_PERIC0, 1586 ENABLE_PCLK_PERIC1, 1587 ENABLE_SCLK_PERIC, 1588 ENABLE_IP_PERIC0, 1589 ENABLE_IP_PERIC1, 1590 ENABLE_IP_PERIC2, 1591}; 1592 1593static const struct samsung_clk_reg_dump peric_suspend_regs[] = { 1594 /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */ 1595 { ENABLE_PCLK_PERIC0, 0xe00ff000 }, 1596 /* sclk: uart2-0 */ 1597 { ENABLE_SCLK_PERIC, 0x7 }, 1598}; 1599 1600static const struct samsung_div_clock peric_div_clks[] __initconst = { 1601 /* DIV_PERIC */ 1602 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), 1603 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), 1604}; 1605 1606static const struct samsung_gate_clock peric_gate_clks[] __initconst = { 1607 /* ENABLE_ACLK_PERIC */ 1608 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", 1609 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), 1610 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", 1611 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), 1612 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", 1613 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), 1614 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", 1615 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), 1616 1617 /* ENABLE_PCLK_PERIC0 */ 1618 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1619 31, CLK_SET_RATE_PARENT, 0), 1620 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", 1621 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), 1622 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", 1623 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), 1624 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1625 28, CLK_SET_RATE_PARENT, 0), 1626 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1627 26, CLK_SET_RATE_PARENT, 0), 1628 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1629 25, CLK_SET_RATE_PARENT, 0), 1630 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1631 24, CLK_SET_RATE_PARENT, 0), 1632 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1633 23, CLK_SET_RATE_PARENT, 0), 1634 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1635 22, CLK_SET_RATE_PARENT, 0), 1636 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1637 21, CLK_SET_RATE_PARENT, 0), 1638 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1639 20, CLK_SET_RATE_PARENT, 0), 1640 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", 1641 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), 1642 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", 1643 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), 1644 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", 1645 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), 1646 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", 1647 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), 1648 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", 1649 ENABLE_PCLK_PERIC0, 15, 1650 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1651 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1652 14, CLK_SET_RATE_PARENT, 0), 1653 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1654 13, CLK_SET_RATE_PARENT, 0), 1655 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1656 12, CLK_SET_RATE_PARENT, 0), 1657 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66", 1658 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0), 1659 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66", 1660 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0), 1661 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66", 1662 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0), 1663 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66", 1664 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 1665 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1666 7, CLK_SET_RATE_PARENT, 0), 1667 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1668 6, CLK_SET_RATE_PARENT, 0), 1669 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1670 5, CLK_SET_RATE_PARENT, 0), 1671 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1672 4, CLK_SET_RATE_PARENT, 0), 1673 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1674 3, CLK_SET_RATE_PARENT, 0), 1675 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1676 2, CLK_SET_RATE_PARENT, 0), 1677 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1678 1, CLK_SET_RATE_PARENT, 0), 1679 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1680 0, CLK_SET_RATE_PARENT, 0), 1681 1682 /* ENABLE_PCLK_PERIC1 */ 1683 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1684 9, CLK_SET_RATE_PARENT, 0), 1685 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1686 8, CLK_SET_RATE_PARENT, 0), 1687 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66", 1688 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0), 1689 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66", 1690 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0), 1691 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66", 1692 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0), 1693 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66", 1694 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 1695 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66", 1696 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0), 1697 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66", 1698 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0), 1699 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66", 1700 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0), 1701 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66", 1702 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 1703 1704 /* ENABLE_SCLK_PERIC */ 1705 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", 1706 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), 1707 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", 1708 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), 1709 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, 1710 19, CLK_SET_RATE_PARENT, 0), 1711 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, 1712 18, CLK_SET_RATE_PARENT, 0), 1713 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, 1714 17, 0, 0), 1715 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, 1716 16, 0, 0), 1717 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), 1718 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", 1719 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), 1720 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", 1721 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0), 1722 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", 1723 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1724 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", 1725 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, 1726 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1727 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", 1728 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1729 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", 1730 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1731 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", 1732 ENABLE_SCLK_PERIC, 6, 1733 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1734 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 1735 5, CLK_SET_RATE_PARENT, 0), 1736 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, 1737 4, CLK_SET_RATE_PARENT, 0), 1738 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 1739 3, CLK_SET_RATE_PARENT, 0), 1740 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", 1741 ENABLE_SCLK_PERIC, 2, 1742 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1743 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", 1744 ENABLE_SCLK_PERIC, 1, 1745 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1746 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", 1747 ENABLE_SCLK_PERIC, 0, 1748 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1749}; 1750 1751static const struct samsung_cmu_info peric_cmu_info __initconst = { 1752 .div_clks = peric_div_clks, 1753 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 1754 .gate_clks = peric_gate_clks, 1755 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 1756 .nr_clk_ids = CLKS_NR_PERIC, 1757 .clk_regs = peric_clk_regs, 1758 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 1759 .suspend_regs = peric_suspend_regs, 1760 .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs), 1761}; 1762 1763static void __init exynos5433_cmu_peric_init(struct device_node *np) 1764{ 1765 samsung_cmu_register_one(np, &peric_cmu_info); 1766} 1767 1768CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", 1769 exynos5433_cmu_peric_init); 1770 1771/* 1772 * Register offset definitions for CMU_PERIS 1773 */ 1774#define ENABLE_ACLK_PERIS 0x0800 1775#define ENABLE_PCLK_PERIS 0x0900 1776#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 1777#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 1778#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c 1779#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 1780#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 1781#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 1782#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c 1783#define ENABLE_SCLK_PERIS 0x0a00 1784#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 1785#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 1786#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c 1787#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 1788#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 1789#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 1790#define ENABLE_IP_PERIS0 0x0b00 1791#define ENABLE_IP_PERIS1 0x0b04 1792#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 1793#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c 1794#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 1795#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 1796#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 1797#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c 1798#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 1799 1800static const unsigned long peris_clk_regs[] __initconst = { 1801 ENABLE_ACLK_PERIS, 1802 ENABLE_PCLK_PERIS, 1803 ENABLE_PCLK_PERIS_SECURE_TZPC, 1804 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 1805 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 1806 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 1807 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 1808 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 1809 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 1810 ENABLE_SCLK_PERIS, 1811 ENABLE_SCLK_PERIS_SECURE_SECKEY, 1812 ENABLE_SCLK_PERIS_SECURE_CHIPID, 1813 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 1814 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 1815 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 1816 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 1817 ENABLE_IP_PERIS0, 1818 ENABLE_IP_PERIS1, 1819 ENABLE_IP_PERIS_SECURE_TZPC, 1820 ENABLE_IP_PERIS_SECURE_SECKEY, 1821 ENABLE_IP_PERIS_SECURE_CHIPID, 1822 ENABLE_IP_PERIS_SECURE_TOPRTC, 1823 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE, 1824 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT, 1825 ENABLE_IP_PERIS_SECURE_OTP_CON, 1826}; 1827 1828static const struct samsung_gate_clock peris_gate_clks[] __initconst = { 1829 /* ENABLE_ACLK_PERIS */ 1830 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", 1831 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), 1832 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66", 1833 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1834 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66", 1835 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1836 1837 /* ENABLE_PCLK_PERIS */ 1838 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66", 1839 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0), 1840 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66", 1841 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0), 1842 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66", 1843 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0), 1844 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66", 1845 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0), 1846 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66", 1847 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0), 1848 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66", 1849 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0), 1850 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66", 1851 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0), 1852 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66", 1853 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0), 1854 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66", 1855 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0), 1856 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66", 1857 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0), 1858 1859 /* ENABLE_PCLK_PERIS_SECURE_TZPC */ 1860 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", 1861 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0), 1862 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", 1863 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0), 1864 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", 1865 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0), 1866 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", 1867 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0), 1868 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", 1869 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0), 1870 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", 1871 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0), 1872 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", 1873 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0), 1874 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", 1875 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0), 1876 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", 1877 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0), 1878 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", 1879 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0), 1880 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", 1881 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0), 1882 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", 1883 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0), 1884 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", 1885 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0), 1886 1887 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ 1888 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", 1889 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1890 1891 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ 1892 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", 1893 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1894 1895 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ 1896 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", 1897 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1898 1899 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ 1900 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif", 1901 "aclk_peris_66", 1902 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0), 1903 1904 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ 1905 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif", 1906 "aclk_peris_66", 1907 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0), 1908 1909 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ 1910 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif", 1911 "aclk_peris_66", 1912 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0), 1913 1914 /* ENABLE_SCLK_PERIS */ 1915 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common", 1916 ENABLE_SCLK_PERIS, 10, 0, 0), 1917 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common", 1918 ENABLE_SCLK_PERIS, 4, 0, 0), 1919 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common", 1920 ENABLE_SCLK_PERIS, 3, 0, 0), 1921 1922 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ 1923 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", 1924 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0), 1925 1926 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ 1927 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", 1928 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0), 1929 1930 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ 1931 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", 1932 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1933 1934 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ 1935 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common", 1936 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0), 1937 1938 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ 1939 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common", 1940 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0), 1941 1942 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ 1943 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common", 1944 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), 1945}; 1946 1947static const struct samsung_cmu_info peris_cmu_info __initconst = { 1948 .gate_clks = peris_gate_clks, 1949 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 1950 .nr_clk_ids = CLKS_NR_PERIS, 1951 .clk_regs = peris_clk_regs, 1952 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 1953}; 1954 1955static void __init exynos5433_cmu_peris_init(struct device_node *np) 1956{ 1957 samsung_cmu_register_one(np, &peris_cmu_info); 1958} 1959 1960CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", 1961 exynos5433_cmu_peris_init); 1962 1963/* 1964 * Register offset definitions for CMU_FSYS 1965 */ 1966#define MUX_SEL_FSYS0 0x0200 1967#define MUX_SEL_FSYS1 0x0204 1968#define MUX_SEL_FSYS2 0x0208 1969#define MUX_SEL_FSYS3 0x020c 1970#define MUX_SEL_FSYS4 0x0210 1971#define MUX_ENABLE_FSYS0 0x0300 1972#define MUX_ENABLE_FSYS1 0x0304 1973#define MUX_ENABLE_FSYS2 0x0308 1974#define MUX_ENABLE_FSYS3 0x030c 1975#define MUX_ENABLE_FSYS4 0x0310 1976#define MUX_STAT_FSYS0 0x0400 1977#define MUX_STAT_FSYS1 0x0404 1978#define MUX_STAT_FSYS2 0x0408 1979#define MUX_STAT_FSYS3 0x040c 1980#define MUX_STAT_FSYS4 0x0410 1981#define MUX_IGNORE_FSYS2 0x0508 1982#define MUX_IGNORE_FSYS3 0x050c 1983#define ENABLE_ACLK_FSYS0 0x0800 1984#define ENABLE_ACLK_FSYS1 0x0804 1985#define ENABLE_PCLK_FSYS 0x0900 1986#define ENABLE_SCLK_FSYS 0x0a00 1987#define ENABLE_IP_FSYS0 0x0b00 1988#define ENABLE_IP_FSYS1 0x0b04 1989 1990/* list of all parent clock list */ 1991PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", }; 1992PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", }; 1993PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",}; 1994PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",}; 1995PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; 1996PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; 1997PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; 1998PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",}; 1999PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", }; 2000 2001PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) 2002 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", }; 2003PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p) 2004 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", }; 2005PNAME(mout_phyclk_usbhost20_phy_hsic1_p) 2006 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", }; 2007PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p) 2008 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", }; 2009PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p) 2010 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", }; 2011PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p) 2012 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", }; 2013PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) 2014 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", }; 2015PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p) 2016 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", }; 2017PNAME(mout_phyclk_ufs_rx1_symbol_user_p) 2018 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", }; 2019PNAME(mout_phyclk_ufs_rx0_symbol_user_p) 2020 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", }; 2021PNAME(mout_phyclk_ufs_tx1_symbol_user_p) 2022 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", }; 2023PNAME(mout_phyclk_ufs_tx0_symbol_user_p) 2024 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", }; 2025PNAME(mout_phyclk_lli_mphy_to_ufs_user_p) 2026 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", }; 2027PNAME(mout_sclk_mphy_p) 2028 = { "mout_sclk_ufs_mphy_user", 2029 "mout_phyclk_lli_mphy_to_ufs_user", }; 2030 2031static const unsigned long fsys_clk_regs[] __initconst = { 2032 MUX_SEL_FSYS0, 2033 MUX_SEL_FSYS1, 2034 MUX_SEL_FSYS2, 2035 MUX_SEL_FSYS3, 2036 MUX_SEL_FSYS4, 2037 MUX_ENABLE_FSYS0, 2038 MUX_ENABLE_FSYS1, 2039 MUX_ENABLE_FSYS2, 2040 MUX_ENABLE_FSYS3, 2041 MUX_ENABLE_FSYS4, 2042 MUX_IGNORE_FSYS2, 2043 MUX_IGNORE_FSYS3, 2044 ENABLE_ACLK_FSYS0, 2045 ENABLE_ACLK_FSYS1, 2046 ENABLE_PCLK_FSYS, 2047 ENABLE_SCLK_FSYS, 2048 ENABLE_IP_FSYS0, 2049 ENABLE_IP_FSYS1, 2050}; 2051 2052static const struct samsung_clk_reg_dump fsys_suspend_regs[] = { 2053 { MUX_SEL_FSYS0, 0 }, 2054 { MUX_SEL_FSYS1, 0 }, 2055 { MUX_SEL_FSYS2, 0 }, 2056 { MUX_SEL_FSYS3, 0 }, 2057 { MUX_SEL_FSYS4, 0 }, 2058}; 2059 2060static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { 2061 /* PHY clocks from USBDRD30_PHY */ 2062 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 2063 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, 2064 0, 60000000), 2065 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY, 2066 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, 2067 0, 125000000), 2068 /* PHY clocks from USBHOST30_PHY */ 2069 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY, 2070 "phyclk_usbhost30_uhost30_phyclock_phy", NULL, 2071 0, 60000000), 2072 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY, 2073 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, 2074 0, 125000000), 2075 /* PHY clocks from USBHOST20_PHY */ 2076 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY, 2077 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000), 2078 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY, 2079 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000), 2080 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY, 2081 "phyclk_usbhost20_phy_clk48mohci_phy", NULL, 2082 0, 48000000), 2083 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY, 2084 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0, 2085 60000000), 2086 /* PHY clocks from UFS_PHY */ 2087 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy", 2088 NULL, 0, 300000000), 2089 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy", 2090 NULL, 0, 300000000), 2091 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy", 2092 NULL, 0, 300000000), 2093 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy", 2094 NULL, 0, 300000000), 2095 /* PHY clocks from LLI_PHY */ 2096 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy", 2097 NULL, 0, 26000000), 2098}; 2099 2100static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { 2101 /* MUX_SEL_FSYS0 */ 2102 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", 2103 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), 2104 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", 2105 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), 2106 2107 /* MUX_SEL_FSYS1 */ 2108 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user", 2109 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1), 2110 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user", 2111 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1), 2112 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", 2113 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), 2114 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", 2115 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), 2116 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", 2117 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), 2118 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user", 2119 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1), 2120 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user", 2121 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1), 2122 2123 /* MUX_SEL_FSYS2 */ 2124 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER, 2125 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2126 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p, 2127 MUX_SEL_FSYS2, 28, 1), 2128 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER, 2129 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2130 mout_phyclk_usbhost30_uhost30_phyclock_user_p, 2131 MUX_SEL_FSYS2, 24, 1), 2132 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER, 2133 "mout_phyclk_usbhost20_phy_hsic1", 2134 mout_phyclk_usbhost20_phy_hsic1_p, 2135 MUX_SEL_FSYS2, 20, 1), 2136 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER, 2137 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2138 mout_phyclk_usbhost20_phy_clk48mohci_user_p, 2139 MUX_SEL_FSYS2, 16, 1), 2140 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER, 2141 "mout_phyclk_usbhost20_phy_phyclock_user", 2142 mout_phyclk_usbhost20_phy_phyclock_user_p, 2143 MUX_SEL_FSYS2, 12, 1), 2144 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER, 2145 "mout_phyclk_usbhost20_phy_freeclk_user", 2146 mout_phyclk_usbhost20_phy_freeclk_user_p, 2147 MUX_SEL_FSYS2, 8, 1), 2148 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 2149 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2150 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p, 2151 MUX_SEL_FSYS2, 4, 1), 2152 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 2153 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2154 mout_phyclk_usbdrd30_udrd30_phyclock_user_p, 2155 MUX_SEL_FSYS2, 0, 1), 2156 2157 /* MUX_SEL_FSYS3 */ 2158 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER, 2159 "mout_phyclk_ufs_rx1_symbol_user", 2160 mout_phyclk_ufs_rx1_symbol_user_p, 2161 MUX_SEL_FSYS3, 16, 1), 2162 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER, 2163 "mout_phyclk_ufs_rx0_symbol_user", 2164 mout_phyclk_ufs_rx0_symbol_user_p, 2165 MUX_SEL_FSYS3, 12, 1), 2166 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER, 2167 "mout_phyclk_ufs_tx1_symbol_user", 2168 mout_phyclk_ufs_tx1_symbol_user_p, 2169 MUX_SEL_FSYS3, 8, 1), 2170 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER, 2171 "mout_phyclk_ufs_tx0_symbol_user", 2172 mout_phyclk_ufs_tx0_symbol_user_p, 2173 MUX_SEL_FSYS3, 4, 1), 2174 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER, 2175 "mout_phyclk_lli_mphy_to_ufs_user", 2176 mout_phyclk_lli_mphy_to_ufs_user_p, 2177 MUX_SEL_FSYS3, 0, 1), 2178 2179 /* MUX_SEL_FSYS4 */ 2180 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p, 2181 MUX_SEL_FSYS4, 0, 1), 2182}; 2183 2184static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { 2185 /* ENABLE_ACLK_FSYS0 */ 2186 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", 2187 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), 2188 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user", 2189 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0), 2190 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user", 2191 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 2192 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user", 2193 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0), 2194 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user", 2195 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0), 2196 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user", 2197 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0), 2198 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user", 2199 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0), 2200 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user", 2201 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0), 2202 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user", 2203 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0), 2204 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user", 2205 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0), 2206 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", 2207 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), 2208 2209 /* ENABLE_ACLK_FSYS1 */ 2210 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user", 2211 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0), 2212 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1", 2213 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2214 26, CLK_IGNORE_UNUSED, 0), 2215 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2216 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), 2217 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", 2218 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0), 2219 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", 2220 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2221 22, CLK_IGNORE_UNUSED, 0), 2222 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2223 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0), 2224 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user", 2225 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0), 2226 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30", 2227 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2228 13, 0, 0), 2229 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30", 2230 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2231 12, 0, 0), 2232 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0", 2233 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2234 11, CLK_IGNORE_UNUSED, 0), 2235 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs", 2236 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2237 10, CLK_IGNORE_UNUSED, 0), 2238 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx", 2239 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2240 9, CLK_IGNORE_UNUSED, 0), 2241 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp", 2242 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2243 8, CLK_IGNORE_UNUSED, 0), 2244 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs", 2245 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2246 7, CLK_IGNORE_UNUSED, 0), 2247 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0", 2248 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2249 6, CLK_IGNORE_UNUSED, 0), 2250 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user", 2251 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0), 2252 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user", 2253 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0), 2254 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user", 2255 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0), 2256 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user", 2257 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0), 2258 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user", 2259 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0), 2260 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user", 2261 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0), 2262 2263 /* ENABLE_PCLK_FSYS */ 2264 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", 2265 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0), 2266 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2267 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), 2268 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", 2269 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0), 2270 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", 2271 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0), 2272 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2273 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), 2274 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", 2275 ENABLE_PCLK_FSYS, 5, 0, 0), 2276 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30", 2277 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0), 2278 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30", 2279 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0), 2280 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user", 2281 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0), 2282 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user", 2283 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0), 2284 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys", 2285 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 2286 0, CLK_IGNORE_UNUSED, 0), 2287 2288 /* ENABLE_SCLK_FSYS */ 2289 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user", 2290 ENABLE_SCLK_FSYS, 21, 0, 0), 2291 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK, 2292 "phyclk_usbhost30_uhost30_pipe_pclk", 2293 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2294 ENABLE_SCLK_FSYS, 18, 0, 0), 2295 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK, 2296 "phyclk_usbhost30_uhost30_phyclock", 2297 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2298 ENABLE_SCLK_FSYS, 17, 0, 0), 2299 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol", 2300 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS, 2301 16, 0, 0), 2302 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol", 2303 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS, 2304 15, 0, 0), 2305 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol", 2306 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS, 2307 14, 0, 0), 2308 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol", 2309 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS, 2310 13, 0, 0), 2311 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1", 2312 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS, 2313 12, 0, 0), 2314 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI, 2315 "phyclk_usbhost20_phy_clk48mohci", 2316 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2317 ENABLE_SCLK_FSYS, 11, 0, 0), 2318 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK, 2319 "phyclk_usbhost20_phy_phyclock", 2320 "mout_phyclk_usbhost20_phy_phyclock_user", 2321 ENABLE_SCLK_FSYS, 10, 0, 0), 2322 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK, 2323 "phyclk_usbhost20_phy_freeclk", 2324 "mout_phyclk_usbhost20_phy_freeclk_user", 2325 ENABLE_SCLK_FSYS, 9, 0, 0), 2326 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 2327 "phyclk_usbdrd30_udrd30_pipe_pclk", 2328 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2329 ENABLE_SCLK_FSYS, 8, 0, 0), 2330 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 2331 "phyclk_usbdrd30_udrd30_phyclock", 2332 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2333 ENABLE_SCLK_FSYS, 7, 0, 0), 2334 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy", 2335 ENABLE_SCLK_FSYS, 6, 0, 0), 2336 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user", 2337 ENABLE_SCLK_FSYS, 5, 0, 0), 2338 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", 2339 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 2340 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", 2341 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), 2342 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", 2343 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 2344 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user", 2345 ENABLE_SCLK_FSYS, 1, 0, 0), 2346 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user", 2347 ENABLE_SCLK_FSYS, 0, 0, 0), 2348 2349 /* ENABLE_IP_FSYS0 */ 2350 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0), 2351 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), 2352 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), 2353}; 2354 2355static const struct samsung_cmu_info fsys_cmu_info __initconst = { 2356 .mux_clks = fsys_mux_clks, 2357 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 2358 .gate_clks = fsys_gate_clks, 2359 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 2360 .fixed_clks = fsys_fixed_clks, 2361 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), 2362 .nr_clk_ids = CLKS_NR_FSYS, 2363 .clk_regs = fsys_clk_regs, 2364 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 2365 .suspend_regs = fsys_suspend_regs, 2366 .nr_suspend_regs = ARRAY_SIZE(fsys_suspend_regs), 2367 .clk_name = "aclk_fsys_200", 2368}; 2369 2370/* 2371 * Register offset definitions for CMU_G2D 2372 */ 2373#define MUX_SEL_G2D0 0x0200 2374#define MUX_SEL_ENABLE_G2D0 0x0300 2375#define MUX_SEL_STAT_G2D0 0x0400 2376#define DIV_G2D 0x0600 2377#define DIV_STAT_G2D 0x0700 2378#define DIV_ENABLE_ACLK_G2D 0x0800 2379#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804 2380#define DIV_ENABLE_PCLK_G2D 0x0900 2381#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904 2382#define DIV_ENABLE_IP_G2D0 0x0b00 2383#define DIV_ENABLE_IP_G2D1 0x0b04 2384#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 2385 2386static const unsigned long g2d_clk_regs[] __initconst = { 2387 MUX_SEL_G2D0, 2388 MUX_SEL_ENABLE_G2D0, 2389 DIV_G2D, 2390 DIV_ENABLE_ACLK_G2D, 2391 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 2392 DIV_ENABLE_PCLK_G2D, 2393 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 2394 DIV_ENABLE_IP_G2D0, 2395 DIV_ENABLE_IP_G2D1, 2396 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, 2397}; 2398 2399static const struct samsung_clk_reg_dump g2d_suspend_regs[] = { 2400 { MUX_SEL_G2D0, 0 }, 2401}; 2402 2403/* list of all parent clock list */ 2404PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; 2405PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; 2406 2407static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { 2408 /* MUX_SEL_G2D0 */ 2409 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", 2410 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), 2411 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user", 2412 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), 2413}; 2414 2415static const struct samsung_div_clock g2d_div_clks[] __initconst = { 2416 /* DIV_G2D */ 2417 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", 2418 DIV_G2D, 0, 2), 2419}; 2420 2421static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { 2422 /* DIV_ENABLE_ACLK_G2D */ 2423 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", 2424 DIV_ENABLE_ACLK_G2D, 12, 0, 0), 2425 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user", 2426 DIV_ENABLE_ACLK_G2D, 11, 0, 0), 2427 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user", 2428 DIV_ENABLE_ACLK_G2D, 10, 0, 0), 2429 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user", 2430 DIV_ENABLE_ACLK_G2D, 9, 0, 0), 2431 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user", 2432 DIV_ENABLE_ACLK_G2D, 8, 0, 0), 2433 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx", 2434 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D, 2435 7, 0, 0), 2436 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d", 2437 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), 2438 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d", 2439 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), 2440 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user", 2441 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), 2442 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d", 2443 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), 2444 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user", 2445 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2446 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user", 2447 DIV_ENABLE_ACLK_G2D, 1, 0, 0), 2448 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user", 2449 DIV_ENABLE_ACLK_G2D, 0, 0, 0), 2450 2451 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ 2452 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user", 2453 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2454 2455 /* DIV_ENABLE_PCLK_G2D */ 2456 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d", 2457 DIV_ENABLE_PCLK_G2D, 7, 0, 0), 2458 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d", 2459 DIV_ENABLE_PCLK_G2D, 6, 0, 0), 2460 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d", 2461 DIV_ENABLE_PCLK_G2D, 5, 0, 0), 2462 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d", 2463 DIV_ENABLE_PCLK_G2D, 4, 0, 0), 2464 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d", 2465 DIV_ENABLE_PCLK_G2D, 3, 0, 0), 2466 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d", 2467 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2468 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d", 2469 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0), 2470 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D, 2471 0, 0, 0), 2472 2473 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ 2474 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d", 2475 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2476}; 2477 2478static const struct samsung_cmu_info g2d_cmu_info __initconst = { 2479 .mux_clks = g2d_mux_clks, 2480 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 2481 .div_clks = g2d_div_clks, 2482 .nr_div_clks = ARRAY_SIZE(g2d_div_clks), 2483 .gate_clks = g2d_gate_clks, 2484 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), 2485 .nr_clk_ids = CLKS_NR_G2D, 2486 .clk_regs = g2d_clk_regs, 2487 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 2488 .suspend_regs = g2d_suspend_regs, 2489 .nr_suspend_regs = ARRAY_SIZE(g2d_suspend_regs), 2490 .clk_name = "aclk_g2d_400", 2491}; 2492 2493/* 2494 * Register offset definitions for CMU_DISP 2495 */ 2496#define DISP_PLL_LOCK 0x0000 2497#define DISP_PLL_CON0 0x0100 2498#define DISP_PLL_CON1 0x0104 2499#define DISP_PLL_FREQ_DET 0x0108 2500#define MUX_SEL_DISP0 0x0200 2501#define MUX_SEL_DISP1 0x0204 2502#define MUX_SEL_DISP2 0x0208 2503#define MUX_SEL_DISP3 0x020c 2504#define MUX_SEL_DISP4 0x0210 2505#define MUX_ENABLE_DISP0 0x0300 2506#define MUX_ENABLE_DISP1 0x0304 2507#define MUX_ENABLE_DISP2 0x0308 2508#define MUX_ENABLE_DISP3 0x030c 2509#define MUX_ENABLE_DISP4 0x0310 2510#define MUX_STAT_DISP0 0x0400 2511#define MUX_STAT_DISP1 0x0404 2512#define MUX_STAT_DISP2 0x0408 2513#define MUX_STAT_DISP3 0x040c 2514#define MUX_STAT_DISP4 0x0410 2515#define MUX_IGNORE_DISP2 0x0508 2516#define DIV_DISP 0x0600 2517#define DIV_DISP_PLL_FREQ_DET 0x0604 2518#define DIV_STAT_DISP 0x0700 2519#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 2520#define ENABLE_ACLK_DISP0 0x0800 2521#define ENABLE_ACLK_DISP1 0x0804 2522#define ENABLE_PCLK_DISP 0x0900 2523#define ENABLE_SCLK_DISP 0x0a00 2524#define ENABLE_IP_DISP0 0x0b00 2525#define ENABLE_IP_DISP1 0x0b04 2526#define CLKOUT_CMU_DISP 0x0c00 2527#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 2528 2529static const unsigned long disp_clk_regs[] __initconst = { 2530 DISP_PLL_LOCK, 2531 DISP_PLL_CON0, 2532 DISP_PLL_CON1, 2533 DISP_PLL_FREQ_DET, 2534 MUX_SEL_DISP0, 2535 MUX_SEL_DISP1, 2536 MUX_SEL_DISP2, 2537 MUX_SEL_DISP3, 2538 MUX_SEL_DISP4, 2539 MUX_ENABLE_DISP0, 2540 MUX_ENABLE_DISP1, 2541 MUX_ENABLE_DISP2, 2542 MUX_ENABLE_DISP3, 2543 MUX_ENABLE_DISP4, 2544 MUX_IGNORE_DISP2, 2545 DIV_DISP, 2546 DIV_DISP_PLL_FREQ_DET, 2547 ENABLE_ACLK_DISP0, 2548 ENABLE_ACLK_DISP1, 2549 ENABLE_PCLK_DISP, 2550 ENABLE_SCLK_DISP, 2551 ENABLE_IP_DISP0, 2552 ENABLE_IP_DISP1, 2553 CLKOUT_CMU_DISP, 2554 CLKOUT_CMU_DISP_DIV_STAT, 2555}; 2556 2557static const struct samsung_clk_reg_dump disp_suspend_regs[] = { 2558 /* PLL has to be enabled for suspend */ 2559 { DISP_PLL_CON0, 0x85f40502 }, 2560 /* ignore status of external PHY muxes during suspend to avoid hangs */ 2561 { MUX_IGNORE_DISP2, 0x00111111 }, 2562 { MUX_SEL_DISP0, 0 }, 2563 { MUX_SEL_DISP1, 0 }, 2564 { MUX_SEL_DISP2, 0 }, 2565 { MUX_SEL_DISP3, 0 }, 2566 { MUX_SEL_DISP4, 0 }, 2567}; 2568 2569/* list of all parent clock list */ 2570PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; 2571PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; 2572PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", }; 2573PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", }; 2574PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk", 2575 "sclk_decon_tv_eclk_disp", }; 2576PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk", 2577 "sclk_decon_vclk_disp", }; 2578PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk", 2579 "sclk_decon_eclk_disp", }; 2580PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk", 2581 "sclk_decon_tv_vclk_disp", }; 2582PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", }; 2583 2584PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk", 2585 "phyclk_mipidphy1_bitclkdiv8_phy", }; 2586PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk", 2587 "phyclk_mipidphy1_rxclkesc0_phy", }; 2588PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk", 2589 "phyclk_mipidphy0_bitclkdiv8_phy", }; 2590PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk", 2591 "phyclk_mipidphy0_rxclkesc0_phy", }; 2592PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk", 2593 "phyclk_hdmiphy_tmds_clko_phy", }; 2594PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk", 2595 "phyclk_hdmiphy_pixel_clko_phy", }; 2596 2597PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll", 2598 "mout_sclk_dsim0_user", }; 2599PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll", 2600 "mout_sclk_decon_tv_eclk_user", }; 2601PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll", 2602 "mout_sclk_decon_vclk_user", }; 2603PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll", 2604 "mout_sclk_decon_eclk_user", }; 2605 2606PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp", 2607 "mout_sclk_dsim1_user", }; 2608PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { 2609 "mout_phyclk_hdmiphy_pixel_clko_user", 2610 "mout_sclk_decon_tv_vclk_b_disp", }; 2611PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", 2612 "mout_sclk_decon_tv_vclk_user", }; 2613 2614static const struct samsung_pll_clock disp_pll_clks[] __initconst = { 2615 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", 2616 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates), 2617}; 2618 2619static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = { 2620 /* 2621 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. 2622 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} 2623 * and sclk_decon_{vclk|tv_vclk}. 2624 */ 2625 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk", 2626 1, 2, 0), 2627 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk", 2628 1, 2, 0), 2629}; 2630 2631static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { 2632 /* PHY clocks from MIPI_DPHY1 */ 2633 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2634 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2635 /* PHY clocks from MIPI_DPHY0 */ 2636 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", 2637 NULL, 0, 188000000), 2638 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", 2639 NULL, 0, 100000000), 2640 /* PHY clocks from HDMI_PHY */ 2641 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2642 NULL, 0, 300000000), 2643 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", 2644 NULL, 0, 166000000), 2645}; 2646 2647static const struct samsung_mux_clock disp_mux_clks[] __initconst = { 2648 /* MUX_SEL_DISP0 */ 2649 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 2650 0, 1), 2651 2652 /* MUX_SEL_DISP1 */ 2653 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user", 2654 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1), 2655 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user", 2656 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1), 2657 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p, 2658 MUX_SEL_DISP1, 20, 1), 2659 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user", 2660 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1), 2661 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user", 2662 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1), 2663 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user", 2664 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1), 2665 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user", 2666 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1), 2667 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 2668 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1), 2669 2670 /* MUX_SEL_DISP2 */ 2671 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 2672 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2673 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2, 2674 20, 1), 2675 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 2676 "mout_phyclk_mipidphy1_rxclkesc0_user", 2677 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2, 2678 16, 1), 2679 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 2680 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2681 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2, 2682 12, 1), 2683 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 2684 "mout_phyclk_mipidphy0_rxclkesc0_user", 2685 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2, 2686 8, 1), 2687 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 2688 "mout_phyclk_hdmiphy_tmds_clko_user", 2689 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2, 2690 4, 1), 2691 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 2692 "mout_phyclk_hdmiphy_pixel_clko_user", 2693 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2, 2694 0, 1), 2695 2696 /* MUX_SEL_DISP3 */ 2697 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p, 2698 MUX_SEL_DISP3, 12, 1), 2699 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk", 2700 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1), 2701 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk", 2702 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1), 2703 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk", 2704 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1), 2705 2706 /* MUX_SEL_DISP4 */ 2707 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp", 2708 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1), 2709 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp", 2710 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1), 2711 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP, 2712 "mout_sclk_decon_tv_vclk_c_disp", 2713 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1), 2714 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP, 2715 "mout_sclk_decon_tv_vclk_b_disp", 2716 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1), 2717 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP, 2718 "mout_sclk_decon_tv_vclk_a_disp", 2719 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), 2720}; 2721 2722static const struct samsung_div_clock disp_div_clks[] __initconst = { 2723 /* DIV_DISP */ 2724 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", 2725 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), 2726 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp", 2727 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3), 2728 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0", 2729 DIV_DISP, 16, 3), 2730 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp", 2731 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3), 2732 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp", 2733 "mout_sclk_decon_vclk", DIV_DISP, 8, 3), 2734 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp", 2735 "mout_sclk_decon_eclk", DIV_DISP, 4, 3), 2736 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user", 2737 DIV_DISP, 0, 2), 2738}; 2739 2740static const struct samsung_gate_clock disp_gate_clks[] __initconst = { 2741 /* ENABLE_ACLK_DISP0 */ 2742 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", 2743 ENABLE_ACLK_DISP0, 2, 0, 0), 2744 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user", 2745 ENABLE_ACLK_DISP0, 0, 0, 0), 2746 2747 /* ENABLE_ACLK_DISP1 */ 2748 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user", 2749 ENABLE_ACLK_DISP1, 25, 0, 0), 2750 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user", 2751 ENABLE_ACLK_DISP1, 24, 0, 0), 2752 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x", 2753 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0), 2754 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x", 2755 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0), 2756 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3", 2757 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0), 2758 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2", 2759 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0), 2760 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1", 2761 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0), 2762 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0", 2763 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0), 2764 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4", 2765 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0), 2766 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3", 2767 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0), 2768 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2", 2769 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0), 2770 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1", 2771 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0), 2772 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0", 2773 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0), 2774 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p", 2775 "div_pclk_disp", ENABLE_ACLK_DISP1, 2776 12, CLK_IGNORE_UNUSED, 0), 2777 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p", 2778 "div_pclk_disp", ENABLE_ACLK_DISP1, 2779 11, CLK_IGNORE_UNUSED, 0), 2780 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p", 2781 "div_pclk_disp", ENABLE_ACLK_DISP1, 2782 10, CLK_IGNORE_UNUSED, 0), 2783 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp", 2784 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0), 2785 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user", 2786 ENABLE_ACLK_DISP1, 7, 0, 0), 2787 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user", 2788 ENABLE_ACLK_DISP1, 6, 0, 0), 2789 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x", 2790 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0), 2791 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x", 2792 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0), 2793 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user", 2794 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0), 2795 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp", 2796 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0), 2797 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333", 2798 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1, 2799 CLK_IGNORE_UNUSED, 0), 2800 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333", 2801 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 2802 0, CLK_IGNORE_UNUSED, 0), 2803 2804 /* ENABLE_PCLK_DISP */ 2805 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp", 2806 ENABLE_PCLK_DISP, 23, 0, 0), 2807 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp", 2808 ENABLE_PCLK_DISP, 22, 0, 0), 2809 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp", 2810 ENABLE_PCLK_DISP, 21, 0, 0), 2811 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp", 2812 ENABLE_PCLK_DISP, 20, 0, 0), 2813 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp", 2814 ENABLE_PCLK_DISP, 19, 0, 0), 2815 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp", 2816 ENABLE_PCLK_DISP, 18, 0, 0), 2817 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp", 2818 ENABLE_PCLK_DISP, 17, 0, 0), 2819 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp", 2820 ENABLE_PCLK_DISP, 16, 0, 0), 2821 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp", 2822 ENABLE_PCLK_DISP, 15, 0, 0), 2823 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp", 2824 ENABLE_PCLK_DISP, 14, 0, 0), 2825 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp", 2826 ENABLE_PCLK_DISP, 13, 0, 0), 2827 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp", 2828 ENABLE_PCLK_DISP, 12, 0, 0), 2829 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp", 2830 ENABLE_PCLK_DISP, 11, 0, 0), 2831 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp", 2832 ENABLE_PCLK_DISP, 10, 0, 0), 2833 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp", 2834 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), 2835 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp", 2836 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), 2837 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp", 2838 ENABLE_PCLK_DISP, 7, 0, 0), 2839 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp", 2840 ENABLE_PCLK_DISP, 6, 0, 0), 2841 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp", 2842 ENABLE_PCLK_DISP, 5, 0, 0), 2843 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp", 2844 ENABLE_PCLK_DISP, 3, 0, 0), 2845 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp", 2846 ENABLE_PCLK_DISP, 2, 0, 0), 2847 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", 2848 ENABLE_PCLK_DISP, 1, 0, 0), 2849 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp", 2850 ENABLE_PCLK_DISP, 0, 0, 0), 2851 2852 /* ENABLE_SCLK_DISP */ 2853 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", 2854 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2855 ENABLE_SCLK_DISP, 26, 0, 0), 2856 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0", 2857 "mout_phyclk_mipidphy1_rxclkesc0_user", 2858 ENABLE_SCLK_DISP, 25, 0, 0), 2859 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1", 2860 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0), 2861 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1", 2862 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0), 2863 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp", 2864 ENABLE_SCLK_DISP, 22, 0, 0), 2865 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk", 2866 "div_sclk_decon_tv_vclk_disp", 2867 ENABLE_SCLK_DISP, 21, 0, 0), 2868 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8", 2869 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2870 ENABLE_SCLK_DISP, 15, 0, 0), 2871 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0", 2872 "mout_phyclk_mipidphy0_rxclkesc0_user", 2873 ENABLE_SCLK_DISP, 14, 0, 0), 2874 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko", 2875 "mout_phyclk_hdmiphy_tmds_clko_user", 2876 ENABLE_SCLK_DISP, 13, 0, 0), 2877 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel", 2878 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0), 2879 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies", 2880 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0), 2881 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0", 2882 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0), 2883 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0", 2884 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0), 2885 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user", 2886 ENABLE_SCLK_DISP, 7, 0, 0), 2887 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp", 2888 ENABLE_SCLK_DISP, 6, 0, 0), 2889 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp", 2890 ENABLE_SCLK_DISP, 5, 0, 0), 2891 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk", 2892 "div_sclk_decon_tv_eclk_disp", 2893 ENABLE_SCLK_DISP, 4, 0, 0), 2894 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", 2895 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0), 2896 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk", 2897 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), 2898}; 2899 2900static const struct samsung_cmu_info disp_cmu_info __initconst = { 2901 .pll_clks = disp_pll_clks, 2902 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), 2903 .mux_clks = disp_mux_clks, 2904 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), 2905 .div_clks = disp_div_clks, 2906 .nr_div_clks = ARRAY_SIZE(disp_div_clks), 2907 .gate_clks = disp_gate_clks, 2908 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), 2909 .fixed_clks = disp_fixed_clks, 2910 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), 2911 .fixed_factor_clks = disp_fixed_factor_clks, 2912 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), 2913 .nr_clk_ids = CLKS_NR_DISP, 2914 .clk_regs = disp_clk_regs, 2915 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 2916 .suspend_regs = disp_suspend_regs, 2917 .nr_suspend_regs = ARRAY_SIZE(disp_suspend_regs), 2918 .clk_name = "aclk_disp_333", 2919}; 2920 2921/* 2922 * Register offset definitions for CMU_AUD 2923 */ 2924#define MUX_SEL_AUD0 0x0200 2925#define MUX_SEL_AUD1 0x0204 2926#define MUX_ENABLE_AUD0 0x0300 2927#define MUX_ENABLE_AUD1 0x0304 2928#define MUX_STAT_AUD0 0x0400 2929#define DIV_AUD0 0x0600 2930#define DIV_AUD1 0x0604 2931#define DIV_STAT_AUD0 0x0700 2932#define DIV_STAT_AUD1 0x0704 2933#define ENABLE_ACLK_AUD 0x0800 2934#define ENABLE_PCLK_AUD 0x0900 2935#define ENABLE_SCLK_AUD0 0x0a00 2936#define ENABLE_SCLK_AUD1 0x0a04 2937#define ENABLE_IP_AUD0 0x0b00 2938#define ENABLE_IP_AUD1 0x0b04 2939 2940static const unsigned long aud_clk_regs[] __initconst = { 2941 MUX_SEL_AUD0, 2942 MUX_SEL_AUD1, 2943 MUX_ENABLE_AUD0, 2944 MUX_ENABLE_AUD1, 2945 DIV_AUD0, 2946 DIV_AUD1, 2947 ENABLE_ACLK_AUD, 2948 ENABLE_PCLK_AUD, 2949 ENABLE_SCLK_AUD0, 2950 ENABLE_SCLK_AUD1, 2951 ENABLE_IP_AUD0, 2952 ENABLE_IP_AUD1, 2953}; 2954 2955static const struct samsung_clk_reg_dump aud_suspend_regs[] = { 2956 { MUX_SEL_AUD0, 0 }, 2957 { MUX_SEL_AUD1, 0 }, 2958}; 2959 2960/* list of all parent clock list */ 2961PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; 2962PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; 2963 2964static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 2965 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), 2966 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), 2967 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), 2968}; 2969 2970static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 2971 /* MUX_SEL_AUD0 */ 2972 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", 2973 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), 2974 2975 /* MUX_SEL_AUD1 */ 2976 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, 2977 MUX_SEL_AUD1, 8, 1), 2978 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p, 2979 MUX_SEL_AUD1, 0, 1), 2980}; 2981 2982static const struct samsung_div_clock aud_div_clks[] __initconst = { 2983 /* DIV_AUD0 */ 2984 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, 2985 12, 4), 2986 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0, 2987 8, 4), 2988 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0, 2989 4, 4), 2990 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 2991 0, 4), 2992 2993 /* DIV_AUD1 */ 2994 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus", 2995 "mout_aud_pll_user", DIV_AUD1, 16, 5), 2996 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user", 2997 DIV_AUD1, 12, 4), 2998 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm", 2999 DIV_AUD1, 4, 8), 3000 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s", 3001 DIV_AUD1, 0, 4), 3002}; 3003 3004static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 3005 /* ENABLE_ACLK_AUD */ 3006 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", 3007 ENABLE_ACLK_AUD, 12, 0, 0), 3008 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud", 3009 ENABLE_ACLK_AUD, 7, 0, 0), 3010 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud", 3011 ENABLE_ACLK_AUD, 0, 4, 0), 3012 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud", 3013 ENABLE_ACLK_AUD, 0, 3, 0), 3014 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud", 3015 ENABLE_ACLK_AUD, 0, 2, 0), 3016 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD, 3017 0, 1, 0), 3018 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD, 3019 0, CLK_IGNORE_UNUSED, 0), 3020 3021 /* ENABLE_PCLK_AUD */ 3022 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, 3023 13, 0, 0), 3024 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, 3025 12, 0, 0), 3026 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, 3027 11, 0, 0), 3028 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud", 3029 ENABLE_PCLK_AUD, 10, 0, 0), 3030 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud", 3031 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), 3032 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud", 3033 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), 3034 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud", 3035 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0), 3036 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud", 3037 ENABLE_PCLK_AUD, 6, 0, 0), 3038 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud", 3039 ENABLE_PCLK_AUD, 5, 0, 0), 3040 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud", 3041 ENABLE_PCLK_AUD, 4, 0, 0), 3042 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud", 3043 ENABLE_PCLK_AUD, 3, 0, 0), 3044 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD, 3045 2, 0, 0), 3046 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud", 3047 ENABLE_PCLK_AUD, 0, 0, 0), 3048 3049 /* ENABLE_SCLK_AUD0 */ 3050 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, 3051 2, CLK_IGNORE_UNUSED, 0), 3052 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", 3053 ENABLE_SCLK_AUD0, 1, 0, 0), 3054 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, 3055 0, 0, 0), 3056 3057 /* ENABLE_SCLK_AUD1 */ 3058 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk", 3059 ENABLE_SCLK_AUD1, 6, 0, 0), 3060 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk", 3061 ENABLE_SCLK_AUD1, 5, 0, 0), 3062 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", 3063 ENABLE_SCLK_AUD1, 4, 0, 0), 3064 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", 3065 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0), 3066 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", 3067 ENABLE_SCLK_AUD1, 2, 0, 0), 3068 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", 3069 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0), 3070 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s", 3071 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), 3072}; 3073 3074static const struct samsung_cmu_info aud_cmu_info __initconst = { 3075 .mux_clks = aud_mux_clks, 3076 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 3077 .div_clks = aud_div_clks, 3078 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 3079 .gate_clks = aud_gate_clks, 3080 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 3081 .fixed_clks = aud_fixed_clks, 3082 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 3083 .nr_clk_ids = CLKS_NR_AUD, 3084 .clk_regs = aud_clk_regs, 3085 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 3086 .suspend_regs = aud_suspend_regs, 3087 .nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs), 3088 .clk_name = "fout_aud_pll", 3089}; 3090 3091/* 3092 * Register offset definitions for CMU_BUS{0|1|2} 3093 */ 3094#define DIV_BUS 0x0600 3095#define DIV_STAT_BUS 0x0700 3096#define ENABLE_ACLK_BUS 0x0800 3097#define ENABLE_PCLK_BUS 0x0900 3098#define ENABLE_IP_BUS0 0x0b00 3099#define ENABLE_IP_BUS1 0x0b04 3100 3101#define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */ 3102#define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */ 3103#define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */ 3104 3105/* list of all parent clock list */ 3106PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; 3107 3108#define CMU_BUS_COMMON_CLK_REGS \ 3109 DIV_BUS, \ 3110 ENABLE_ACLK_BUS, \ 3111 ENABLE_PCLK_BUS, \ 3112 ENABLE_IP_BUS0, \ 3113 ENABLE_IP_BUS1 3114 3115static const unsigned long bus01_clk_regs[] __initconst = { 3116 CMU_BUS_COMMON_CLK_REGS, 3117}; 3118 3119static const unsigned long bus2_clk_regs[] __initconst = { 3120 MUX_SEL_BUS2, 3121 MUX_ENABLE_BUS2, 3122 CMU_BUS_COMMON_CLK_REGS, 3123}; 3124 3125static const struct samsung_div_clock bus0_div_clks[] __initconst = { 3126 /* DIV_BUS0 */ 3127 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", 3128 DIV_BUS, 0, 3), 3129}; 3130 3131/* CMU_BUS0 clocks */ 3132static const struct samsung_gate_clock bus0_gate_clks[] __initconst = { 3133 /* ENABLE_ACLK_BUS0 */ 3134 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", 3135 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3136 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133", 3137 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3138 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400", 3139 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3140 3141 /* ENABLE_PCLK_BUS0 */ 3142 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133", 3143 ENABLE_PCLK_BUS, 2, 0, 0), 3144 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133", 3145 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3146 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133", 3147 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3148}; 3149 3150/* CMU_BUS1 clocks */ 3151static const struct samsung_div_clock bus1_div_clks[] __initconst = { 3152 /* DIV_BUS1 */ 3153 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", 3154 DIV_BUS, 0, 3), 3155}; 3156 3157static const struct samsung_gate_clock bus1_gate_clks[] __initconst = { 3158 /* ENABLE_ACLK_BUS1 */ 3159 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", 3160 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3161 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133", 3162 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3163 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400", 3164 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3165 3166 /* ENABLE_PCLK_BUS1 */ 3167 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133", 3168 ENABLE_PCLK_BUS, 2, 0, 0), 3169 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133", 3170 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3171 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133", 3172 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3173}; 3174 3175/* CMU_BUS2 clocks */ 3176static const struct samsung_mux_clock bus2_mux_clks[] __initconst = { 3177 /* MUX_SEL_BUS2 */ 3178 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", 3179 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), 3180}; 3181 3182static const struct samsung_div_clock bus2_div_clks[] __initconst = { 3183 /* DIV_BUS2 */ 3184 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", 3185 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), 3186}; 3187 3188static const struct samsung_gate_clock bus2_gate_clks[] __initconst = { 3189 /* ENABLE_ACLK_BUS2 */ 3190 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", 3191 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), 3192 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133", 3193 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3194 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400", 3195 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3196 1, CLK_IGNORE_UNUSED, 0), 3197 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400", 3198 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3199 0, CLK_IGNORE_UNUSED, 0), 3200 3201 /* ENABLE_PCLK_BUS2 */ 3202 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133", 3203 ENABLE_PCLK_BUS, 2, 0, 0), 3204 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133", 3205 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3206 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133", 3207 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3208}; 3209 3210#define CMU_BUS_INFO_CLKS(id) \ 3211 .div_clks = bus##id##_div_clks, \ 3212 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ 3213 .gate_clks = bus##id##_gate_clks, \ 3214 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ 3215 .nr_clk_ids = CLKS_NR_BUSX 3216 3217static const struct samsung_cmu_info bus0_cmu_info __initconst = { 3218 CMU_BUS_INFO_CLKS(0), 3219 .clk_regs = bus01_clk_regs, 3220 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3221}; 3222 3223static const struct samsung_cmu_info bus1_cmu_info __initconst = { 3224 CMU_BUS_INFO_CLKS(1), 3225 .clk_regs = bus01_clk_regs, 3226 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3227}; 3228 3229static const struct samsung_cmu_info bus2_cmu_info __initconst = { 3230 CMU_BUS_INFO_CLKS(2), 3231 .mux_clks = bus2_mux_clks, 3232 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), 3233 .clk_regs = bus2_clk_regs, 3234 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs), 3235}; 3236 3237#define exynos5433_cmu_bus_init(id) \ 3238static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\ 3239{ \ 3240 samsung_cmu_register_one(np, &bus##id##_cmu_info); \ 3241} \ 3242CLK_OF_DECLARE(exynos5433_cmu_bus##id, \ 3243 "samsung,exynos5433-cmu-bus"#id, \ 3244 exynos5433_cmu_bus##id##_init) 3245 3246exynos5433_cmu_bus_init(0); 3247exynos5433_cmu_bus_init(1); 3248exynos5433_cmu_bus_init(2); 3249 3250/* 3251 * Register offset definitions for CMU_G3D 3252 */ 3253#define G3D_PLL_LOCK 0x0000 3254#define G3D_PLL_CON0 0x0100 3255#define G3D_PLL_CON1 0x0104 3256#define G3D_PLL_FREQ_DET 0x010c 3257#define MUX_SEL_G3D 0x0200 3258#define MUX_ENABLE_G3D 0x0300 3259#define MUX_STAT_G3D 0x0400 3260#define DIV_G3D 0x0600 3261#define DIV_G3D_PLL_FREQ_DET 0x0604 3262#define DIV_STAT_G3D 0x0700 3263#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704 3264#define ENABLE_ACLK_G3D 0x0800 3265#define ENABLE_PCLK_G3D 0x0900 3266#define ENABLE_SCLK_G3D 0x0a00 3267#define ENABLE_IP_G3D0 0x0b00 3268#define ENABLE_IP_G3D1 0x0b04 3269#define CLKOUT_CMU_G3D 0x0c00 3270#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 3271#define CLK_STOPCTRL 0x1000 3272 3273static const unsigned long g3d_clk_regs[] __initconst = { 3274 G3D_PLL_LOCK, 3275 G3D_PLL_CON0, 3276 G3D_PLL_CON1, 3277 G3D_PLL_FREQ_DET, 3278 MUX_SEL_G3D, 3279 MUX_ENABLE_G3D, 3280 DIV_G3D, 3281 DIV_G3D_PLL_FREQ_DET, 3282 ENABLE_ACLK_G3D, 3283 ENABLE_PCLK_G3D, 3284 ENABLE_SCLK_G3D, 3285 ENABLE_IP_G3D0, 3286 ENABLE_IP_G3D1, 3287 CLKOUT_CMU_G3D, 3288 CLKOUT_CMU_G3D_DIV_STAT, 3289 CLK_STOPCTRL, 3290}; 3291 3292static const struct samsung_clk_reg_dump g3d_suspend_regs[] = { 3293 { MUX_SEL_G3D, 0 }, 3294}; 3295 3296/* list of all parent clock list */ 3297PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; 3298PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; 3299 3300static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 3301 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 3302 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates), 3303}; 3304 3305static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 3306 /* MUX_SEL_G3D */ 3307 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, 3308 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), 3309 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 3310 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), 3311}; 3312 3313static const struct samsung_div_clock g3d_div_clks[] __initconst = { 3314 /* DIV_G3D */ 3315 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, 3316 8, 2), 3317 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D, 3318 4, 3), 3319 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D, 3320 0, 3, CLK_SET_RATE_PARENT, 0), 3321}; 3322 3323static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 3324 /* ENABLE_ACLK_G3D */ 3325 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", 3326 ENABLE_ACLK_G3D, 7, 0, 0), 3327 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d", 3328 ENABLE_ACLK_G3D, 6, 0, 0), 3329 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d", 3330 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0), 3331 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d", 3332 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0), 3333 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d", 3334 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0), 3335 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d", 3336 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0), 3337 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d", 3338 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3339 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d", 3340 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0), 3341 3342 /* ENABLE_PCLK_G3D */ 3343 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d", 3344 ENABLE_PCLK_G3D, 3, 0, 0), 3345 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d", 3346 ENABLE_PCLK_G3D, 2, 0, 0), 3347 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d", 3348 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3349 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d", 3350 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0), 3351 3352 /* ENABLE_SCLK_G3D */ 3353 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d", 3354 ENABLE_SCLK_G3D, 0, 0, 0), 3355}; 3356 3357static const struct samsung_cmu_info g3d_cmu_info __initconst = { 3358 .pll_clks = g3d_pll_clks, 3359 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 3360 .mux_clks = g3d_mux_clks, 3361 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 3362 .div_clks = g3d_div_clks, 3363 .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 3364 .gate_clks = g3d_gate_clks, 3365 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 3366 .nr_clk_ids = CLKS_NR_G3D, 3367 .clk_regs = g3d_clk_regs, 3368 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 3369 .suspend_regs = g3d_suspend_regs, 3370 .nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs), 3371 .clk_name = "aclk_g3d_400", 3372}; 3373 3374/* 3375 * Register offset definitions for CMU_GSCL 3376 */ 3377#define MUX_SEL_GSCL 0x0200 3378#define MUX_ENABLE_GSCL 0x0300 3379#define MUX_STAT_GSCL 0x0400 3380#define ENABLE_ACLK_GSCL 0x0800 3381#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804 3382#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808 3383#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c 3384#define ENABLE_PCLK_GSCL 0x0900 3385#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904 3386#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908 3387#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c 3388#define ENABLE_IP_GSCL0 0x0b00 3389#define ENABLE_IP_GSCL1 0x0b04 3390#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 3391#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 3392#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 3393 3394static const unsigned long gscl_clk_regs[] __initconst = { 3395 MUX_SEL_GSCL, 3396 MUX_ENABLE_GSCL, 3397 ENABLE_ACLK_GSCL, 3398 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 3399 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 3400 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 3401 ENABLE_PCLK_GSCL, 3402 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 3403 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 3404 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 3405 ENABLE_IP_GSCL0, 3406 ENABLE_IP_GSCL1, 3407 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0, 3408 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1, 3409 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2, 3410}; 3411 3412static const struct samsung_clk_reg_dump gscl_suspend_regs[] = { 3413 { MUX_SEL_GSCL, 0 }, 3414 { ENABLE_ACLK_GSCL, 0xfff }, 3415 { ENABLE_PCLK_GSCL, 0xff }, 3416}; 3417 3418/* list of all parent clock list */ 3419PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; 3420PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; 3421 3422static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { 3423 /* MUX_SEL_GSCL */ 3424 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", 3425 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), 3426 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", 3427 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), 3428}; 3429 3430static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { 3431 /* ENABLE_ACLK_GSCL */ 3432 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", 3433 ENABLE_ACLK_GSCL, 11, 0, 0), 3434 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user", 3435 ENABLE_ACLK_GSCL, 10, 0, 0), 3436 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user", 3437 ENABLE_ACLK_GSCL, 9, 0, 0), 3438 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp", 3439 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL, 3440 8, CLK_IGNORE_UNUSED, 0), 3441 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user", 3442 ENABLE_ACLK_GSCL, 7, 0, 0), 3443 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", 3444 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), 3445 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", 3446 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 3447 CLK_IGNORE_UNUSED, 0), 3448 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", 3449 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 3450 CLK_IGNORE_UNUSED, 0), 3451 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", 3452 ENABLE_ACLK_GSCL, 3, 0, 0), 3453 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", 3454 ENABLE_ACLK_GSCL, 2, 0, 0), 3455 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user", 3456 ENABLE_ACLK_GSCL, 1, 0, 0), 3457 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user", 3458 ENABLE_ACLK_GSCL, 0, 0, 0), 3459 3460 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */ 3461 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user", 3462 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3463 3464 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */ 3465 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user", 3466 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3467 3468 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */ 3469 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user", 3470 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3471 3472 /* ENABLE_PCLK_GSCL */ 3473 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user", 3474 ENABLE_PCLK_GSCL, 7, 0, 0), 3475 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user", 3476 ENABLE_PCLK_GSCL, 6, 0, 0), 3477 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user", 3478 ENABLE_PCLK_GSCL, 5, 0, 0), 3479 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user", 3480 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0), 3481 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl", 3482 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL, 3483 3, CLK_IGNORE_UNUSED, 0), 3484 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user", 3485 ENABLE_PCLK_GSCL, 2, 0, 0), 3486 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user", 3487 ENABLE_PCLK_GSCL, 1, 0, 0), 3488 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user", 3489 ENABLE_PCLK_GSCL, 0, 0, 0), 3490 3491 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */ 3492 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user", 3493 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3494 3495 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ 3496 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user", 3497 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3498 3499 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ 3500 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user", 3501 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3502}; 3503 3504static const struct samsung_cmu_info gscl_cmu_info __initconst = { 3505 .mux_clks = gscl_mux_clks, 3506 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 3507 .gate_clks = gscl_gate_clks, 3508 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), 3509 .nr_clk_ids = CLKS_NR_GSCL, 3510 .clk_regs = gscl_clk_regs, 3511 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), 3512 .suspend_regs = gscl_suspend_regs, 3513 .nr_suspend_regs = ARRAY_SIZE(gscl_suspend_regs), 3514 .clk_name = "aclk_gscl_111", 3515}; 3516 3517/* 3518 * Register offset definitions for CMU_APOLLO 3519 */ 3520#define APOLLO_PLL_LOCK 0x0000 3521#define APOLLO_PLL_CON0 0x0100 3522#define APOLLO_PLL_CON1 0x0104 3523#define APOLLO_PLL_FREQ_DET 0x010c 3524#define MUX_SEL_APOLLO0 0x0200 3525#define MUX_SEL_APOLLO1 0x0204 3526#define MUX_SEL_APOLLO2 0x0208 3527#define MUX_ENABLE_APOLLO0 0x0300 3528#define MUX_ENABLE_APOLLO1 0x0304 3529#define MUX_ENABLE_APOLLO2 0x0308 3530#define MUX_STAT_APOLLO0 0x0400 3531#define MUX_STAT_APOLLO1 0x0404 3532#define MUX_STAT_APOLLO2 0x0408 3533#define DIV_APOLLO0 0x0600 3534#define DIV_APOLLO1 0x0604 3535#define DIV_APOLLO_PLL_FREQ_DET 0x0608 3536#define DIV_STAT_APOLLO0 0x0700 3537#define DIV_STAT_APOLLO1 0x0704 3538#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708 3539#define ENABLE_ACLK_APOLLO 0x0800 3540#define ENABLE_PCLK_APOLLO 0x0900 3541#define ENABLE_SCLK_APOLLO 0x0a00 3542#define ENABLE_IP_APOLLO0 0x0b00 3543#define ENABLE_IP_APOLLO1 0x0b04 3544#define CLKOUT_CMU_APOLLO 0x0c00 3545#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04 3546#define ARMCLK_STOPCTRL 0x1000 3547#define APOLLO_PWR_CTRL 0x1020 3548#define APOLLO_PWR_CTRL2 0x1024 3549#define APOLLO_INTR_SPREAD_ENABLE 0x1080 3550#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 3551#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 3552 3553static const unsigned long apollo_clk_regs[] __initconst = { 3554 APOLLO_PLL_LOCK, 3555 APOLLO_PLL_CON0, 3556 APOLLO_PLL_CON1, 3557 APOLLO_PLL_FREQ_DET, 3558 MUX_SEL_APOLLO0, 3559 MUX_SEL_APOLLO1, 3560 MUX_SEL_APOLLO2, 3561 MUX_ENABLE_APOLLO0, 3562 MUX_ENABLE_APOLLO1, 3563 MUX_ENABLE_APOLLO2, 3564 DIV_APOLLO0, 3565 DIV_APOLLO1, 3566 DIV_APOLLO_PLL_FREQ_DET, 3567 ENABLE_ACLK_APOLLO, 3568 ENABLE_PCLK_APOLLO, 3569 ENABLE_SCLK_APOLLO, 3570 ENABLE_IP_APOLLO0, 3571 ENABLE_IP_APOLLO1, 3572 CLKOUT_CMU_APOLLO, 3573 CLKOUT_CMU_APOLLO_DIV_STAT, 3574 ARMCLK_STOPCTRL, 3575 APOLLO_PWR_CTRL, 3576 APOLLO_PWR_CTRL2, 3577 APOLLO_INTR_SPREAD_ENABLE, 3578 APOLLO_INTR_SPREAD_USE_STANDBYWFI, 3579 APOLLO_INTR_SPREAD_BLOCKING_DURATION, 3580}; 3581 3582/* list of all parent clock list */ 3583PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", }; 3584PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", }; 3585PNAME(mout_apollo_p) = { "mout_apollo_pll", 3586 "mout_bus_pll_apollo_user", }; 3587 3588static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { 3589 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", 3590 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates), 3591}; 3592 3593static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { 3594 /* MUX_SEL_APOLLO0 */ 3595 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, 3596 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT | 3597 CLK_RECALC_NEW_RATES, 0), 3598 3599 /* MUX_SEL_APOLLO1 */ 3600 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", 3601 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1), 3602 3603 /* MUX_SEL_APOLLO2 */ 3604 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, 3605 0, 1, CLK_SET_RATE_PARENT, 0), 3606}; 3607 3608static const struct samsung_div_clock apollo_div_clks[] __initconst = { 3609 /* DIV_APOLLO0 */ 3610 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", 3611 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, 3612 CLK_DIVIDER_READ_ONLY), 3613 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2", 3614 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE, 3615 CLK_DIVIDER_READ_ONLY), 3616 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2", 3617 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE, 3618 CLK_DIVIDER_READ_ONLY), 3619 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2", 3620 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE, 3621 CLK_DIVIDER_READ_ONLY), 3622 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2", 3623 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, 3624 CLK_DIVIDER_READ_ONLY), 3625 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", 3626 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0), 3627 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", 3628 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0), 3629 3630 /* DIV_APOLLO1 */ 3631 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", 3632 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE, 3633 CLK_DIVIDER_READ_ONLY), 3634 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo", 3635 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE, 3636 CLK_DIVIDER_READ_ONLY), 3637}; 3638 3639static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { 3640 /* ENABLE_ACLK_APOLLO */ 3641 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", 3642 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3643 6, CLK_IGNORE_UNUSED, 0), 3644 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys", 3645 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3646 5, CLK_IGNORE_UNUSED, 0), 3647 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys", 3648 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3649 4, CLK_IGNORE_UNUSED, 0), 3650 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys", 3651 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3652 3, CLK_IGNORE_UNUSED, 0), 3653 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci", 3654 "div_aclk_apollo", ENABLE_ACLK_APOLLO, 3655 2, CLK_IGNORE_UNUSED, 0), 3656 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop", 3657 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3658 1, CLK_IGNORE_UNUSED, 0), 3659 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200", 3660 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3661 0, CLK_IGNORE_UNUSED, 0), 3662 3663 /* ENABLE_PCLK_APOLLO */ 3664 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo", 3665 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO, 3666 2, CLK_IGNORE_UNUSED, 0), 3667 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo", 3668 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3669 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo", 3670 "div_pclk_apollo", ENABLE_PCLK_APOLLO, 3671 0, CLK_IGNORE_UNUSED, 0), 3672 3673 /* ENABLE_SCLK_APOLLO */ 3674 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo", 3675 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), 3676 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", 3677 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3678}; 3679 3680#define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3681 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3682 ((pclk) << 12) | ((aclk) << 8)) 3683 3684#define E5433_APOLLO_DIV1(hpm, copy) \ 3685 (((hpm) << 4) | ((copy) << 0)) 3686 3687static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = { 3688 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3689 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3690 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3691 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3692 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3693 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3694 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3695 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3696 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3697 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3698 { 0 }, 3699}; 3700 3701static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = { 3702 CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL, 3703 CLK_MOUT_BUS_PLL_APOLLO_USER, 0, 0x0, 3704 CPUCLK_LAYOUT_E5433, exynos5433_apolloclk_d), 3705}; 3706 3707static const struct samsung_cmu_info apollo_cmu_info __initconst = { 3708 .pll_clks = apollo_pll_clks, 3709 .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks), 3710 .mux_clks = apollo_mux_clks, 3711 .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks), 3712 .div_clks = apollo_div_clks, 3713 .nr_div_clks = ARRAY_SIZE(apollo_div_clks), 3714 .gate_clks = apollo_gate_clks, 3715 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks), 3716 .cpu_clks = apollo_cpu_clks, 3717 .nr_cpu_clks = ARRAY_SIZE(apollo_cpu_clks), 3718 .nr_clk_ids = CLKS_NR_APOLLO, 3719 .clk_regs = apollo_clk_regs, 3720 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs), 3721}; 3722 3723static void __init exynos5433_cmu_apollo_init(struct device_node *np) 3724{ 3725 samsung_cmu_register_one(np, &apollo_cmu_info); 3726} 3727CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", 3728 exynos5433_cmu_apollo_init); 3729 3730/* 3731 * Register offset definitions for CMU_ATLAS 3732 */ 3733#define ATLAS_PLL_LOCK 0x0000 3734#define ATLAS_PLL_CON0 0x0100 3735#define ATLAS_PLL_CON1 0x0104 3736#define ATLAS_PLL_FREQ_DET 0x010c 3737#define MUX_SEL_ATLAS0 0x0200 3738#define MUX_SEL_ATLAS1 0x0204 3739#define MUX_SEL_ATLAS2 0x0208 3740#define MUX_ENABLE_ATLAS0 0x0300 3741#define MUX_ENABLE_ATLAS1 0x0304 3742#define MUX_ENABLE_ATLAS2 0x0308 3743#define MUX_STAT_ATLAS0 0x0400 3744#define MUX_STAT_ATLAS1 0x0404 3745#define MUX_STAT_ATLAS2 0x0408 3746#define DIV_ATLAS0 0x0600 3747#define DIV_ATLAS1 0x0604 3748#define DIV_ATLAS_PLL_FREQ_DET 0x0608 3749#define DIV_STAT_ATLAS0 0x0700 3750#define DIV_STAT_ATLAS1 0x0704 3751#define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708 3752#define ENABLE_ACLK_ATLAS 0x0800 3753#define ENABLE_PCLK_ATLAS 0x0900 3754#define ENABLE_SCLK_ATLAS 0x0a00 3755#define ENABLE_IP_ATLAS0 0x0b00 3756#define ENABLE_IP_ATLAS1 0x0b04 3757#define CLKOUT_CMU_ATLAS 0x0c00 3758#define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04 3759#define ARMCLK_STOPCTRL 0x1000 3760#define ATLAS_PWR_CTRL 0x1020 3761#define ATLAS_PWR_CTRL2 0x1024 3762#define ATLAS_INTR_SPREAD_ENABLE 0x1080 3763#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 3764#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 3765 3766static const unsigned long atlas_clk_regs[] __initconst = { 3767 ATLAS_PLL_LOCK, 3768 ATLAS_PLL_CON0, 3769 ATLAS_PLL_CON1, 3770 ATLAS_PLL_FREQ_DET, 3771 MUX_SEL_ATLAS0, 3772 MUX_SEL_ATLAS1, 3773 MUX_SEL_ATLAS2, 3774 MUX_ENABLE_ATLAS0, 3775 MUX_ENABLE_ATLAS1, 3776 MUX_ENABLE_ATLAS2, 3777 DIV_ATLAS0, 3778 DIV_ATLAS1, 3779 DIV_ATLAS_PLL_FREQ_DET, 3780 ENABLE_ACLK_ATLAS, 3781 ENABLE_PCLK_ATLAS, 3782 ENABLE_SCLK_ATLAS, 3783 ENABLE_IP_ATLAS0, 3784 ENABLE_IP_ATLAS1, 3785 CLKOUT_CMU_ATLAS, 3786 CLKOUT_CMU_ATLAS_DIV_STAT, 3787 ARMCLK_STOPCTRL, 3788 ATLAS_PWR_CTRL, 3789 ATLAS_PWR_CTRL2, 3790 ATLAS_INTR_SPREAD_ENABLE, 3791 ATLAS_INTR_SPREAD_USE_STANDBYWFI, 3792 ATLAS_INTR_SPREAD_BLOCKING_DURATION, 3793}; 3794 3795/* list of all parent clock list */ 3796PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", }; 3797PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", }; 3798PNAME(mout_atlas_p) = { "mout_atlas_pll", 3799 "mout_bus_pll_atlas_user", }; 3800 3801static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { 3802 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", 3803 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates), 3804}; 3805 3806static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { 3807 /* MUX_SEL_ATLAS0 */ 3808 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, 3809 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT | 3810 CLK_RECALC_NEW_RATES, 0), 3811 3812 /* MUX_SEL_ATLAS1 */ 3813 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", 3814 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1), 3815 3816 /* MUX_SEL_ATLAS2 */ 3817 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2, 3818 0, 1, CLK_SET_RATE_PARENT, 0), 3819}; 3820 3821static const struct samsung_div_clock atlas_div_clks[] __initconst = { 3822 /* DIV_ATLAS0 */ 3823 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", 3824 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, 3825 CLK_DIVIDER_READ_ONLY), 3826 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas", 3827 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE, 3828 CLK_DIVIDER_READ_ONLY), 3829 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2", 3830 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE, 3831 CLK_DIVIDER_READ_ONLY), 3832 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2", 3833 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE, 3834 CLK_DIVIDER_READ_ONLY), 3835 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2", 3836 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE, 3837 CLK_DIVIDER_READ_ONLY), 3838 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1", 3839 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0), 3840 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas", 3841 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0), 3842 3843 /* DIV_ATLAS1 */ 3844 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas", 3845 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE, 3846 CLK_DIVIDER_READ_ONLY), 3847 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas", 3848 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE, 3849 CLK_DIVIDER_READ_ONLY), 3850}; 3851 3852static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { 3853 /* ENABLE_ACLK_ATLAS */ 3854 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", 3855 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3856 9, CLK_IGNORE_UNUSED, 0), 3857 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys", 3858 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3859 8, CLK_IGNORE_UNUSED, 0), 3860 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys", 3861 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3862 7, CLK_IGNORE_UNUSED, 0), 3863 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys", 3864 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3865 6, CLK_IGNORE_UNUSED, 0), 3866 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys", 3867 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3868 5, CLK_IGNORE_UNUSED, 0), 3869 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss", 3870 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3871 4, CLK_IGNORE_UNUSED, 0), 3872 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix", 3873 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS, 3874 3, CLK_IGNORE_UNUSED, 0), 3875 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci", 3876 "div_aclk_atlas", ENABLE_ACLK_ATLAS, 3877 2, CLK_IGNORE_UNUSED, 0), 3878 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas", 3879 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3880 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas", 3881 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3882 3883 /* ENABLE_PCLK_ATLAS */ 3884 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys", 3885 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3886 5, CLK_IGNORE_UNUSED, 0), 3887 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys", 3888 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3889 4, CLK_IGNORE_UNUSED, 0), 3890 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys", 3891 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3892 3, CLK_IGNORE_UNUSED, 0), 3893 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas", 3894 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3895 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas", 3896 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3897 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas", 3898 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3899 3900 /* ENABLE_SCLK_ATLAS */ 3901 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas", 3902 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0), 3903 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas", 3904 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0), 3905 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas", 3906 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0), 3907 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas", 3908 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0), 3909 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas", 3910 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0), 3911 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas", 3912 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0), 3913 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas", 3914 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3915 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", 3916 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3917}; 3918 3919#define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3920 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3921 ((pclk) << 12) | ((aclk) << 8)) 3922 3923#define E5433_ATLAS_DIV1(hpm, copy) \ 3924 (((hpm) << 4) | ((copy) << 0)) 3925 3926static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 3927 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3928 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3929 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3930 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3931 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3932 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3933 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3934 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3935 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3936 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3937 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3938 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3939 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3940 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3941 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3942 { 0 }, 3943}; 3944 3945static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = { 3946 CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL, 3947 CLK_MOUT_BUS_PLL_ATLAS_USER, 0, 0x0, 3948 CPUCLK_LAYOUT_E5433, exynos5433_atlasclk_d), 3949}; 3950 3951static const struct samsung_cmu_info atlas_cmu_info __initconst = { 3952 .pll_clks = atlas_pll_clks, 3953 .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks), 3954 .mux_clks = atlas_mux_clks, 3955 .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks), 3956 .div_clks = atlas_div_clks, 3957 .nr_div_clks = ARRAY_SIZE(atlas_div_clks), 3958 .gate_clks = atlas_gate_clks, 3959 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks), 3960 .cpu_clks = atlas_cpu_clks, 3961 .nr_cpu_clks = ARRAY_SIZE(atlas_cpu_clks), 3962 .nr_clk_ids = CLKS_NR_ATLAS, 3963 .clk_regs = atlas_clk_regs, 3964 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), 3965}; 3966 3967static void __init exynos5433_cmu_atlas_init(struct device_node *np) 3968{ 3969 samsung_cmu_register_one(np, &atlas_cmu_info); 3970} 3971CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", 3972 exynos5433_cmu_atlas_init); 3973 3974/* 3975 * Register offset definitions for CMU_MSCL 3976 */ 3977#define MUX_SEL_MSCL0 0x0200 3978#define MUX_SEL_MSCL1 0x0204 3979#define MUX_ENABLE_MSCL0 0x0300 3980#define MUX_ENABLE_MSCL1 0x0304 3981#define MUX_STAT_MSCL0 0x0400 3982#define MUX_STAT_MSCL1 0x0404 3983#define DIV_MSCL 0x0600 3984#define DIV_STAT_MSCL 0x0700 3985#define ENABLE_ACLK_MSCL 0x0800 3986#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804 3987#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808 3988#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c 3989#define ENABLE_PCLK_MSCL 0x0900 3990#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904 3991#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908 3992#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c 3993#define ENABLE_SCLK_MSCL 0x0a00 3994#define ENABLE_IP_MSCL0 0x0b00 3995#define ENABLE_IP_MSCL1 0x0b04 3996#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08 3997#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c 3998#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 3999 4000static const unsigned long mscl_clk_regs[] __initconst = { 4001 MUX_SEL_MSCL0, 4002 MUX_SEL_MSCL1, 4003 MUX_ENABLE_MSCL0, 4004 MUX_ENABLE_MSCL1, 4005 DIV_MSCL, 4006 ENABLE_ACLK_MSCL, 4007 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 4008 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 4009 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 4010 ENABLE_PCLK_MSCL, 4011 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 4012 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 4013 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 4014 ENABLE_SCLK_MSCL, 4015 ENABLE_IP_MSCL0, 4016 ENABLE_IP_MSCL1, 4017 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0, 4018 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1, 4019 ENABLE_IP_MSCL_SECURE_SMMU_JPEG, 4020}; 4021 4022static const struct samsung_clk_reg_dump mscl_suspend_regs[] = { 4023 { MUX_SEL_MSCL0, 0 }, 4024 { MUX_SEL_MSCL1, 0 }, 4025}; 4026 4027/* list of all parent clock list */ 4028PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", }; 4029PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", }; 4030PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", 4031 "mout_aclk_mscl_400_user", }; 4032 4033static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { 4034 /* MUX_SEL_MSCL0 */ 4035 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", 4036 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), 4037 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user", 4038 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1), 4039 4040 /* MUX_SEL_MSCL1 */ 4041 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p, 4042 MUX_SEL_MSCL1, 0, 1), 4043}; 4044 4045static const struct samsung_div_clock mscl_div_clks[] __initconst = { 4046 /* DIV_MSCL */ 4047 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", 4048 DIV_MSCL, 0, 3), 4049}; 4050 4051static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { 4052 /* ENABLE_ACLK_MSCL */ 4053 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", 4054 ENABLE_ACLK_MSCL, 9, 0, 0), 4055 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1", 4056 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0), 4057 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0", 4058 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0), 4059 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl", 4060 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0), 4061 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user", 4062 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0), 4063 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl", 4064 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4065 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user", 4066 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4067 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user", 4068 ENABLE_ACLK_MSCL, 2, 0, 0), 4069 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user", 4070 ENABLE_ACLK_MSCL, 1, 0, 0), 4071 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user", 4072 ENABLE_ACLK_MSCL, 0, 0, 0), 4073 4074 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4075 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0", 4076 "mout_aclk_mscl_400_user", 4077 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 4078 0, CLK_IGNORE_UNUSED, 0), 4079 4080 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4081 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1", 4082 "mout_aclk_mscl_400_user", 4083 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 4084 0, CLK_IGNORE_UNUSED, 0), 4085 4086 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */ 4087 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user", 4088 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 4089 0, CLK_IGNORE_UNUSED, 0), 4090 4091 /* ENABLE_PCLK_MSCL */ 4092 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl", 4093 ENABLE_PCLK_MSCL, 7, 0, 0), 4094 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl", 4095 ENABLE_PCLK_MSCL, 6, 0, 0), 4096 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl", 4097 ENABLE_PCLK_MSCL, 5, 0, 0), 4098 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl", 4099 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4100 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl", 4101 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4102 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl", 4103 ENABLE_PCLK_MSCL, 2, 0, 0), 4104 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl", 4105 ENABLE_PCLK_MSCL, 1, 0, 0), 4106 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl", 4107 ENABLE_PCLK_MSCL, 0, 0, 0), 4108 4109 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4110 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl", 4111 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 4112 0, CLK_IGNORE_UNUSED, 0), 4113 4114 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4115 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl", 4116 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 4117 0, CLK_IGNORE_UNUSED, 0), 4118 4119 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */ 4120 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl", 4121 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 4122 0, CLK_IGNORE_UNUSED, 0), 4123 4124 /* ENABLE_SCLK_MSCL */ 4125 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0, 4126 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 4127}; 4128 4129static const struct samsung_cmu_info mscl_cmu_info __initconst = { 4130 .mux_clks = mscl_mux_clks, 4131 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 4132 .div_clks = mscl_div_clks, 4133 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 4134 .gate_clks = mscl_gate_clks, 4135 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 4136 .nr_clk_ids = CLKS_NR_MSCL, 4137 .clk_regs = mscl_clk_regs, 4138 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 4139 .suspend_regs = mscl_suspend_regs, 4140 .nr_suspend_regs = ARRAY_SIZE(mscl_suspend_regs), 4141 .clk_name = "aclk_mscl_400", 4142}; 4143 4144/* 4145 * Register offset definitions for CMU_MFC 4146 */ 4147#define MUX_SEL_MFC 0x0200 4148#define MUX_ENABLE_MFC 0x0300 4149#define MUX_STAT_MFC 0x0400 4150#define DIV_MFC 0x0600 4151#define DIV_STAT_MFC 0x0700 4152#define ENABLE_ACLK_MFC 0x0800 4153#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804 4154#define ENABLE_PCLK_MFC 0x0900 4155#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904 4156#define ENABLE_IP_MFC0 0x0b00 4157#define ENABLE_IP_MFC1 0x0b04 4158#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 4159 4160static const unsigned long mfc_clk_regs[] __initconst = { 4161 MUX_SEL_MFC, 4162 MUX_ENABLE_MFC, 4163 DIV_MFC, 4164 ENABLE_ACLK_MFC, 4165 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4166 ENABLE_PCLK_MFC, 4167 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4168 ENABLE_IP_MFC0, 4169 ENABLE_IP_MFC1, 4170 ENABLE_IP_MFC_SECURE_SMMU_MFC, 4171}; 4172 4173static const struct samsung_clk_reg_dump mfc_suspend_regs[] = { 4174 { MUX_SEL_MFC, 0 }, 4175}; 4176 4177PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; 4178 4179static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 4180 /* MUX_SEL_MFC */ 4181 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", 4182 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), 4183}; 4184 4185static const struct samsung_div_clock mfc_div_clks[] __initconst = { 4186 /* DIV_MFC */ 4187 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", 4188 DIV_MFC, 0, 2), 4189}; 4190 4191static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 4192 /* ENABLE_ACLK_MFC */ 4193 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", 4194 ENABLE_ACLK_MFC, 6, 0, 0), 4195 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user", 4196 ENABLE_ACLK_MFC, 5, 0, 0), 4197 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc", 4198 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4199 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user", 4200 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0), 4201 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc", 4202 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4203 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user", 4204 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4205 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user", 4206 ENABLE_ACLK_MFC, 0, 0, 0), 4207 4208 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */ 4209 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user", 4210 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4211 1, CLK_IGNORE_UNUSED, 0), 4212 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user", 4213 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4214 0, CLK_IGNORE_UNUSED, 0), 4215 4216 /* ENABLE_PCLK_MFC */ 4217 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc", 4218 ENABLE_PCLK_MFC, 4, 0, 0), 4219 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc", 4220 ENABLE_PCLK_MFC, 3, 0, 0), 4221 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc", 4222 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4223 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc", 4224 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4225 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc", 4226 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4227 4228 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */ 4229 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc", 4230 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4231 1, CLK_IGNORE_UNUSED, 0), 4232 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc", 4233 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4234 0, CLK_IGNORE_UNUSED, 0), 4235}; 4236 4237static const struct samsung_cmu_info mfc_cmu_info __initconst = { 4238 .mux_clks = mfc_mux_clks, 4239 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 4240 .div_clks = mfc_div_clks, 4241 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 4242 .gate_clks = mfc_gate_clks, 4243 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 4244 .nr_clk_ids = CLKS_NR_MFC, 4245 .clk_regs = mfc_clk_regs, 4246 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 4247 .suspend_regs = mfc_suspend_regs, 4248 .nr_suspend_regs = ARRAY_SIZE(mfc_suspend_regs), 4249 .clk_name = "aclk_mfc_400", 4250}; 4251 4252/* 4253 * Register offset definitions for CMU_HEVC 4254 */ 4255#define MUX_SEL_HEVC 0x0200 4256#define MUX_ENABLE_HEVC 0x0300 4257#define MUX_STAT_HEVC 0x0400 4258#define DIV_HEVC 0x0600 4259#define DIV_STAT_HEVC 0x0700 4260#define ENABLE_ACLK_HEVC 0x0800 4261#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804 4262#define ENABLE_PCLK_HEVC 0x0900 4263#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904 4264#define ENABLE_IP_HEVC0 0x0b00 4265#define ENABLE_IP_HEVC1 0x0b04 4266#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 4267 4268static const unsigned long hevc_clk_regs[] __initconst = { 4269 MUX_SEL_HEVC, 4270 MUX_ENABLE_HEVC, 4271 DIV_HEVC, 4272 ENABLE_ACLK_HEVC, 4273 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4274 ENABLE_PCLK_HEVC, 4275 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4276 ENABLE_IP_HEVC0, 4277 ENABLE_IP_HEVC1, 4278 ENABLE_IP_HEVC_SECURE_SMMU_HEVC, 4279}; 4280 4281static const struct samsung_clk_reg_dump hevc_suspend_regs[] = { 4282 { MUX_SEL_HEVC, 0 }, 4283}; 4284 4285PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; 4286 4287static const struct samsung_mux_clock hevc_mux_clks[] __initconst = { 4288 /* MUX_SEL_HEVC */ 4289 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", 4290 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), 4291}; 4292 4293static const struct samsung_div_clock hevc_div_clks[] __initconst = { 4294 /* DIV_HEVC */ 4295 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", 4296 DIV_HEVC, 0, 2), 4297}; 4298 4299static const struct samsung_gate_clock hevc_gate_clks[] __initconst = { 4300 /* ENABLE_ACLK_HEVC */ 4301 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", 4302 ENABLE_ACLK_HEVC, 6, 0, 0), 4303 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user", 4304 ENABLE_ACLK_HEVC, 5, 0, 0), 4305 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc", 4306 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4307 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user", 4308 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0), 4309 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc", 4310 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4311 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user", 4312 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4313 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user", 4314 ENABLE_ACLK_HEVC, 0, 0, 0), 4315 4316 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */ 4317 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1", 4318 "mout_aclk_hevc_400_user", 4319 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4320 1, CLK_IGNORE_UNUSED, 0), 4321 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0", 4322 "mout_aclk_hevc_400_user", 4323 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4324 0, CLK_IGNORE_UNUSED, 0), 4325 4326 /* ENABLE_PCLK_HEVC */ 4327 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc", 4328 ENABLE_PCLK_HEVC, 4, 0, 0), 4329 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc", 4330 ENABLE_PCLK_HEVC, 3, 0, 0), 4331 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc", 4332 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4333 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc", 4334 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4335 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc", 4336 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4337 4338 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */ 4339 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc", 4340 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4341 1, CLK_IGNORE_UNUSED, 0), 4342 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc", 4343 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4344 0, CLK_IGNORE_UNUSED, 0), 4345}; 4346 4347static const struct samsung_cmu_info hevc_cmu_info __initconst = { 4348 .mux_clks = hevc_mux_clks, 4349 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), 4350 .div_clks = hevc_div_clks, 4351 .nr_div_clks = ARRAY_SIZE(hevc_div_clks), 4352 .gate_clks = hevc_gate_clks, 4353 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks), 4354 .nr_clk_ids = CLKS_NR_HEVC, 4355 .clk_regs = hevc_clk_regs, 4356 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs), 4357 .suspend_regs = hevc_suspend_regs, 4358 .nr_suspend_regs = ARRAY_SIZE(hevc_suspend_regs), 4359 .clk_name = "aclk_hevc_400", 4360}; 4361 4362/* 4363 * Register offset definitions for CMU_ISP 4364 */ 4365#define MUX_SEL_ISP 0x0200 4366#define MUX_ENABLE_ISP 0x0300 4367#define MUX_STAT_ISP 0x0400 4368#define DIV_ISP 0x0600 4369#define DIV_STAT_ISP 0x0700 4370#define ENABLE_ACLK_ISP0 0x0800 4371#define ENABLE_ACLK_ISP1 0x0804 4372#define ENABLE_ACLK_ISP2 0x0808 4373#define ENABLE_PCLK_ISP 0x0900 4374#define ENABLE_SCLK_ISP 0x0a00 4375#define ENABLE_IP_ISP0 0x0b00 4376#define ENABLE_IP_ISP1 0x0b04 4377#define ENABLE_IP_ISP2 0x0b08 4378#define ENABLE_IP_ISP3 0x0b0c 4379 4380static const unsigned long isp_clk_regs[] __initconst = { 4381 MUX_SEL_ISP, 4382 MUX_ENABLE_ISP, 4383 DIV_ISP, 4384 ENABLE_ACLK_ISP0, 4385 ENABLE_ACLK_ISP1, 4386 ENABLE_ACLK_ISP2, 4387 ENABLE_PCLK_ISP, 4388 ENABLE_SCLK_ISP, 4389 ENABLE_IP_ISP0, 4390 ENABLE_IP_ISP1, 4391 ENABLE_IP_ISP2, 4392 ENABLE_IP_ISP3, 4393}; 4394 4395static const struct samsung_clk_reg_dump isp_suspend_regs[] = { 4396 { MUX_SEL_ISP, 0 }, 4397}; 4398 4399PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; 4400PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; 4401 4402static const struct samsung_mux_clock isp_mux_clks[] __initconst = { 4403 /* MUX_SEL_ISP */ 4404 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", 4405 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), 4406 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user", 4407 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), 4408}; 4409 4410static const struct samsung_div_clock isp_div_clks[] __initconst = { 4411 /* DIV_ISP */ 4412 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", 4413 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), 4414 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user", 4415 DIV_ISP, 8, 3), 4416 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200", 4417 "mout_aclk_isp_400_user", DIV_ISP, 4, 3), 4418 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200", 4419 "mout_aclk_isp_400_user", DIV_ISP, 0, 3), 4420}; 4421 4422static const struct samsung_gate_clock isp_gate_clks[] __initconst = { 4423 /* ENABLE_ACLK_ISP0 */ 4424 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", 4425 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), 4426 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user", 4427 ENABLE_ACLK_ISP0, 5, 0, 0), 4428 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user", 4429 ENABLE_ACLK_ISP0, 4, 0, 0), 4430 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user", 4431 ENABLE_ACLK_ISP0, 3, 0, 0), 4432 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user", 4433 ENABLE_ACLK_ISP0, 2, 0, 0), 4434 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user", 4435 ENABLE_ACLK_ISP0, 1, 0, 0), 4436 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user", 4437 ENABLE_ACLK_ISP0, 0, 0, 0), 4438 4439 /* ENABLE_ACLK_ISP1 */ 4440 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp", 4441 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4442 17, CLK_IGNORE_UNUSED, 0), 4443 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc", 4444 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4445 16, CLK_IGNORE_UNUSED, 0), 4446 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc", 4447 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4448 15, CLK_IGNORE_UNUSED, 0), 4449 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p", 4450 "div_pclk_isp", ENABLE_ACLK_ISP1, 4451 14, CLK_IGNORE_UNUSED, 0), 4452 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p", 4453 "div_pclk_isp", ENABLE_ACLK_ISP1, 4454 13, CLK_IGNORE_UNUSED, 0), 4455 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1", 4456 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4457 12, CLK_IGNORE_UNUSED, 0), 4458 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0", 4459 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4460 11, CLK_IGNORE_UNUSED, 0), 4461 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1", 4462 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4463 10, CLK_IGNORE_UNUSED, 0), 4464 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0", 4465 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4466 9, CLK_IGNORE_UNUSED, 0), 4467 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p", 4468 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4469 8, CLK_IGNORE_UNUSED, 0), 4470 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p", 4471 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4472 7, CLK_IGNORE_UNUSED, 0), 4473 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp", 4474 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0), 4475 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp", 4476 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0), 4477 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p", 4478 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4479 4, CLK_IGNORE_UNUSED, 0), 4480 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p", 4481 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4482 3, CLK_IGNORE_UNUSED, 0), 4483 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user", 4484 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0), 4485 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user", 4486 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4487 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user", 4488 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4489 4490 /* ENABLE_ACLK_ISP2 */ 4491 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp", 4492 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4493 13, CLK_IGNORE_UNUSED, 0), 4494 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user", 4495 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0), 4496 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user", 4497 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0), 4498 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user", 4499 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0), 4500 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc", 4501 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4502 9, CLK_IGNORE_UNUSED, 0), 4503 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user", 4504 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0), 4505 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user", 4506 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0), 4507 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp", 4508 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4509 6, CLK_IGNORE_UNUSED, 0), 4510 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user", 4511 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0), 4512 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user", 4513 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0), 4514 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user", 4515 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0), 4516 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc", 4517 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4518 2, CLK_IGNORE_UNUSED, 0), 4519 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user", 4520 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0), 4521 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user", 4522 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0), 4523 4524 /* ENABLE_PCLK_ISP */ 4525 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200", 4526 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0), 4527 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200", 4528 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0), 4529 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200", 4530 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0), 4531 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200", 4532 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0), 4533 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200", 4534 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0), 4535 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200", 4536 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0), 4537 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200", 4538 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0), 4539 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp", 4540 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0), 4541 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp", 4542 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0), 4543 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp", 4544 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0), 4545 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp", 4546 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0), 4547 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp", 4548 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0), 4549 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp", 4550 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0), 4551 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp", 4552 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0), 4553 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp", 4554 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0), 4555 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp", 4556 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0), 4557 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp", 4558 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0), 4559 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp", 4560 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0), 4561 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local", 4562 "div_aclk_isp_c_200", ENABLE_PCLK_ISP, 4563 7, CLK_IGNORE_UNUSED, 0), 4564 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200", 4565 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0), 4566 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200", 4567 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0), 4568 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis", 4569 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0), 4570 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200", 4571 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0), 4572 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200", 4573 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0), 4574 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200", 4575 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0), 4576 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200", 4577 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), 4578 4579 /* ENABLE_SCLK_ISP */ 4580 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis", 4581 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4582 5, CLK_IGNORE_UNUSED, 0), 4583 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis", 4584 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4585 4, CLK_IGNORE_UNUSED, 0), 4586 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp", 4587 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4588 3, CLK_IGNORE_UNUSED, 0), 4589 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd", 4590 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4591 2, CLK_IGNORE_UNUSED, 0), 4592 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc", 4593 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4594 1, CLK_IGNORE_UNUSED, 0), 4595 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc", 4596 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4597 0, CLK_IGNORE_UNUSED, 0), 4598}; 4599 4600static const struct samsung_cmu_info isp_cmu_info __initconst = { 4601 .mux_clks = isp_mux_clks, 4602 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), 4603 .div_clks = isp_div_clks, 4604 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 4605 .gate_clks = isp_gate_clks, 4606 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 4607 .nr_clk_ids = CLKS_NR_ISP, 4608 .clk_regs = isp_clk_regs, 4609 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), 4610 .suspend_regs = isp_suspend_regs, 4611 .nr_suspend_regs = ARRAY_SIZE(isp_suspend_regs), 4612 .clk_name = "aclk_isp_400", 4613}; 4614 4615/* 4616 * Register offset definitions for CMU_CAM0 4617 */ 4618#define MUX_SEL_CAM00 0x0200 4619#define MUX_SEL_CAM01 0x0204 4620#define MUX_SEL_CAM02 0x0208 4621#define MUX_SEL_CAM03 0x020c 4622#define MUX_SEL_CAM04 0x0210 4623#define MUX_ENABLE_CAM00 0x0300 4624#define MUX_ENABLE_CAM01 0x0304 4625#define MUX_ENABLE_CAM02 0x0308 4626#define MUX_ENABLE_CAM03 0x030c 4627#define MUX_ENABLE_CAM04 0x0310 4628#define MUX_STAT_CAM00 0x0400 4629#define MUX_STAT_CAM01 0x0404 4630#define MUX_STAT_CAM02 0x0408 4631#define MUX_STAT_CAM03 0x040c 4632#define MUX_STAT_CAM04 0x0410 4633#define MUX_IGNORE_CAM01 0x0504 4634#define DIV_CAM00 0x0600 4635#define DIV_CAM01 0x0604 4636#define DIV_CAM02 0x0608 4637#define DIV_CAM03 0x060c 4638#define DIV_STAT_CAM00 0x0700 4639#define DIV_STAT_CAM01 0x0704 4640#define DIV_STAT_CAM02 0x0708 4641#define DIV_STAT_CAM03 0x070c 4642#define ENABLE_ACLK_CAM00 0X0800 4643#define ENABLE_ACLK_CAM01 0X0804 4644#define ENABLE_ACLK_CAM02 0X0808 4645#define ENABLE_PCLK_CAM0 0X0900 4646#define ENABLE_SCLK_CAM0 0X0a00 4647#define ENABLE_IP_CAM00 0X0b00 4648#define ENABLE_IP_CAM01 0X0b04 4649#define ENABLE_IP_CAM02 0X0b08 4650#define ENABLE_IP_CAM03 0X0b0C 4651 4652static const unsigned long cam0_clk_regs[] __initconst = { 4653 MUX_SEL_CAM00, 4654 MUX_SEL_CAM01, 4655 MUX_SEL_CAM02, 4656 MUX_SEL_CAM03, 4657 MUX_SEL_CAM04, 4658 MUX_ENABLE_CAM00, 4659 MUX_ENABLE_CAM01, 4660 MUX_ENABLE_CAM02, 4661 MUX_ENABLE_CAM03, 4662 MUX_ENABLE_CAM04, 4663 MUX_IGNORE_CAM01, 4664 DIV_CAM00, 4665 DIV_CAM01, 4666 DIV_CAM02, 4667 DIV_CAM03, 4668 ENABLE_ACLK_CAM00, 4669 ENABLE_ACLK_CAM01, 4670 ENABLE_ACLK_CAM02, 4671 ENABLE_PCLK_CAM0, 4672 ENABLE_SCLK_CAM0, 4673 ENABLE_IP_CAM00, 4674 ENABLE_IP_CAM01, 4675 ENABLE_IP_CAM02, 4676 ENABLE_IP_CAM03, 4677}; 4678 4679static const struct samsung_clk_reg_dump cam0_suspend_regs[] = { 4680 { MUX_SEL_CAM00, 0 }, 4681 { MUX_SEL_CAM01, 0 }, 4682 { MUX_SEL_CAM02, 0 }, 4683 { MUX_SEL_CAM03, 0 }, 4684 { MUX_SEL_CAM04, 0 }, 4685}; 4686 4687PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", }; 4688PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", }; 4689PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", }; 4690 4691PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk", 4692 "phyclk_rxbyteclkhs0_s4_phy", }; 4693PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk", 4694 "phyclk_rxbyteclkhs0_s2a_phy", }; 4695 4696PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a", 4697 "mout_aclk_cam0_333_user", }; 4698PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user", 4699 "mout_aclk_cam0_400_user", }; 4700PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a", 4701 "mout_aclk_cam0_333_user", }; 4702PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user", 4703 "mout_aclk_cam0_400_user", }; 4704PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a", 4705 "mout_aclk_cam0_333_user", }; 4706PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user", 4707 "mout_aclk_cam0_400_user", }; 4708PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user", 4709 "mout_aclk_cam0_333_user", }; 4710 4711PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a", 4712 "mout_aclk_cam0_333_user" }; 4713PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user", 4714 "mout_aclk_cam0_400_user", }; 4715PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a", 4716 "mout_aclk_cam0_333_user", }; 4717PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user", 4718 "mout_aclk-cam0_400_user", }; 4719PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a", 4720 "mout_aclk_cam0_333_user", }; 4721PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user", 4722 "mout_aclk_cam0_400_user", }; 4723PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a", 4724 "mout_aclk_cam0_333_user", }; 4725PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user", 4726 "mout_aclk_cam0_400_user", }; 4727 4728PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b", 4729 "div_pclk_lite_d", }; 4730PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a", 4731 "div_pclk_pixelasync_lite_c", }; 4732PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a", 4733 "div_pclk_lite_b", }; 4734PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a", 4735 "mout_aclk_cam0_333_user", }; 4736PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user", 4737 "mout_aclk_cam0_400_user", }; 4738PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = { 4739 "mout_sclk_pixelasync_lite_c_init_a", 4740 "mout_aclk_cam0_400_user", }; 4741PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = { 4742 "mout_aclk_cam0_552_user", 4743 "mout_aclk_cam0_400_user", }; 4744 4745static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = { 4746 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", 4747 NULL, 0, 100000000), 4748 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", 4749 NULL, 0, 100000000), 4750}; 4751 4752static const struct samsung_mux_clock cam0_mux_clks[] __initconst = { 4753 /* MUX_SEL_CAM00 */ 4754 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", 4755 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), 4756 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user", 4757 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1), 4758 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user", 4759 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1), 4760 4761 /* MUX_SEL_CAM01 */ 4762 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER, 4763 "mout_phyclk_rxbyteclkhs0_s4_user", 4764 mout_phyclk_rxbyteclkhs0_s4_user_p, 4765 MUX_SEL_CAM01, 4, 1), 4766 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER, 4767 "mout_phyclk_rxbyteclkhs0_s2a_user", 4768 mout_phyclk_rxbyteclkhs0_s2a_user_p, 4769 MUX_SEL_CAM01, 0, 1), 4770 4771 /* MUX_SEL_CAM02 */ 4772 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p, 4773 MUX_SEL_CAM02, 24, 1), 4774 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p, 4775 MUX_SEL_CAM02, 20, 1), 4776 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p, 4777 MUX_SEL_CAM02, 16, 1), 4778 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p, 4779 MUX_SEL_CAM02, 12, 1), 4780 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p, 4781 MUX_SEL_CAM02, 8, 1), 4782 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p, 4783 MUX_SEL_CAM02, 4, 1), 4784 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p, 4785 MUX_SEL_CAM02, 0, 1), 4786 4787 /* MUX_SEL_CAM03 */ 4788 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p, 4789 MUX_SEL_CAM03, 28, 1), 4790 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p, 4791 MUX_SEL_CAM03, 24, 1), 4792 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p, 4793 MUX_SEL_CAM03, 20, 1), 4794 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p, 4795 MUX_SEL_CAM03, 16, 1), 4796 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p, 4797 MUX_SEL_CAM03, 12, 1), 4798 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p, 4799 MUX_SEL_CAM03, 8, 1), 4800 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p, 4801 MUX_SEL_CAM03, 4, 1), 4802 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p, 4803 MUX_SEL_CAM03, 0, 1), 4804 4805 /* MUX_SEL_CAM04 */ 4806 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c", 4807 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1), 4808 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b", 4809 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1), 4810 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a", 4811 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1), 4812 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b", 4813 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1), 4814 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a", 4815 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1), 4816 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B, 4817 "mout_sclk_pixelasync_lite_c_init_b", 4818 mout_sclk_pixelasync_lite_c_init_b_p, 4819 MUX_SEL_CAM04, 4, 1), 4820 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A, 4821 "mout_sclk_pixelasync_lite_c_init_a", 4822 mout_sclk_pixelasync_lite_c_init_a_p, 4823 MUX_SEL_CAM04, 0, 1), 4824}; 4825 4826static const struct samsung_div_clock cam0_div_clks[] __initconst = { 4827 /* DIV_CAM00 */ 4828 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", 4829 DIV_CAM00, 8, 2), 4830 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400", 4831 DIV_CAM00, 4, 3), 4832 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400", 4833 "mout_aclk_cam0_400", DIV_CAM00, 0, 3), 4834 4835 /* DIV_CAM01 */ 4836 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d", 4837 DIV_CAM01, 20, 2), 4838 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b", 4839 DIV_CAM01, 16, 3), 4840 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b", 4841 DIV_CAM01, 12, 2), 4842 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b", 4843 DIV_CAM01, 8, 3), 4844 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a", 4845 DIV_CAM01, 4, 2), 4846 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b", 4847 DIV_CAM01, 0, 3), 4848 4849 /* DIV_CAM02 */ 4850 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b", 4851 DIV_CAM02, 20, 3), 4852 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b", 4853 DIV_CAM02, 16, 3), 4854 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1", 4855 DIV_CAM02, 12, 2), 4856 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b", 4857 DIV_CAM02, 8, 3), 4858 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0", 4859 DIV_CAM02, 4, 2), 4860 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b", 4861 DIV_CAM02, 0, 3), 4862 4863 /* DIV_CAM03 */ 4864 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c", 4865 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3), 4866 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c", 4867 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2), 4868 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT, 4869 "div_sclk_pixelasync_lite_c_init", 4870 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), 4871}; 4872 4873static const struct samsung_gate_clock cam0_gate_clks[] __initconst = { 4874 /* ENABLE_ACLK_CAM00 */ 4875 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, 4876 6, 0, 0), 4877 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00, 4878 5, 0, 0), 4879 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00, 4880 4, 0, 0), 4881 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00, 4882 3, 0, 0), 4883 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d", 4884 ENABLE_ACLK_CAM00, 2, 0, 0), 4885 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b", 4886 ENABLE_ACLK_CAM00, 1, 0, 0), 4887 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a", 4888 ENABLE_ACLK_CAM00, 0, 0, 0), 4889 4890 /* ENABLE_ACLK_CAM01 */ 4891 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200", 4892 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0), 4893 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400", 4894 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0), 4895 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400", 4896 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0), 4897 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400", 4898 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0), 4899 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1", 4900 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0), 4901 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1", 4902 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0), 4903 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0", 4904 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0), 4905 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0", 4906 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0), 4907 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d", 4908 "div_pclk_lite_d", ENABLE_ACLK_CAM01, 4909 23, CLK_IGNORE_UNUSED, 0), 4910 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d", 4911 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4912 22, CLK_IGNORE_UNUSED, 0), 4913 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b", 4914 "div_pclk_lite_b", ENABLE_ACLK_CAM01, 4915 21, CLK_IGNORE_UNUSED, 0), 4916 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b", 4917 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4918 20, CLK_IGNORE_UNUSED, 0), 4919 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a", 4920 "div_pclk_lite_a", ENABLE_ACLK_CAM01, 4921 19, CLK_IGNORE_UNUSED, 0), 4922 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a", 4923 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4924 18, CLK_IGNORE_UNUSED, 0), 4925 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p", 4926 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4927 17, CLK_IGNORE_UNUSED, 0), 4928 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1", 4929 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4930 16, CLK_IGNORE_UNUSED, 0), 4931 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1", 4932 "div_aclk_3aa1", ENABLE_ACLK_CAM01, 4933 15, CLK_IGNORE_UNUSED, 0), 4934 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0", 4935 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4936 14, CLK_IGNORE_UNUSED, 0), 4937 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0", 4938 "div_aclk_3aa0", ENABLE_ACLK_CAM01, 4939 13, CLK_IGNORE_UNUSED, 0), 4940 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d", 4941 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4942 12, CLK_IGNORE_UNUSED, 0), 4943 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d", 4944 "div_aclk_lite_d", ENABLE_ACLK_CAM01, 4945 11, CLK_IGNORE_UNUSED, 0), 4946 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b", 4947 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4948 10, CLK_IGNORE_UNUSED, 0), 4949 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b", 4950 "div_aclk_lite_b", ENABLE_ACLK_CAM01, 4951 9, CLK_IGNORE_UNUSED, 0), 4952 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a", 4953 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4954 8, CLK_IGNORE_UNUSED, 0), 4955 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a", 4956 "div_aclk_lite_a", ENABLE_ACLK_CAM01, 4957 7, CLK_IGNORE_UNUSED, 0), 4958 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp", 4959 "div_pclk_cam0_50", ENABLE_ACLK_CAM01, 4960 6, CLK_IGNORE_UNUSED, 0), 4961 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200", 4962 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0), 4963 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200", 4964 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0), 4965 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200", 4966 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0), 4967 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400", 4968 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0), 4969 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200", 4970 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0), 4971 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400", 4972 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0), 4973 4974 /* ENABLE_ACLK_CAM02 */ 4975 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400", 4976 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0), 4977 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400", 4978 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0), 4979 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400", 4980 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0), 4981 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400", 4982 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0), 4983 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400", 4984 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0), 4985 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400", 4986 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0), 4987 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400", 4988 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0), 4989 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400", 4990 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0), 4991 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400", 4992 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0), 4993 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400", 4994 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0), 4995 4996 /* ENABLE_PCLK_CAM0 */ 4997 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200", 4998 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0), 4999 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200", 5000 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0), 5001 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200", 5002 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0), 5003 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200", 5004 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0), 5005 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200", 5006 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0), 5007 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50", 5008 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0), 5009 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50", 5010 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0), 5011 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50", 5012 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0), 5013 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50", 5014 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0), 5015 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50", 5016 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0), 5017 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50", 5018 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0), 5019 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50", 5020 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0), 5021 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50", 5022 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0), 5023 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d", 5024 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 5025 12, CLK_IGNORE_UNUSED, 0), 5026 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b", 5027 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 5028 11, CLK_IGNORE_UNUSED, 0), 5029 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a", 5030 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 5031 10, CLK_IGNORE_UNUSED, 0), 5032 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50", 5033 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0), 5034 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50", 5035 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0), 5036 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local", 5037 "div_aclk_cam0_200", ENABLE_PCLK_CAM0, 5038 7, CLK_IGNORE_UNUSED, 0), 5039 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200", 5040 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0), 5041 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200", 5042 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0), 5043 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1", 5044 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0), 5045 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0", 5046 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0), 5047 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d", 5048 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0), 5049 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b", 5050 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0), 5051 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a", 5052 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0), 5053 5054 /* ENABLE_SCLK_CAM0 */ 5055 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4", 5056 "mout_phyclk_rxbyteclkhs0_s4_user", 5057 ENABLE_SCLK_CAM0, 8, 0, 0), 5058 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a", 5059 "mout_phyclk_rxbyteclkhs0_s2a_user", 5060 ENABLE_SCLK_CAM0, 7, 0, 0), 5061 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt", 5062 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0), 5063 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1", 5064 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0), 5065 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0", 5066 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0), 5067 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0", 5068 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0), 5069 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c", 5070 "div_sclk_pixelasync_lite_c", 5071 ENABLE_SCLK_CAM0, 2, 0, 0), 5072 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init", 5073 "div_sclk_pixelasync_lite_c_init", 5074 ENABLE_SCLK_CAM0, 1, 0, 0), 5075 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init", 5076 "div_sclk_pixelasync_lite_c", 5077 ENABLE_SCLK_CAM0, 0, 0, 0), 5078}; 5079 5080static const struct samsung_cmu_info cam0_cmu_info __initconst = { 5081 .mux_clks = cam0_mux_clks, 5082 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), 5083 .div_clks = cam0_div_clks, 5084 .nr_div_clks = ARRAY_SIZE(cam0_div_clks), 5085 .gate_clks = cam0_gate_clks, 5086 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks), 5087 .fixed_clks = cam0_fixed_clks, 5088 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks), 5089 .nr_clk_ids = CLKS_NR_CAM0, 5090 .clk_regs = cam0_clk_regs, 5091 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs), 5092 .suspend_regs = cam0_suspend_regs, 5093 .nr_suspend_regs = ARRAY_SIZE(cam0_suspend_regs), 5094 .clk_name = "aclk_cam0_400", 5095}; 5096 5097/* 5098 * Register offset definitions for CMU_CAM1 5099 */ 5100#define MUX_SEL_CAM10 0x0200 5101#define MUX_SEL_CAM11 0x0204 5102#define MUX_SEL_CAM12 0x0208 5103#define MUX_ENABLE_CAM10 0x0300 5104#define MUX_ENABLE_CAM11 0x0304 5105#define MUX_ENABLE_CAM12 0x0308 5106#define MUX_STAT_CAM10 0x0400 5107#define MUX_STAT_CAM11 0x0404 5108#define MUX_STAT_CAM12 0x0408 5109#define MUX_IGNORE_CAM11 0x0504 5110#define DIV_CAM10 0x0600 5111#define DIV_CAM11 0x0604 5112#define DIV_STAT_CAM10 0x0700 5113#define DIV_STAT_CAM11 0x0704 5114#define ENABLE_ACLK_CAM10 0X0800 5115#define ENABLE_ACLK_CAM11 0X0804 5116#define ENABLE_ACLK_CAM12 0X0808 5117#define ENABLE_PCLK_CAM1 0X0900 5118#define ENABLE_SCLK_CAM1 0X0a00 5119#define ENABLE_IP_CAM10 0X0b00 5120#define ENABLE_IP_CAM11 0X0b04 5121#define ENABLE_IP_CAM12 0X0b08 5122 5123static const unsigned long cam1_clk_regs[] __initconst = { 5124 MUX_SEL_CAM10, 5125 MUX_SEL_CAM11, 5126 MUX_SEL_CAM12, 5127 MUX_ENABLE_CAM10, 5128 MUX_ENABLE_CAM11, 5129 MUX_ENABLE_CAM12, 5130 MUX_IGNORE_CAM11, 5131 DIV_CAM10, 5132 DIV_CAM11, 5133 ENABLE_ACLK_CAM10, 5134 ENABLE_ACLK_CAM11, 5135 ENABLE_ACLK_CAM12, 5136 ENABLE_PCLK_CAM1, 5137 ENABLE_SCLK_CAM1, 5138 ENABLE_IP_CAM10, 5139 ENABLE_IP_CAM11, 5140 ENABLE_IP_CAM12, 5141}; 5142 5143static const struct samsung_clk_reg_dump cam1_suspend_regs[] = { 5144 { MUX_SEL_CAM10, 0 }, 5145 { MUX_SEL_CAM11, 0 }, 5146 { MUX_SEL_CAM12, 0 }, 5147}; 5148 5149PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", }; 5150PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", }; 5151PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", }; 5152 5153PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", }; 5154PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", }; 5155PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", }; 5156 5157PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk", 5158 "phyclk_rxbyteclkhs0_s2b_phy", }; 5159 5160PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a", 5161 "mout_aclk_cam1_333_user", }; 5162PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user", 5163 "mout_aclk_cam1_400_user", }; 5164 5165PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a", 5166 "mout_aclk_cam1_333_user", }; 5167PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user", 5168 "mout_aclk_cam1_400_user", }; 5169 5170PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a", 5171 "mout_aclk_cam1_333_user", }; 5172PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", 5173 "mout_aclk_cam1_400_user", }; 5174 5175static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = { 5176 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 5177 0, 100000000), 5178}; 5179 5180static const struct samsung_mux_clock cam1_mux_clks[] __initconst = { 5181 /* MUX_SEL_CAM10 */ 5182 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", 5183 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), 5184 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user", 5185 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1), 5186 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user", 5187 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1), 5188 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user", 5189 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1), 5190 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user", 5191 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1), 5192 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user", 5193 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1), 5194 5195 /* MUX_SEL_CAM11 */ 5196 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER, 5197 "mout_phyclk_rxbyteclkhs0_s2b_user", 5198 mout_phyclk_rxbyteclkhs0_s2b_user_p, 5199 MUX_SEL_CAM11, 0, 1), 5200 5201 /* MUX_SEL_CAM12 */ 5202 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p, 5203 MUX_SEL_CAM12, 20, 1), 5204 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p, 5205 MUX_SEL_CAM12, 16, 1), 5206 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p, 5207 MUX_SEL_CAM12, 12, 1), 5208 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p, 5209 MUX_SEL_CAM12, 8, 1), 5210 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p, 5211 MUX_SEL_CAM12, 4, 1), 5212 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p, 5213 MUX_SEL_CAM12, 0, 1), 5214}; 5215 5216static const struct samsung_div_clock cam1_div_clks[] __initconst = { 5217 /* DIV_CAM10 */ 5218 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", 5219 "div_pclk_cam1_83", DIV_CAM10, 16, 2), 5220 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83", 5221 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2), 5222 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166", 5223 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2), 5224 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1", 5225 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3), 5226 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user", 5227 DIV_CAM10, 0, 3), 5228 5229 /* DIV_CAM11 */ 5230 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b", 5231 DIV_CAM11, 16, 3), 5232 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2), 5233 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3), 5234 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c", 5235 DIV_CAM11, 4, 2), 5236 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b", 5237 DIV_CAM11, 0, 3), 5238}; 5239 5240static const struct samsung_gate_clock cam1_gate_clks[] __initconst = { 5241 /* ENABLE_ACLK_CAM10 */ 5242 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", 5243 ENABLE_ACLK_CAM10, 4, 0, 0), 5244 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd", 5245 ENABLE_ACLK_CAM10, 3, 0, 0), 5246 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c", 5247 ENABLE_ACLK_CAM10, 1, 0, 0), 5248 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2", 5249 ENABLE_ACLK_CAM10, 0, 0, 0), 5250 5251 /* ENABLE_ACLK_CAM11 */ 5252 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd", 5253 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0), 5254 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166", 5255 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0), 5256 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c", 5257 "div_pclk_lite_c", ENABLE_ACLK_CAM11, 5258 27, CLK_IGNORE_UNUSED, 0), 5259 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c", 5260 "div_pclk_cam1_166", ENABLE_ACLK_CAM11, 5261 26, CLK_IGNORE_UNUSED, 0), 5262 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2", 5263 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5264 25, CLK_IGNORE_UNUSED, 0), 5265 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1", 5266 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5267 24, CLK_IGNORE_UNUSED, 0), 5268 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5", 5269 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5270 23, CLK_IGNORE_UNUSED, 0), 5271 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5", 5272 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11, 5273 22, CLK_IGNORE_UNUSED, 0), 5274 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2", 5275 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5276 21, CLK_IGNORE_UNUSED, 0), 5277 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1", 5278 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5279 20, CLK_IGNORE_UNUSED, 0), 5280 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0", 5281 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5282 19, CLK_IGNORE_UNUSED, 0), 5283 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex", 5284 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5285 18, CLK_IGNORE_UNUSED, 0), 5286 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p", 5287 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5288 17, CLK_IGNORE_UNUSED, 0), 5289 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p", 5290 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5291 16, CLK_IGNORE_UNUSED, 0), 5292 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd", 5293 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5294 15, CLK_IGNORE_UNUSED, 0), 5295 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd", 5296 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0), 5297 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c", 5298 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5299 13, CLK_IGNORE_UNUSED, 0), 5300 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c", 5301 "div_aclk_lite_c", ENABLE_ACLK_CAM11, 5302 12, CLK_IGNORE_UNUSED, 0), 5303 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83", 5304 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0), 5305 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83", 5306 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0), 5307 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p", 5308 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5309 9, CLK_IGNORE_UNUSED, 0), 5310 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83", 5311 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0), 5312 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166", 5313 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0), 5314 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166", 5315 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0), 5316 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user", 5317 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0), 5318 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user", 5319 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0), 5320 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user", 5321 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0), 5322 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user", 5323 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0), 5324 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user", 5325 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0), 5326 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user", 5327 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0), 5328 5329 /* ENABLE_ACLK_CAM12 */ 5330 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu", 5331 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5332 10, CLK_IGNORE_UNUSED, 0), 5333 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user", 5334 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0), 5335 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c", 5336 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5337 8, CLK_IGNORE_UNUSED, 0), 5338 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user", 5339 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0), 5340 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user", 5341 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0), 5342 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user", 5343 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0), 5344 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h", 5345 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5346 4, CLK_IGNORE_UNUSED, 0), 5347 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p", 5348 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5349 3, CLK_IGNORE_UNUSED, 0), 5350 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p", 5351 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5352 2, CLK_IGNORE_UNUSED, 0), 5353 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user", 5354 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0), 5355 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c", 5356 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5357 0, CLK_IGNORE_UNUSED, 0), 5358 5359 /* ENABLE_PCLK_CAM1 */ 5360 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166", 5361 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0), 5362 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166", 5363 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0), 5364 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166", 5365 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0), 5366 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83", 5367 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0), 5368 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83", 5369 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0), 5370 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83", 5371 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0), 5372 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166", 5373 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0), 5374 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex", 5375 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5376 20, CLK_IGNORE_UNUSED, 0), 5377 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p", 5378 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5379 19, CLK_IGNORE_UNUSED, 0), 5380 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83", 5381 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0), 5382 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c", 5383 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5384 17, CLK_IGNORE_UNUSED, 0), 5385 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83", 5386 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0), 5387 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83", 5388 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0), 5389 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local", 5390 "div_pclk_cam1_166", ENABLE_PCLK_CAM1, 5391 14, CLK_IGNORE_UNUSED, 0), 5392 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83", 5393 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0), 5394 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83", 5395 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0), 5396 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83", 5397 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0), 5398 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83", 5399 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0), 5400 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83", 5401 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0), 5402 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83", 5403 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0), 5404 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83", 5405 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0), 5406 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83", 5407 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0), 5408 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83", 5409 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0), 5410 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83", 5411 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0), 5412 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83", 5413 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5414 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd", 5415 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5416 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c", 5417 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0), 5418 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166", 5419 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0), 5420 5421 /* ENABLE_SCLK_CAM1 */ 5422 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1, 5423 15, 0, 0), 5424 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1, 5425 14, 0, 0), 5426 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1, 5427 13, 0, 0), 5428 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1, 5429 12, 0, 0), 5430 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b", 5431 "mout_phyclk_rxbyteclkhs0_s2b_user", 5432 ENABLE_SCLK_CAM1, 11, 0, 0), 5433 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c", 5434 ENABLE_SCLK_CAM1, 10, 0, 0), 5435 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd", 5436 ENABLE_SCLK_CAM1, 9, 0, 0), 5437 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1", 5438 ENABLE_SCLK_CAM1, 7, 0, 0), 5439 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user", 5440 ENABLE_SCLK_CAM1, 6, 0, 0), 5441 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user", 5442 ENABLE_SCLK_CAM1, 5, 0, 0), 5443 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user", 5444 ENABLE_SCLK_CAM1, 4, 0, 0), 5445 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm", 5446 ENABLE_SCLK_CAM1, 3, 0, 0), 5447 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1", 5448 ENABLE_SCLK_CAM1, 2, 0, 0), 5449 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1", 5450 ENABLE_SCLK_CAM1, 1, 0, 0), 5451 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user", 5452 ENABLE_SCLK_CAM1, 0, 0, 0), 5453}; 5454 5455static const struct samsung_cmu_info cam1_cmu_info __initconst = { 5456 .mux_clks = cam1_mux_clks, 5457 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), 5458 .div_clks = cam1_div_clks, 5459 .nr_div_clks = ARRAY_SIZE(cam1_div_clks), 5460 .gate_clks = cam1_gate_clks, 5461 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks), 5462 .fixed_clks = cam1_fixed_clks, 5463 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks), 5464 .nr_clk_ids = CLKS_NR_CAM1, 5465 .clk_regs = cam1_clk_regs, 5466 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs), 5467 .suspend_regs = cam1_suspend_regs, 5468 .nr_suspend_regs = ARRAY_SIZE(cam1_suspend_regs), 5469 .clk_name = "aclk_cam1_400", 5470}; 5471 5472/* 5473 * Register offset definitions for CMU_IMEM 5474 */ 5475#define ENABLE_ACLK_IMEM_SLIMSSS 0x080c 5476#define ENABLE_PCLK_IMEM_SLIMSSS 0x0908 5477 5478static const unsigned long imem_clk_regs[] __initconst = { 5479 ENABLE_ACLK_IMEM_SLIMSSS, 5480 ENABLE_PCLK_IMEM_SLIMSSS, 5481}; 5482 5483static const struct samsung_gate_clock imem_gate_clks[] __initconst = { 5484 /* ENABLE_ACLK_IMEM_SLIMSSS */ 5485 GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266", 5486 ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0), 5487 5488 /* ENABLE_PCLK_IMEM_SLIMSSS */ 5489 GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200", 5490 ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0), 5491}; 5492 5493static const struct samsung_cmu_info imem_cmu_info __initconst = { 5494 .gate_clks = imem_gate_clks, 5495 .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), 5496 .nr_clk_ids = CLKS_NR_IMEM, 5497 .clk_regs = imem_clk_regs, 5498 .nr_clk_regs = ARRAY_SIZE(imem_clk_regs), 5499 .clk_name = "aclk_imem_200", 5500}; 5501 5502static int __init exynos5433_cmu_probe(struct platform_device *pdev) 5503{ 5504 return exynos_arm64_register_cmu_pm(pdev, false); 5505} 5506 5507static const struct of_device_id exynos5433_cmu_of_match[] = { 5508 { 5509 .compatible = "samsung,exynos5433-cmu-aud", 5510 .data = &aud_cmu_info, 5511 }, { 5512 .compatible = "samsung,exynos5433-cmu-cam0", 5513 .data = &cam0_cmu_info, 5514 }, { 5515 .compatible = "samsung,exynos5433-cmu-cam1", 5516 .data = &cam1_cmu_info, 5517 }, { 5518 .compatible = "samsung,exynos5433-cmu-disp", 5519 .data = &disp_cmu_info, 5520 }, { 5521 .compatible = "samsung,exynos5433-cmu-g2d", 5522 .data = &g2d_cmu_info, 5523 }, { 5524 .compatible = "samsung,exynos5433-cmu-g3d", 5525 .data = &g3d_cmu_info, 5526 }, { 5527 .compatible = "samsung,exynos5433-cmu-fsys", 5528 .data = &fsys_cmu_info, 5529 }, { 5530 .compatible = "samsung,exynos5433-cmu-gscl", 5531 .data = &gscl_cmu_info, 5532 }, { 5533 .compatible = "samsung,exynos5433-cmu-mfc", 5534 .data = &mfc_cmu_info, 5535 }, { 5536 .compatible = "samsung,exynos5433-cmu-hevc", 5537 .data = &hevc_cmu_info, 5538 }, { 5539 .compatible = "samsung,exynos5433-cmu-isp", 5540 .data = &isp_cmu_info, 5541 }, { 5542 .compatible = "samsung,exynos5433-cmu-mscl", 5543 .data = &mscl_cmu_info, 5544 }, { 5545 .compatible = "samsung,exynos5433-cmu-imem", 5546 .data = &imem_cmu_info, 5547 }, { 5548 }, 5549}; 5550 5551static const struct dev_pm_ops exynos5433_cmu_pm_ops = { 5552 SET_RUNTIME_PM_OPS(exynos_arm64_cmu_suspend, exynos_arm64_cmu_resume, 5553 NULL) 5554 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5555 pm_runtime_force_resume) 5556}; 5557 5558static struct platform_driver exynos5433_cmu_driver __refdata = { 5559 .driver = { 5560 .name = "exynos5433-cmu", 5561 .of_match_table = exynos5433_cmu_of_match, 5562 .suppress_bind_attrs = true, 5563 .pm = &exynos5433_cmu_pm_ops, 5564 }, 5565 .probe = exynos5433_cmu_probe, 5566}; 5567 5568static int __init exynos5433_cmu_init(void) 5569{ 5570 return platform_driver_register(&exynos5433_cmu_driver); 5571} 5572core_initcall(exynos5433_cmu_init); 5573