1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
4 * Author: Tomasz Figa <t.figa@samsung.com>
5 *
6 * Clock driver for Exynos clock output
7 */
8
9#include <linux/slab.h>
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/module.h>
13#include <linux/io.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/pm.h>
19
20#define EXYNOS_CLKOUT_NR_CLKS		1
21#define EXYNOS_CLKOUT_PARENTS		32
22
23#define EXYNOS_PMU_DEBUG_REG		0xa00
24#define EXYNOS_CLKOUT_DISABLE_SHIFT	0
25#define EXYNOS_CLKOUT_MUX_SHIFT		8
26#define EXYNOS4_CLKOUT_MUX_MASK		0xf
27#define EXYNOS5_CLKOUT_MUX_MASK		0x1f
28
29struct exynos_clkout {
30	struct clk_gate gate;
31	struct clk_mux mux;
32	spinlock_t slock;
33	void __iomem *reg;
34	struct device_node *np;
35	u32 pmu_debug_save;
36	struct clk_hw_onecell_data data;
37};
38
39struct exynos_clkout_variant {
40	u32 mux_mask;
41};
42
43static const struct exynos_clkout_variant exynos_clkout_exynos4 = {
44	.mux_mask	= EXYNOS4_CLKOUT_MUX_MASK,
45};
46
47static const struct exynos_clkout_variant exynos_clkout_exynos5 = {
48	.mux_mask	= EXYNOS5_CLKOUT_MUX_MASK,
49};
50
51static const struct of_device_id exynos_clkout_ids[] = {
52	{
53		.compatible = "samsung,exynos3250-pmu",
54		.data = &exynos_clkout_exynos4,
55	}, {
56		.compatible = "samsung,exynos4210-pmu",
57		.data = &exynos_clkout_exynos4,
58	}, {
59		.compatible = "samsung,exynos4212-pmu",
60		.data = &exynos_clkout_exynos4,
61	}, {
62		.compatible = "samsung,exynos4412-pmu",
63		.data = &exynos_clkout_exynos4,
64	}, {
65		.compatible = "samsung,exynos5250-pmu",
66		.data = &exynos_clkout_exynos5,
67	}, {
68		.compatible = "samsung,exynos5410-pmu",
69		.data = &exynos_clkout_exynos5,
70	}, {
71		.compatible = "samsung,exynos5420-pmu",
72		.data = &exynos_clkout_exynos5,
73	}, {
74		.compatible = "samsung,exynos5433-pmu",
75		.data = &exynos_clkout_exynos5,
76	}, { }
77};
78MODULE_DEVICE_TABLE(of, exynos_clkout_ids);
79
80/*
81 * Device will be instantiated as child of PMU device without its own
82 * device node.  Therefore match compatibles against parent.
83 */
84static int exynos_clkout_match_parent_dev(struct device *dev, u32 *mux_mask)
85{
86	const struct exynos_clkout_variant *variant;
87	const struct of_device_id *match;
88
89	if (!dev->parent) {
90		dev_err(dev, "not instantiated from MFD\n");
91		return -EINVAL;
92	}
93
94	/*
95	 * 'exynos_clkout_ids' arrays is not the ids array matched by
96	 * the dev->parent driver, so of_device_get_match_data() or
97	 * device_get_match_data() cannot be used here.
98	 */
99	match = of_match_device(exynos_clkout_ids, dev->parent);
100	if (!match) {
101		dev_err(dev, "cannot match parent device\n");
102		return -EINVAL;
103	}
104	variant = match->data;
105
106	*mux_mask = variant->mux_mask;
107
108	return 0;
109}
110
111static int exynos_clkout_probe(struct platform_device *pdev)
112{
113	const char *parent_names[EXYNOS_CLKOUT_PARENTS];
114	struct clk *parents[EXYNOS_CLKOUT_PARENTS];
115	struct exynos_clkout *clkout;
116	int parent_count, ret, i;
117	u32 mux_mask;
118
119	clkout = devm_kzalloc(&pdev->dev,
120			      struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS),
121			      GFP_KERNEL);
122	if (!clkout)
123		return -ENOMEM;
124
125	ret = exynos_clkout_match_parent_dev(&pdev->dev, &mux_mask);
126	if (ret)
127		return ret;
128
129	clkout->np = pdev->dev.of_node;
130	if (!clkout->np) {
131		/*
132		 * pdev->dev.parent was checked by exynos_clkout_match_parent_dev()
133		 * so it is not NULL.
134		 */
135		clkout->np = pdev->dev.parent->of_node;
136	}
137
138	platform_set_drvdata(pdev, clkout);
139
140	spin_lock_init(&clkout->slock);
141
142	parent_count = 0;
143	for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
144		char name[] = "clkoutXX";
145
146		snprintf(name, sizeof(name), "clkout%d", i);
147		parents[i] = of_clk_get_by_name(clkout->np, name);
148		if (IS_ERR(parents[i])) {
149			parent_names[i] = "none";
150			continue;
151		}
152
153		parent_names[i] = __clk_get_name(parents[i]);
154		parent_count = i + 1;
155	}
156
157	if (!parent_count)
158		return -EINVAL;
159
160	clkout->reg = of_iomap(clkout->np, 0);
161	if (!clkout->reg) {
162		ret = -ENODEV;
163		goto clks_put;
164	}
165
166	clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
167	clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
168	clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
169	clkout->gate.lock = &clkout->slock;
170
171	clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
172	clkout->mux.mask = mux_mask;
173	clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
174	clkout->mux.lock = &clkout->slock;
175
176	clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
177				parent_names, parent_count, &clkout->mux.hw,
178				&clk_mux_ops, NULL, NULL, &clkout->gate.hw,
179				&clk_gate_ops, CLK_SET_RATE_PARENT
180				| CLK_SET_RATE_NO_REPARENT);
181	if (IS_ERR(clkout->data.hws[0])) {
182		ret = PTR_ERR(clkout->data.hws[0]);
183		goto err_unmap;
184	}
185
186	clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
187	ret = of_clk_add_hw_provider(clkout->np, of_clk_hw_onecell_get, &clkout->data);
188	if (ret)
189		goto err_clk_unreg;
190
191	return 0;
192
193err_clk_unreg:
194	clk_hw_unregister(clkout->data.hws[0]);
195err_unmap:
196	iounmap(clkout->reg);
197clks_put:
198	for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
199		if (!IS_ERR(parents[i]))
200			clk_put(parents[i]);
201
202	dev_err(&pdev->dev, "failed to register clkout clock\n");
203
204	return ret;
205}
206
207static void exynos_clkout_remove(struct platform_device *pdev)
208{
209	struct exynos_clkout *clkout = platform_get_drvdata(pdev);
210
211	of_clk_del_provider(clkout->np);
212	clk_hw_unregister(clkout->data.hws[0]);
213	iounmap(clkout->reg);
214}
215
216static int __maybe_unused exynos_clkout_suspend(struct device *dev)
217{
218	struct exynos_clkout *clkout = dev_get_drvdata(dev);
219
220	clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
221
222	return 0;
223}
224
225static int __maybe_unused exynos_clkout_resume(struct device *dev)
226{
227	struct exynos_clkout *clkout = dev_get_drvdata(dev);
228
229	writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
230
231	return 0;
232}
233
234static SIMPLE_DEV_PM_OPS(exynos_clkout_pm_ops, exynos_clkout_suspend,
235			 exynos_clkout_resume);
236
237static struct platform_driver exynos_clkout_driver = {
238	.driver = {
239		.name = "exynos-clkout",
240		.of_match_table = exynos_clkout_ids,
241		.pm = &exynos_clkout_pm_ops,
242	},
243	.probe = exynos_clkout_probe,
244	.remove_new = exynos_clkout_remove,
245};
246module_platform_driver(exynos_clkout_driver);
247
248MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>");
249MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
250MODULE_DESCRIPTION("Samsung Exynos clock output driver");
251MODULE_LICENSE("GPL");
252