1// SPDX-License-Identifier: GPL-2.0 2/* 3 * r8a7742 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <linux/device.h> 9#include <linux/init.h> 10#include <linux/kernel.h> 11#include <linux/soc/renesas/rcar-rst.h> 12 13#include <dt-bindings/clock/r8a7742-cpg-mssr.h> 14 15#include "renesas-cpg-mssr.h" 16#include "rcar-gen2-cpg.h" 17 18enum clk_ids { 19 /* Core Clock Outputs exported to DT */ 20 LAST_DT_CORE_CLK = R8A7742_CLK_OSC, 21 22 /* External Input Clocks */ 23 CLK_EXTAL, 24 CLK_USB_EXTAL, 25 26 /* Internal Core Clocks */ 27 CLK_MAIN, 28 CLK_PLL0, 29 CLK_PLL1, 30 CLK_PLL3, 31 CLK_PLL1_DIV2, 32 33 /* Module Clocks */ 34 MOD_CLK_BASE 35}; 36 37static const struct cpg_core_clk r8a7742_core_clks[] __initconst = { 38 /* External Clock Inputs */ 39 DEF_INPUT("extal", CLK_EXTAL), 40 DEF_INPUT("usb_extal", CLK_USB_EXTAL), 41 42 /* Internal Core Clocks */ 43 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), 47 48 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 49 50 /* Core Clock Outputs */ 51 DEF_BASE("z", R8A7742_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0), 52 DEF_BASE("lb", R8A7742_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), 53 DEF_BASE("sdh", R8A7742_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 54 DEF_BASE("sd0", R8A7742_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 55 DEF_BASE("sd1", R8A7742_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1), 56 DEF_BASE("qspi", R8A7742_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), 57 DEF_BASE("rcan", R8A7742_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), 58 59 DEF_FIXED("z2", R8A7742_CLK_Z2, CLK_PLL1, 2, 1), 60 DEF_FIXED("zg", R8A7742_CLK_ZG, CLK_PLL1, 3, 1), 61 DEF_FIXED("zx", R8A7742_CLK_ZX, CLK_PLL1, 3, 1), 62 DEF_FIXED("zs", R8A7742_CLK_ZS, CLK_PLL1, 6, 1), 63 DEF_FIXED("hp", R8A7742_CLK_HP, CLK_PLL1, 12, 1), 64 DEF_FIXED("b", R8A7742_CLK_B, CLK_PLL1, 12, 1), 65 DEF_FIXED("p", R8A7742_CLK_P, CLK_PLL1, 24, 1), 66 DEF_FIXED("cl", R8A7742_CLK_CL, CLK_PLL1, 48, 1), 67 DEF_FIXED("m2", R8A7742_CLK_M2, CLK_PLL1, 8, 1), 68 DEF_FIXED("zb3", R8A7742_CLK_ZB3, CLK_PLL3, 4, 1), 69 DEF_FIXED("zb3d2", R8A7742_CLK_ZB3D2, CLK_PLL3, 8, 1), 70 DEF_FIXED("ddr", R8A7742_CLK_DDR, CLK_PLL3, 8, 1), 71 DEF_FIXED("mp", R8A7742_CLK_MP, CLK_PLL1_DIV2, 15, 1), 72 DEF_FIXED("cp", R8A7742_CLK_CP, CLK_EXTAL, 2, 1), 73 DEF_FIXED("r", R8A7742_CLK_R, CLK_PLL1, 49152, 1), 74 DEF_FIXED("osc", R8A7742_CLK_OSC, CLK_PLL1, 12288, 1), 75 76 DEF_DIV6P1("sd2", R8A7742_CLK_SD2, CLK_PLL1_DIV2, 0x078), 77 DEF_DIV6P1("sd3", R8A7742_CLK_SD3, CLK_PLL1_DIV2, 0x26c), 78 DEF_DIV6P1("mmc0", R8A7742_CLK_MMC0, CLK_PLL1_DIV2, 0x240), 79 DEF_DIV6P1("mmc1", R8A7742_CLK_MMC1, CLK_PLL1_DIV2, 0x244), 80}; 81 82static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = { 83 DEF_MOD("msiof0", 0, R8A7742_CLK_MP), 84 DEF_MOD("vcp1", 100, R8A7742_CLK_ZS), 85 DEF_MOD("vcp0", 101, R8A7742_CLK_ZS), 86 DEF_MOD("vpc1", 102, R8A7742_CLK_ZS), 87 DEF_MOD("vpc0", 103, R8A7742_CLK_ZS), 88 DEF_MOD("tmu1", 111, R8A7742_CLK_P), 89 DEF_MOD("3dg", 112, R8A7742_CLK_ZG), 90 DEF_MOD("2d-dmac", 115, R8A7742_CLK_ZS), 91 DEF_MOD("fdp1-2", 117, R8A7742_CLK_ZS), 92 DEF_MOD("fdp1-1", 118, R8A7742_CLK_ZS), 93 DEF_MOD("fdp1-0", 119, R8A7742_CLK_ZS), 94 DEF_MOD("tmu3", 121, R8A7742_CLK_P), 95 DEF_MOD("tmu2", 122, R8A7742_CLK_P), 96 DEF_MOD("cmt0", 124, R8A7742_CLK_R), 97 DEF_MOD("tmu0", 125, R8A7742_CLK_CP), 98 DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS), 99 DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS), 100 DEF_MOD("vspr", 130, R8A7742_CLK_ZS), 101 DEF_MOD("vsps", 131, R8A7742_CLK_ZS), 102 DEF_MOD("scifa2", 202, R8A7742_CLK_MP), 103 DEF_MOD("scifa1", 203, R8A7742_CLK_MP), 104 DEF_MOD("scifa0", 204, R8A7742_CLK_MP), 105 DEF_MOD("msiof2", 205, R8A7742_CLK_MP), 106 DEF_MOD("scifb0", 206, R8A7742_CLK_MP), 107 DEF_MOD("scifb1", 207, R8A7742_CLK_MP), 108 DEF_MOD("msiof1", 208, R8A7742_CLK_MP), 109 DEF_MOD("msiof3", 215, R8A7742_CLK_MP), 110 DEF_MOD("scifb2", 216, R8A7742_CLK_MP), 111 DEF_MOD("sys-dmac1", 218, R8A7742_CLK_ZS), 112 DEF_MOD("sys-dmac0", 219, R8A7742_CLK_ZS), 113 DEF_MOD("iic2", 300, R8A7742_CLK_HP), 114 DEF_MOD("tpu0", 304, R8A7742_CLK_CP), 115 DEF_MOD("mmcif1", 305, R8A7742_CLK_MMC1), 116 DEF_MOD("scif2", 310, R8A7742_CLK_P), 117 DEF_MOD("sdhi3", 311, R8A7742_CLK_SD3), 118 DEF_MOD("sdhi2", 312, R8A7742_CLK_SD2), 119 DEF_MOD("sdhi1", 313, R8A7742_CLK_SD1), 120 DEF_MOD("sdhi0", 314, R8A7742_CLK_SD0), 121 DEF_MOD("mmcif0", 315, R8A7742_CLK_MMC0), 122 DEF_MOD("iic0", 318, R8A7742_CLK_HP), 123 DEF_MOD("pciec", 319, R8A7742_CLK_MP), 124 DEF_MOD("iic1", 323, R8A7742_CLK_HP), 125 DEF_MOD("usb3.0", 328, R8A7742_CLK_MP), 126 DEF_MOD("cmt1", 329, R8A7742_CLK_R), 127 DEF_MOD("usbhs-dmac0", 330, R8A7742_CLK_HP), 128 DEF_MOD("usbhs-dmac1", 331, R8A7742_CLK_HP), 129 DEF_MOD("rwdt", 402, R8A7742_CLK_R), 130 DEF_MOD("irqc", 407, R8A7742_CLK_CP), 131 DEF_MOD("intc-sys", 408, R8A7742_CLK_ZS), 132 DEF_MOD("audio-dmac1", 501, R8A7742_CLK_HP), 133 DEF_MOD("audio-dmac0", 502, R8A7742_CLK_HP), 134 DEF_MOD("thermal", 522, CLK_EXTAL), 135 DEF_MOD("pwm", 523, R8A7742_CLK_P), 136 DEF_MOD("usb-ehci", 703, R8A7742_CLK_MP), 137 DEF_MOD("usbhs", 704, R8A7742_CLK_HP), 138 DEF_MOD("hscif1", 716, R8A7742_CLK_ZS), 139 DEF_MOD("hscif0", 717, R8A7742_CLK_ZS), 140 DEF_MOD("scif1", 720, R8A7742_CLK_P), 141 DEF_MOD("scif0", 721, R8A7742_CLK_P), 142 DEF_MOD("du2", 722, R8A7742_CLK_ZX), 143 DEF_MOD("du1", 723, R8A7742_CLK_ZX), 144 DEF_MOD("du0", 724, R8A7742_CLK_ZX), 145 DEF_MOD("lvds1", 725, R8A7742_CLK_ZX), 146 DEF_MOD("lvds0", 726, R8A7742_CLK_ZX), 147 DEF_MOD("r-gp2d", 807, R8A7742_CLK_ZX), 148 DEF_MOD("vin3", 808, R8A7742_CLK_ZG), 149 DEF_MOD("vin2", 809, R8A7742_CLK_ZG), 150 DEF_MOD("vin1", 810, R8A7742_CLK_ZG), 151 DEF_MOD("vin0", 811, R8A7742_CLK_ZG), 152 DEF_MOD("etheravb", 812, R8A7742_CLK_HP), 153 DEF_MOD("ether", 813, R8A7742_CLK_P), 154 DEF_MOD("sata1", 814, R8A7742_CLK_ZS), 155 DEF_MOD("sata0", 815, R8A7742_CLK_ZS), 156 DEF_MOD("imr-x2-1", 820, R8A7742_CLK_ZG), 157 DEF_MOD("imr-x2-0", 821, R8A7742_CLK_HP), 158 DEF_MOD("imr-lsx2-1", 822, R8A7742_CLK_P), 159 DEF_MOD("imr-lsx2-0", 823, R8A7742_CLK_ZS), 160 DEF_MOD("gpio5", 907, R8A7742_CLK_CP), 161 DEF_MOD("gpio4", 908, R8A7742_CLK_CP), 162 DEF_MOD("gpio3", 909, R8A7742_CLK_CP), 163 DEF_MOD("gpio2", 910, R8A7742_CLK_CP), 164 DEF_MOD("gpio1", 911, R8A7742_CLK_CP), 165 DEF_MOD("gpio0", 912, R8A7742_CLK_CP), 166 DEF_MOD("can1", 915, R8A7742_CLK_P), 167 DEF_MOD("can0", 916, R8A7742_CLK_P), 168 DEF_MOD("qspi_mod", 917, R8A7742_CLK_QSPI), 169 DEF_MOD("iicdvfs", 926, R8A7742_CLK_CP), 170 DEF_MOD("i2c3", 928, R8A7742_CLK_HP), 171 DEF_MOD("i2c2", 929, R8A7742_CLK_HP), 172 DEF_MOD("i2c1", 930, R8A7742_CLK_HP), 173 DEF_MOD("i2c0", 931, R8A7742_CLK_HP), 174 DEF_MOD("ssi-all", 1005, R8A7742_CLK_P), 175 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 176 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 177 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 178 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 179 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 180 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 181 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 182 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 183 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 184 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 185 DEF_MOD("scu-all", 1017, R8A7742_CLK_P), 186 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 187 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 188 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 189 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 190 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 191 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 192 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 193 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 194 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 195 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 196 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 197 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 198 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 199 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 200}; 201 202static const unsigned int r8a7742_crit_mod_clks[] __initconst = { 203 MOD_CLK_ID(402), /* RWDT */ 204 MOD_CLK_ID(408), /* INTC-SYS (GIC) */ 205}; 206 207/* 208 * CPG Clock Data 209 */ 210 211/* 212 * MD EXTAL PLL0 PLL1 PLL3 213 * 14 13 19 (MHz) *1 *1 214 *--------------------------------------------------- 215 * 0 0 0 15 x172/2 x208/2 x106 216 * 0 0 1 15 x172/2 x208/2 x88 217 * 0 1 0 20 x130/2 x156/2 x80 218 * 0 1 1 20 x130/2 x156/2 x66 219 * 1 0 0 26 / 2 x200/2 x240/2 x122 220 * 1 0 1 26 / 2 x200/2 x240/2 x102 221 * 1 1 0 30 / 2 x172/2 x208/2 x106 222 * 1 1 1 30 / 2 x172/2 x208/2 x88 223 * 224 * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2) 225 */ 226#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ 227 (((md) & BIT(13)) >> 12) | \ 228 (((md) & BIT(19)) >> 19)) 229 230static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { 231 /* EXTAL div PLL1 mult PLL3 mult */ 232 { 1, 208, 106, }, 233 { 1, 208, 88, }, 234 { 1, 156, 80, }, 235 { 1, 156, 66, }, 236 { 2, 240, 122, }, 237 { 2, 240, 102, }, 238 { 2, 208, 106, }, 239 { 2, 208, 88, }, 240}; 241 242static int __init r8a7742_cpg_mssr_init(struct device *dev) 243{ 244 const struct rcar_gen2_cpg_pll_config *cpg_pll_config; 245 u32 cpg_mode; 246 int error; 247 248 error = rcar_rst_read_mode_pins(&cpg_mode); 249 if (error) 250 return error; 251 252 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 253 254 return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode); 255} 256 257const struct cpg_mssr_info r8a7742_cpg_mssr_info __initconst = { 258 /* Core Clocks */ 259 .core_clks = r8a7742_core_clks, 260 .num_core_clks = ARRAY_SIZE(r8a7742_core_clks), 261 .last_dt_core_clk = LAST_DT_CORE_CLK, 262 .num_total_core_clks = MOD_CLK_BASE, 263 264 /* Module Clocks */ 265 .mod_clks = r8a7742_mod_clks, 266 .num_mod_clks = ARRAY_SIZE(r8a7742_mod_clks), 267 .num_hw_mod_clks = 12 * 32, 268 269 /* Critical Module Clocks */ 270 .crit_mod_clks = r8a7742_crit_mod_clks, 271 .num_crit_mod_clks = ARRAY_SIZE(r8a7742_crit_mod_clks), 272 273 /* Callbacks */ 274 .init = r8a7742_cpg_mssr_init, 275 .cpg_clk_register = rcar_gen2_cpg_clk_register, 276}; 277