1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk-provider.h> 7#include <linux/mod_devicetable.h> 8#include <linux/module.h> 9#include <linux/platform_device.h> 10#include <linux/regmap.h> 11 12#include <dt-bindings/clock/qcom,sm8450-gpucc.h> 13#include <dt-bindings/reset/qcom,sm8450-gpucc.h> 14 15#include "clk-alpha-pll.h" 16#include "clk-branch.h" 17#include "clk-rcg.h" 18#include "clk-regmap.h" 19#include "clk-regmap-divider.h" 20#include "clk-regmap-mux.h" 21#include "clk-regmap-phy-mux.h" 22#include "gdsc.h" 23#include "reset.h" 24 25enum { 26 DT_BI_TCXO, 27 DT_GPLL0_OUT_MAIN, 28 DT_GPLL0_OUT_MAIN_DIV, 29}; 30 31enum { 32 P_BI_TCXO, 33 P_GPLL0_OUT_MAIN, 34 P_GPLL0_OUT_MAIN_DIV, 35 P_GPU_CC_PLL0_OUT_MAIN, 36 P_GPU_CC_PLL1_OUT_MAIN, 37}; 38 39static struct pll_vco lucid_evo_vco[] = { 40 { 249600000, 2000000000, 0 }, 41}; 42 43static struct alpha_pll_config gpu_cc_pll0_config = { 44 .l = 0x1d, 45 .alpha = 0xb000, 46 .config_ctl_val = 0x20485699, 47 .config_ctl_hi_val = 0x00182261, 48 .config_ctl_hi1_val = 0x32aa299c, 49 .user_ctl_val = 0x00000000, 50 .user_ctl_hi_val = 0x00000805, 51}; 52 53static struct clk_alpha_pll gpu_cc_pll0 = { 54 .offset = 0x0, 55 .vco_table = lucid_evo_vco, 56 .num_vco = ARRAY_SIZE(lucid_evo_vco), 57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 58 .clkr = { 59 .hw.init = &(struct clk_init_data){ 60 .name = "gpu_cc_pll0", 61 .parent_data = &(const struct clk_parent_data){ 62 .index = DT_BI_TCXO, 63 }, 64 .num_parents = 1, 65 .ops = &clk_alpha_pll_lucid_evo_ops, 66 }, 67 }, 68}; 69 70static struct alpha_pll_config gpu_cc_pll1_config = { 71 .l = 0x34, 72 .alpha = 0x1555, 73 .config_ctl_val = 0x20485699, 74 .config_ctl_hi_val = 0x00182261, 75 .config_ctl_hi1_val = 0x32aa299c, 76 .user_ctl_val = 0x00000000, 77 .user_ctl_hi_val = 0x00000805, 78}; 79 80static struct clk_alpha_pll gpu_cc_pll1 = { 81 .offset = 0x1000, 82 .vco_table = lucid_evo_vco, 83 .num_vco = ARRAY_SIZE(lucid_evo_vco), 84 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 85 .clkr = { 86 .hw.init = &(struct clk_init_data){ 87 .name = "gpu_cc_pll1", 88 .parent_data = &(const struct clk_parent_data){ 89 .index = DT_BI_TCXO, 90 }, 91 .num_parents = 1, 92 .ops = &clk_alpha_pll_lucid_evo_ops, 93 }, 94 }, 95}; 96 97static const struct parent_map gpu_cc_parent_map_0[] = { 98 { P_BI_TCXO, 0 }, 99 { P_GPLL0_OUT_MAIN, 5 }, 100 { P_GPLL0_OUT_MAIN_DIV, 6 }, 101}; 102 103static const struct clk_parent_data gpu_cc_parent_data_0[] = { 104 { .index = DT_BI_TCXO }, 105 { .index = DT_GPLL0_OUT_MAIN }, 106 { .index = DT_GPLL0_OUT_MAIN_DIV }, 107}; 108 109static const struct parent_map gpu_cc_parent_map_1[] = { 110 { P_BI_TCXO, 0 }, 111 { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 112 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 113 { P_GPLL0_OUT_MAIN, 5 }, 114 { P_GPLL0_OUT_MAIN_DIV, 6 }, 115}; 116 117static const struct clk_parent_data gpu_cc_parent_data_1[] = { 118 { .index = DT_BI_TCXO }, 119 { .hw = &gpu_cc_pll0.clkr.hw }, 120 { .hw = &gpu_cc_pll1.clkr.hw }, 121 { .index = DT_GPLL0_OUT_MAIN }, 122 { .index = DT_GPLL0_OUT_MAIN_DIV }, 123}; 124 125static const struct parent_map gpu_cc_parent_map_2[] = { 126 { P_BI_TCXO, 0 }, 127 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 128 { P_GPLL0_OUT_MAIN, 5 }, 129 { P_GPLL0_OUT_MAIN_DIV, 6 }, 130}; 131 132static const struct clk_parent_data gpu_cc_parent_data_2[] = { 133 { .index = DT_BI_TCXO }, 134 { .hw = &gpu_cc_pll1.clkr.hw }, 135 { .index = DT_GPLL0_OUT_MAIN }, 136 { .index = DT_GPLL0_OUT_MAIN_DIV }, 137}; 138 139static const struct parent_map gpu_cc_parent_map_3[] = { 140 { P_BI_TCXO, 0 }, 141}; 142 143static const struct clk_parent_data gpu_cc_parent_data_3[] = { 144 { .index = DT_BI_TCXO }, 145}; 146 147static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { 148 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 149 { } 150}; 151 152static struct clk_rcg2 gpu_cc_ff_clk_src = { 153 .cmd_rcgr = 0x9474, 154 .mnd_width = 0, 155 .hid_width = 5, 156 .parent_map = gpu_cc_parent_map_0, 157 .freq_tbl = ftbl_gpu_cc_ff_clk_src, 158 .hw_clk_ctrl = true, 159 .clkr.hw.init = &(struct clk_init_data){ 160 .name = "gpu_cc_ff_clk_src", 161 .parent_data = gpu_cc_parent_data_0, 162 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 163 .flags = CLK_SET_RATE_PARENT, 164 .ops = &clk_rcg2_shared_ops, 165 }, 166}; 167 168static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 169 F(19200000, P_BI_TCXO, 1, 0, 0), 170 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 171 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), 172 { } 173}; 174 175static struct clk_rcg2 gpu_cc_gmu_clk_src = { 176 .cmd_rcgr = 0x9318, 177 .mnd_width = 0, 178 .hid_width = 5, 179 .parent_map = gpu_cc_parent_map_1, 180 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 181 .hw_clk_ctrl = true, 182 .clkr.hw.init = &(struct clk_init_data){ 183 .name = "gpu_cc_gmu_clk_src", 184 .parent_data = gpu_cc_parent_data_1, 185 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 186 .flags = CLK_SET_RATE_PARENT, 187 .ops = &clk_rcg2_shared_ops, 188 }, 189}; 190 191static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { 192 F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), 193 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 194 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 195 { } 196}; 197 198static struct clk_rcg2 gpu_cc_hub_clk_src = { 199 .cmd_rcgr = 0x93ec, 200 .mnd_width = 0, 201 .hid_width = 5, 202 .parent_map = gpu_cc_parent_map_2, 203 .freq_tbl = ftbl_gpu_cc_hub_clk_src, 204 .hw_clk_ctrl = true, 205 .clkr.hw.init = &(struct clk_init_data){ 206 .name = "gpu_cc_hub_clk_src", 207 .parent_data = gpu_cc_parent_data_2, 208 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), 209 .flags = CLK_SET_RATE_PARENT, 210 .ops = &clk_rcg2_shared_ops, 211 }, 212}; 213 214static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { 215 F(19200000, P_BI_TCXO, 1, 0, 0), 216 { } 217}; 218 219static struct clk_rcg2 gpu_cc_xo_clk_src = { 220 .cmd_rcgr = 0x9010, 221 .mnd_width = 0, 222 .hid_width = 5, 223 .parent_map = gpu_cc_parent_map_3, 224 .freq_tbl = ftbl_gpu_cc_xo_clk_src, 225 .hw_clk_ctrl = true, 226 .clkr.hw.init = &(struct clk_init_data){ 227 .name = "gpu_cc_xo_clk_src", 228 .parent_data = gpu_cc_parent_data_3, 229 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), 230 .flags = CLK_SET_RATE_PARENT, 231 .ops = &clk_rcg2_shared_ops, 232 }, 233}; 234 235static struct clk_regmap_div gpu_cc_demet_div_clk_src = { 236 .reg = 0x9054, 237 .shift = 0, 238 .width = 4, 239 .clkr.hw.init = &(struct clk_init_data) { 240 .name = "gpu_cc_demet_div_clk_src", 241 .parent_hws = (const struct clk_hw*[]){ 242 &gpu_cc_xo_clk_src.clkr.hw, 243 }, 244 .num_parents = 1, 245 .flags = CLK_SET_RATE_PARENT, 246 .ops = &clk_regmap_div_ro_ops, 247 }, 248}; 249 250static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { 251 .reg = 0x9430, 252 .shift = 0, 253 .width = 4, 254 .clkr.hw.init = &(struct clk_init_data) { 255 .name = "gpu_cc_hub_ahb_div_clk_src", 256 .parent_hws = (const struct clk_hw*[]){ 257 &gpu_cc_hub_clk_src.clkr.hw, 258 }, 259 .num_parents = 1, 260 .flags = CLK_SET_RATE_PARENT, 261 .ops = &clk_regmap_div_ro_ops, 262 }, 263}; 264 265static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { 266 .reg = 0x942c, 267 .shift = 0, 268 .width = 4, 269 .clkr.hw.init = &(struct clk_init_data) { 270 .name = "gpu_cc_hub_cx_int_div_clk_src", 271 .parent_hws = (const struct clk_hw*[]){ 272 &gpu_cc_hub_clk_src.clkr.hw, 273 }, 274 .num_parents = 1, 275 .flags = CLK_SET_RATE_PARENT, 276 .ops = &clk_regmap_div_ro_ops, 277 }, 278}; 279 280static struct clk_regmap_div gpu_cc_xo_div_clk_src = { 281 .reg = 0x9050, 282 .shift = 0, 283 .width = 4, 284 .clkr.hw.init = &(struct clk_init_data) { 285 .name = "gpu_cc_xo_div_clk_src", 286 .parent_hws = (const struct clk_hw*[]){ 287 &gpu_cc_xo_clk_src.clkr.hw, 288 }, 289 .num_parents = 1, 290 .flags = CLK_SET_RATE_PARENT, 291 .ops = &clk_regmap_div_ro_ops, 292 }, 293}; 294 295static struct clk_branch gpu_cc_ahb_clk = { 296 .halt_reg = 0x911c, 297 .halt_check = BRANCH_HALT_DELAY, 298 .clkr = { 299 .enable_reg = 0x911c, 300 .enable_mask = BIT(0), 301 .hw.init = &(struct clk_init_data){ 302 .name = "gpu_cc_ahb_clk", 303 .parent_hws = (const struct clk_hw*[]) { 304 &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 305 }, 306 .num_parents = 1, 307 .flags = CLK_SET_RATE_PARENT, 308 .ops = &clk_branch2_ops, 309 }, 310 }, 311}; 312 313static struct clk_branch gpu_cc_crc_ahb_clk = { 314 .halt_reg = 0x9120, 315 .halt_check = BRANCH_HALT_VOTED, 316 .clkr = { 317 .enable_reg = 0x9120, 318 .enable_mask = BIT(0), 319 .hw.init = &(struct clk_init_data){ 320 .name = "gpu_cc_crc_ahb_clk", 321 .parent_hws = (const struct clk_hw*[]) { 322 &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 323 }, 324 .num_parents = 1, 325 .flags = CLK_SET_RATE_PARENT, 326 .ops = &clk_branch2_ops, 327 }, 328 }, 329}; 330 331static struct clk_branch gpu_cc_cx_apb_clk = { 332 .halt_reg = 0x912c, 333 .halt_check = BRANCH_HALT_VOTED, 334 .clkr = { 335 .enable_reg = 0x912c, 336 .enable_mask = BIT(0), 337 .hw.init = &(struct clk_init_data){ 338 .name = "gpu_cc_cx_apb_clk", 339 .ops = &clk_branch2_ops, 340 }, 341 }, 342}; 343 344static struct clk_branch gpu_cc_cx_ff_clk = { 345 .halt_reg = 0x914c, 346 .halt_check = BRANCH_HALT, 347 .clkr = { 348 .enable_reg = 0x914c, 349 .enable_mask = BIT(0), 350 .hw.init = &(struct clk_init_data){ 351 .name = "gpu_cc_cx_ff_clk", 352 .parent_hws = (const struct clk_hw*[]) { 353 &gpu_cc_ff_clk_src.clkr.hw, 354 }, 355 .num_parents = 1, 356 .flags = CLK_SET_RATE_PARENT, 357 .ops = &clk_branch2_ops, 358 }, 359 }, 360}; 361 362static struct clk_branch gpu_cc_cx_gmu_clk = { 363 .halt_reg = 0x913c, 364 .halt_check = BRANCH_HALT, 365 .clkr = { 366 .enable_reg = 0x913c, 367 .enable_mask = BIT(0), 368 .hw.init = &(struct clk_init_data){ 369 .name = "gpu_cc_cx_gmu_clk", 370 .parent_hws = (const struct clk_hw*[]) { 371 &gpu_cc_gmu_clk_src.clkr.hw, 372 }, 373 .num_parents = 1, 374 .flags = CLK_SET_RATE_PARENT, 375 .ops = &clk_branch2_aon_ops, 376 }, 377 }, 378}; 379 380static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { 381 .halt_reg = 0x9130, 382 .halt_check = BRANCH_HALT_VOTED, 383 .clkr = { 384 .enable_reg = 0x9130, 385 .enable_mask = BIT(0), 386 .hw.init = &(struct clk_init_data){ 387 .name = "gpu_cc_cx_snoc_dvm_clk", 388 .ops = &clk_branch2_ops, 389 }, 390 }, 391}; 392 393static struct clk_branch gpu_cc_cxo_aon_clk = { 394 .halt_reg = 0x9004, 395 .halt_check = BRANCH_HALT_VOTED, 396 .clkr = { 397 .enable_reg = 0x9004, 398 .enable_mask = BIT(0), 399 .hw.init = &(struct clk_init_data){ 400 .name = "gpu_cc_cxo_aon_clk", 401 .parent_hws = (const struct clk_hw*[]) { 402 &gpu_cc_xo_clk_src.clkr.hw, 403 }, 404 .num_parents = 1, 405 .flags = CLK_SET_RATE_PARENT, 406 .ops = &clk_branch2_ops, 407 }, 408 }, 409}; 410 411static struct clk_branch gpu_cc_cxo_clk = { 412 .halt_reg = 0x9144, 413 .halt_check = BRANCH_HALT, 414 .clkr = { 415 .enable_reg = 0x9144, 416 .enable_mask = BIT(0), 417 .hw.init = &(struct clk_init_data){ 418 .name = "gpu_cc_cxo_clk", 419 .parent_hws = (const struct clk_hw*[]) { 420 &gpu_cc_xo_clk_src.clkr.hw, 421 }, 422 .num_parents = 1, 423 .flags = CLK_SET_RATE_PARENT, 424 .ops = &clk_branch2_ops, 425 }, 426 }, 427}; 428 429static struct clk_branch gpu_cc_demet_clk = { 430 .halt_reg = 0x900c, 431 .halt_check = BRANCH_HALT, 432 .clkr = { 433 .enable_reg = 0x900c, 434 .enable_mask = BIT(0), 435 .hw.init = &(struct clk_init_data){ 436 .name = "gpu_cc_demet_clk", 437 .parent_hws = (const struct clk_hw*[]) { 438 &gpu_cc_demet_div_clk_src.clkr.hw, 439 }, 440 .num_parents = 1, 441 .flags = CLK_SET_RATE_PARENT, 442 .ops = &clk_branch2_aon_ops, 443 }, 444 }, 445}; 446 447static struct clk_branch gpu_cc_freq_measure_clk = { 448 .halt_reg = 0x9008, 449 .halt_check = BRANCH_HALT, 450 .clkr = { 451 .enable_reg = 0x9008, 452 .enable_mask = BIT(0), 453 .hw.init = &(struct clk_init_data){ 454 .name = "gpu_cc_freq_measure_clk", 455 .parent_hws = (const struct clk_hw*[]) { 456 &gpu_cc_xo_div_clk_src.clkr.hw, 457 }, 458 .num_parents = 1, 459 .flags = CLK_SET_RATE_PARENT, 460 .ops = &clk_branch2_ops, 461 }, 462 }, 463}; 464 465static struct clk_branch gpu_cc_gx_ff_clk = { 466 .halt_reg = 0x90c0, 467 .halt_check = BRANCH_HALT, 468 .clkr = { 469 .enable_reg = 0x90c0, 470 .enable_mask = BIT(0), 471 .hw.init = &(struct clk_init_data){ 472 .name = "gpu_cc_gx_ff_clk", 473 .parent_hws = (const struct clk_hw*[]) { 474 &gpu_cc_ff_clk_src.clkr.hw, 475 }, 476 .num_parents = 1, 477 .flags = CLK_SET_RATE_PARENT, 478 .ops = &clk_branch2_ops, 479 }, 480 }, 481}; 482 483static struct clk_branch gpu_cc_gx_gfx3d_clk = { 484 .halt_reg = 0x90a8, 485 .halt_check = BRANCH_HALT, 486 .clkr = { 487 .enable_reg = 0x90a8, 488 .enable_mask = BIT(0), 489 .hw.init = &(struct clk_init_data){ 490 .name = "gpu_cc_gx_gfx3d_clk", 491 .ops = &clk_branch2_ops, 492 }, 493 }, 494}; 495 496static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = { 497 .halt_reg = 0x90c8, 498 .halt_check = BRANCH_HALT, 499 .clkr = { 500 .enable_reg = 0x90c8, 501 .enable_mask = BIT(0), 502 .hw.init = &(struct clk_init_data){ 503 .name = "gpu_cc_gx_gfx3d_rdvm_clk", 504 .ops = &clk_branch2_ops, 505 }, 506 }, 507}; 508 509static struct clk_branch gpu_cc_gx_gmu_clk = { 510 .halt_reg = 0x90bc, 511 .halt_check = BRANCH_HALT, 512 .clkr = { 513 .enable_reg = 0x90bc, 514 .enable_mask = BIT(0), 515 .hw.init = &(struct clk_init_data){ 516 .name = "gpu_cc_gx_gmu_clk", 517 .parent_hws = (const struct clk_hw*[]) { 518 &gpu_cc_gmu_clk_src.clkr.hw, 519 }, 520 .num_parents = 1, 521 .flags = CLK_SET_RATE_PARENT, 522 .ops = &clk_branch2_ops, 523 }, 524 }, 525}; 526 527static struct clk_branch gpu_cc_gx_vsense_clk = { 528 .halt_reg = 0x90b0, 529 .halt_check = BRANCH_HALT_VOTED, 530 .clkr = { 531 .enable_reg = 0x90b0, 532 .enable_mask = BIT(0), 533 .hw.init = &(struct clk_init_data){ 534 .name = "gpu_cc_gx_vsense_clk", 535 .ops = &clk_branch2_ops, 536 }, 537 }, 538}; 539 540static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { 541 .halt_reg = 0x7000, 542 .halt_check = BRANCH_HALT_VOTED, 543 .clkr = { 544 .enable_reg = 0x7000, 545 .enable_mask = BIT(0), 546 .hw.init = &(struct clk_init_data){ 547 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", 548 .ops = &clk_branch2_ops, 549 }, 550 }, 551}; 552 553static struct clk_branch gpu_cc_hub_aon_clk = { 554 .halt_reg = 0x93e8, 555 .halt_check = BRANCH_HALT, 556 .clkr = { 557 .enable_reg = 0x93e8, 558 .enable_mask = BIT(0), 559 .hw.init = &(struct clk_init_data){ 560 .name = "gpu_cc_hub_aon_clk", 561 .parent_hws = (const struct clk_hw*[]) { 562 &gpu_cc_hub_clk_src.clkr.hw, 563 }, 564 .num_parents = 1, 565 .flags = CLK_SET_RATE_PARENT, 566 .ops = &clk_branch2_aon_ops, 567 }, 568 }, 569}; 570 571static struct clk_branch gpu_cc_hub_cx_int_clk = { 572 .halt_reg = 0x9148, 573 .halt_check = BRANCH_HALT, 574 .clkr = { 575 .enable_reg = 0x9148, 576 .enable_mask = BIT(0), 577 .hw.init = &(struct clk_init_data){ 578 .name = "gpu_cc_hub_cx_int_clk", 579 .parent_hws = (const struct clk_hw*[]) { 580 &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, 581 }, 582 .num_parents = 1, 583 .flags = CLK_SET_RATE_PARENT, 584 .ops = &clk_branch2_aon_ops, 585 }, 586 }, 587}; 588 589static struct clk_branch gpu_cc_memnoc_gfx_clk = { 590 .halt_reg = 0x9150, 591 .halt_check = BRANCH_HALT, 592 .clkr = { 593 .enable_reg = 0x9150, 594 .enable_mask = BIT(0), 595 .hw.init = &(struct clk_init_data){ 596 .name = "gpu_cc_memnoc_gfx_clk", 597 .ops = &clk_branch2_ops, 598 }, 599 }, 600}; 601 602static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { 603 .halt_reg = 0x9288, 604 .halt_check = BRANCH_HALT, 605 .clkr = { 606 .enable_reg = 0x9288, 607 .enable_mask = BIT(0), 608 .hw.init = &(struct clk_init_data){ 609 .name = "gpu_cc_mnd1x_0_gfx3d_clk", 610 .ops = &clk_branch2_ops, 611 }, 612 }, 613}; 614 615static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { 616 .halt_reg = 0x928c, 617 .halt_check = BRANCH_HALT, 618 .clkr = { 619 .enable_reg = 0x928c, 620 .enable_mask = BIT(0), 621 .hw.init = &(struct clk_init_data){ 622 .name = "gpu_cc_mnd1x_1_gfx3d_clk", 623 .ops = &clk_branch2_ops, 624 }, 625 }, 626}; 627 628static struct clk_branch gpu_cc_sleep_clk = { 629 .halt_reg = 0x9134, 630 .halt_check = BRANCH_HALT_VOTED, 631 .clkr = { 632 .enable_reg = 0x9134, 633 .enable_mask = BIT(0), 634 .hw.init = &(struct clk_init_data){ 635 .name = "gpu_cc_sleep_clk", 636 .ops = &clk_branch2_ops, 637 }, 638 }, 639}; 640 641static struct gdsc gpu_cx_gdsc = { 642 .gdscr = 0x9108, 643 .gds_hw_ctrl = 0x953c, 644 .clk_dis_wait_val = 8, 645 .pd = { 646 .name = "gpu_cx_gdsc", 647 }, 648 .pwrsts = PWRSTS_OFF_ON, 649 .flags = VOTABLE | RETAIN_FF_ENABLE, 650}; 651 652static struct gdsc gpu_gx_gdsc = { 653 .gdscr = 0x905c, 654 .clamp_io_ctrl = 0x9504, 655 .resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR, 656 GPUCC_GPU_CC_ACD_BCR, 657 GPUCC_GPU_CC_GX_ACD_IROOT_BCR }, 658 .reset_count = 3, 659 .pd = { 660 .name = "gpu_gx_gdsc", 661 .power_on = gdsc_gx_do_nothing_enable, 662 }, 663 .pwrsts = PWRSTS_OFF_ON, 664 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR, 665}; 666 667static struct clk_regmap *gpu_cc_sm8450_clocks[] = { 668 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 669 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 670 [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, 671 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, 672 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 673 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, 674 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 675 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 676 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, 677 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, 678 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, 679 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, 680 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 681 [GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr, 682 [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, 683 [GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr, 684 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, 685 [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, 686 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, 687 [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, 688 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 689 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 690 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 691 [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, 692 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, 693 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, 694 [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, 695 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 696 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 697 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 698 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, 699 [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr, 700}; 701 702static const struct qcom_reset_map gpu_cc_sm8450_resets[] = { 703 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, 704 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, 705 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, 706 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, 707 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, 708 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, 709 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, 710 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, 711 [GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c }, 712}; 713 714static struct gdsc *gpu_cc_sm8450_gdscs[] = { 715 [GPU_CX_GDSC] = &gpu_cx_gdsc, 716 [GPU_GX_GDSC] = &gpu_gx_gdsc, 717}; 718 719static const struct regmap_config gpu_cc_sm8450_regmap_config = { 720 .reg_bits = 32, 721 .reg_stride = 4, 722 .val_bits = 32, 723 .max_register = 0xa000, 724 .fast_io = true, 725}; 726 727static const struct qcom_cc_desc gpu_cc_sm8450_desc = { 728 .config = &gpu_cc_sm8450_regmap_config, 729 .clks = gpu_cc_sm8450_clocks, 730 .num_clks = ARRAY_SIZE(gpu_cc_sm8450_clocks), 731 .resets = gpu_cc_sm8450_resets, 732 .num_resets = ARRAY_SIZE(gpu_cc_sm8450_resets), 733 .gdscs = gpu_cc_sm8450_gdscs, 734 .num_gdscs = ARRAY_SIZE(gpu_cc_sm8450_gdscs), 735}; 736 737static const struct of_device_id gpu_cc_sm8450_match_table[] = { 738 { .compatible = "qcom,sm8450-gpucc" }, 739 { } 740}; 741MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table); 742 743static int gpu_cc_sm8450_probe(struct platform_device *pdev) 744{ 745 struct regmap *regmap; 746 747 regmap = qcom_cc_map(pdev, &gpu_cc_sm8450_desc); 748 if (IS_ERR(regmap)) 749 return PTR_ERR(regmap); 750 751 clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 752 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 753 754 return qcom_cc_really_probe(pdev, &gpu_cc_sm8450_desc, regmap); 755} 756 757static struct platform_driver gpu_cc_sm8450_driver = { 758 .probe = gpu_cc_sm8450_probe, 759 .driver = { 760 .name = "sm8450-gpucc", 761 .of_match_table = gpu_cc_sm8450_match_table, 762 }, 763}; 764module_platform_driver(gpu_cc_sm8450_driver); 765 766MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver"); 767MODULE_LICENSE("GPL"); 768