1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <linux/clk-provider.h> 7#include <linux/mod_devicetable.h> 8#include <linux/module.h> 9#include <linux/platform_device.h> 10#include <linux/pm_runtime.h> 11#include <linux/regmap.h> 12 13#include <dt-bindings/clock/qcom,x1e80100-camcc.h> 14 15#include "clk-alpha-pll.h" 16#include "clk-branch.h" 17#include "clk-rcg.h" 18#include "clk-regmap.h" 19#include "common.h" 20#include "gdsc.h" 21#include "reset.h" 22 23enum { 24 DT_IFACE, 25 DT_BI_TCXO, 26 DT_BI_TCXO_AO, 27 DT_SLEEP_CLK, 28}; 29 30enum { 31 P_BI_TCXO, 32 P_BI_TCXO_AO, 33 P_CAM_CC_PLL0_OUT_EVEN, 34 P_CAM_CC_PLL0_OUT_MAIN, 35 P_CAM_CC_PLL0_OUT_ODD, 36 P_CAM_CC_PLL1_OUT_EVEN, 37 P_CAM_CC_PLL2_OUT_EVEN, 38 P_CAM_CC_PLL2_OUT_MAIN, 39 P_CAM_CC_PLL3_OUT_EVEN, 40 P_CAM_CC_PLL4_OUT_EVEN, 41 P_CAM_CC_PLL6_OUT_EVEN, 42 P_CAM_CC_PLL8_OUT_EVEN, 43 P_SLEEP_CLK, 44}; 45 46static const struct pll_vco lucid_ole_vco[] = { 47 { 249600000, 2300000000, 0 }, 48}; 49 50static const struct pll_vco rivian_ole_vco[] = { 51 { 777000000, 1285000000, 0 }, 52}; 53 54static const struct alpha_pll_config cam_cc_pll0_config = { 55 .l = 0x3e, 56 .alpha = 0x8000, 57 .config_ctl_val = 0x20485699, 58 .config_ctl_hi_val = 0x00182261, 59 .config_ctl_hi1_val = 0x82aa299c, 60 .test_ctl_val = 0x00000000, 61 .test_ctl_hi_val = 0x00000003, 62 .test_ctl_hi1_val = 0x00009000, 63 .test_ctl_hi2_val = 0x00000034, 64 .user_ctl_val = 0x00008400, 65 .user_ctl_hi_val = 0x00000005, 66}; 67 68static struct clk_alpha_pll cam_cc_pll0 = { 69 .offset = 0x0, 70 .vco_table = lucid_ole_vco, 71 .num_vco = ARRAY_SIZE(lucid_ole_vco), 72 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 73 .clkr = { 74 .hw.init = &(const struct clk_init_data) { 75 .name = "cam_cc_pll0", 76 .parent_data = &(const struct clk_parent_data) { 77 .index = DT_BI_TCXO, 78 }, 79 .num_parents = 1, 80 .ops = &clk_alpha_pll_lucid_evo_ops, 81 }, 82 }, 83}; 84 85static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 86 { 0x1, 2 }, 87 { } 88}; 89 90static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 91 .offset = 0x0, 92 .post_div_shift = 10, 93 .post_div_table = post_div_table_cam_cc_pll0_out_even, 94 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 95 .width = 4, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 97 .clkr.hw.init = &(const struct clk_init_data) { 98 .name = "cam_cc_pll0_out_even", 99 .parent_hws = (const struct clk_hw*[]) { 100 &cam_cc_pll0.clkr.hw, 101 }, 102 .num_parents = 1, 103 .flags = CLK_SET_RATE_PARENT, 104 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 105 }, 106}; 107 108static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 109 { 0x2, 3 }, 110 { } 111}; 112 113static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 114 .offset = 0x0, 115 .post_div_shift = 14, 116 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 117 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 118 .width = 4, 119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 120 .clkr.hw.init = &(const struct clk_init_data) { 121 .name = "cam_cc_pll0_out_odd", 122 .parent_hws = (const struct clk_hw*[]) { 123 &cam_cc_pll0.clkr.hw, 124 }, 125 .num_parents = 1, 126 .flags = CLK_SET_RATE_PARENT, 127 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 128 }, 129}; 130 131static const struct alpha_pll_config cam_cc_pll1_config = { 132 .l = 0x1f, 133 .alpha = 0xaaaa, 134 .config_ctl_val = 0x20485699, 135 .config_ctl_hi_val = 0x00182261, 136 .config_ctl_hi1_val = 0x82aa299c, 137 .test_ctl_val = 0x00000000, 138 .test_ctl_hi_val = 0x00000003, 139 .test_ctl_hi1_val = 0x00009000, 140 .test_ctl_hi2_val = 0x00000034, 141 .user_ctl_val = 0x00000400, 142 .user_ctl_hi_val = 0x00000005, 143}; 144 145static struct clk_alpha_pll cam_cc_pll1 = { 146 .offset = 0x1000, 147 .vco_table = lucid_ole_vco, 148 .num_vco = ARRAY_SIZE(lucid_ole_vco), 149 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 150 .clkr = { 151 .hw.init = &(const struct clk_init_data) { 152 .name = "cam_cc_pll1", 153 .parent_data = &(const struct clk_parent_data) { 154 .index = DT_BI_TCXO, 155 }, 156 .num_parents = 1, 157 .ops = &clk_alpha_pll_lucid_evo_ops, 158 }, 159 }, 160}; 161 162static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 163 { 0x1, 2 }, 164 { } 165}; 166 167static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 168 .offset = 0x1000, 169 .post_div_shift = 10, 170 .post_div_table = post_div_table_cam_cc_pll1_out_even, 171 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 172 .width = 4, 173 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 174 .clkr.hw.init = &(const struct clk_init_data) { 175 .name = "cam_cc_pll1_out_even", 176 .parent_hws = (const struct clk_hw*[]) { 177 &cam_cc_pll1.clkr.hw, 178 }, 179 .num_parents = 1, 180 .flags = CLK_SET_RATE_PARENT, 181 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 182 }, 183}; 184 185static const struct alpha_pll_config cam_cc_pll2_config = { 186 .l = 0x32, 187 .alpha = 0x0, 188 .config_ctl_val = 0x10000030, 189 .config_ctl_hi_val = 0x80890263, 190 .config_ctl_hi1_val = 0x00000217, 191 .user_ctl_val = 0x00000001, 192 .user_ctl_hi_val = 0x00000000, 193}; 194 195static struct clk_alpha_pll cam_cc_pll2 = { 196 .offset = 0x2000, 197 .vco_table = rivian_ole_vco, 198 .num_vco = ARRAY_SIZE(rivian_ole_vco), 199 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 200 .clkr = { 201 .hw.init = &(const struct clk_init_data) { 202 .name = "cam_cc_pll2", 203 .parent_data = &(const struct clk_parent_data) { 204 .index = DT_BI_TCXO, 205 }, 206 .num_parents = 1, 207 .ops = &clk_alpha_pll_rivian_evo_ops, 208 }, 209 }, 210}; 211 212static const struct alpha_pll_config cam_cc_pll3_config = { 213 .l = 0x24, 214 .alpha = 0x0, 215 .config_ctl_val = 0x20485699, 216 .config_ctl_hi_val = 0x00182261, 217 .config_ctl_hi1_val = 0x82aa299c, 218 .test_ctl_val = 0x00000000, 219 .test_ctl_hi_val = 0x00000003, 220 .test_ctl_hi1_val = 0x00009000, 221 .test_ctl_hi2_val = 0x00000034, 222 .user_ctl_val = 0x00000400, 223 .user_ctl_hi_val = 0x00000005, 224}; 225 226static struct clk_alpha_pll cam_cc_pll3 = { 227 .offset = 0x3000, 228 .vco_table = lucid_ole_vco, 229 .num_vco = ARRAY_SIZE(lucid_ole_vco), 230 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 231 .clkr = { 232 .hw.init = &(const struct clk_init_data) { 233 .name = "cam_cc_pll3", 234 .parent_data = &(const struct clk_parent_data) { 235 .index = DT_BI_TCXO, 236 }, 237 .num_parents = 1, 238 .ops = &clk_alpha_pll_lucid_evo_ops, 239 }, 240 }, 241}; 242 243static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 244 { 0x1, 2 }, 245 { } 246}; 247 248static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 249 .offset = 0x3000, 250 .post_div_shift = 10, 251 .post_div_table = post_div_table_cam_cc_pll3_out_even, 252 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 253 .width = 4, 254 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 255 .clkr.hw.init = &(const struct clk_init_data) { 256 .name = "cam_cc_pll3_out_even", 257 .parent_hws = (const struct clk_hw*[]) { 258 &cam_cc_pll3.clkr.hw, 259 }, 260 .num_parents = 1, 261 .flags = CLK_SET_RATE_PARENT, 262 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 263 }, 264}; 265 266static const struct alpha_pll_config cam_cc_pll4_config = { 267 .l = 0x24, 268 .alpha = 0x0, 269 .config_ctl_val = 0x20485699, 270 .config_ctl_hi_val = 0x00182261, 271 .config_ctl_hi1_val = 0x82aa299c, 272 .test_ctl_val = 0x00000000, 273 .test_ctl_hi_val = 0x00000003, 274 .test_ctl_hi1_val = 0x00009000, 275 .test_ctl_hi2_val = 0x00000034, 276 .user_ctl_val = 0x00000400, 277 .user_ctl_hi_val = 0x00000005, 278}; 279 280static struct clk_alpha_pll cam_cc_pll4 = { 281 .offset = 0x4000, 282 .vco_table = lucid_ole_vco, 283 .num_vco = ARRAY_SIZE(lucid_ole_vco), 284 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 285 .clkr = { 286 .hw.init = &(const struct clk_init_data) { 287 .name = "cam_cc_pll4", 288 .parent_data = &(const struct clk_parent_data) { 289 .index = DT_BI_TCXO, 290 }, 291 .num_parents = 1, 292 .ops = &clk_alpha_pll_lucid_evo_ops, 293 }, 294 }, 295}; 296 297static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 298 { 0x1, 2 }, 299 { } 300}; 301 302static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 303 .offset = 0x4000, 304 .post_div_shift = 10, 305 .post_div_table = post_div_table_cam_cc_pll4_out_even, 306 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 307 .width = 4, 308 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 309 .clkr.hw.init = &(const struct clk_init_data) { 310 .name = "cam_cc_pll4_out_even", 311 .parent_hws = (const struct clk_hw*[]) { 312 &cam_cc_pll4.clkr.hw, 313 }, 314 .num_parents = 1, 315 .flags = CLK_SET_RATE_PARENT, 316 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 317 }, 318}; 319 320static const struct alpha_pll_config cam_cc_pll6_config = { 321 .l = 0x24, 322 .alpha = 0x0, 323 .config_ctl_val = 0x20485699, 324 .config_ctl_hi_val = 0x00182261, 325 .config_ctl_hi1_val = 0x82aa299c, 326 .test_ctl_val = 0x00000000, 327 .test_ctl_hi_val = 0x00000003, 328 .test_ctl_hi1_val = 0x00009000, 329 .test_ctl_hi2_val = 0x00000034, 330 .user_ctl_val = 0x00000400, 331 .user_ctl_hi_val = 0x00000005, 332}; 333 334static struct clk_alpha_pll cam_cc_pll6 = { 335 .offset = 0x6000, 336 .vco_table = lucid_ole_vco, 337 .num_vco = ARRAY_SIZE(lucid_ole_vco), 338 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 339 .clkr = { 340 .hw.init = &(const struct clk_init_data) { 341 .name = "cam_cc_pll6", 342 .parent_data = &(const struct clk_parent_data) { 343 .index = DT_BI_TCXO, 344 }, 345 .num_parents = 1, 346 .ops = &clk_alpha_pll_lucid_evo_ops, 347 }, 348 }, 349}; 350 351static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 352 { 0x1, 2 }, 353 { } 354}; 355 356static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 357 .offset = 0x6000, 358 .post_div_shift = 10, 359 .post_div_table = post_div_table_cam_cc_pll6_out_even, 360 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 361 .width = 4, 362 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 363 .clkr.hw.init = &(const struct clk_init_data) { 364 .name = "cam_cc_pll6_out_even", 365 .parent_hws = (const struct clk_hw*[]) { 366 &cam_cc_pll6.clkr.hw, 367 }, 368 .num_parents = 1, 369 .flags = CLK_SET_RATE_PARENT, 370 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 371 }, 372}; 373 374static const struct alpha_pll_config cam_cc_pll8_config = { 375 .l = 0x32, 376 .alpha = 0x0, 377 .config_ctl_val = 0x20485699, 378 .config_ctl_hi_val = 0x00182261, 379 .config_ctl_hi1_val = 0x82aa299c, 380 .test_ctl_val = 0x00000000, 381 .test_ctl_hi_val = 0x00000003, 382 .test_ctl_hi1_val = 0x00009000, 383 .test_ctl_hi2_val = 0x00000034, 384 .user_ctl_val = 0x00000400, 385 .user_ctl_hi_val = 0x00000005, 386}; 387 388static struct clk_alpha_pll cam_cc_pll8 = { 389 .offset = 0x8000, 390 .vco_table = lucid_ole_vco, 391 .num_vco = ARRAY_SIZE(lucid_ole_vco), 392 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 393 .clkr = { 394 .hw.init = &(const struct clk_init_data) { 395 .name = "cam_cc_pll8", 396 .parent_data = &(const struct clk_parent_data) { 397 .index = DT_BI_TCXO, 398 }, 399 .num_parents = 1, 400 .ops = &clk_alpha_pll_lucid_evo_ops, 401 }, 402 }, 403}; 404 405static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { 406 { 0x1, 2 }, 407 { } 408}; 409 410static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { 411 .offset = 0x8000, 412 .post_div_shift = 10, 413 .post_div_table = post_div_table_cam_cc_pll8_out_even, 414 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), 415 .width = 4, 416 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 417 .clkr.hw.init = &(const struct clk_init_data) { 418 .name = "cam_cc_pll8_out_even", 419 .parent_hws = (const struct clk_hw*[]) { 420 &cam_cc_pll8.clkr.hw, 421 }, 422 .num_parents = 1, 423 .flags = CLK_SET_RATE_PARENT, 424 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 425 }, 426}; 427 428static const struct parent_map cam_cc_parent_map_0[] = { 429 { P_BI_TCXO, 0 }, 430 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 431 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 432 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 433 { P_CAM_CC_PLL8_OUT_EVEN, 5 }, 434}; 435 436static const struct clk_parent_data cam_cc_parent_data_0[] = { 437 { .index = DT_BI_TCXO }, 438 { .hw = &cam_cc_pll0.clkr.hw }, 439 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 440 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 441 { .hw = &cam_cc_pll8_out_even.clkr.hw }, 442}; 443 444static const struct parent_map cam_cc_parent_map_1[] = { 445 { P_BI_TCXO, 0 }, 446 { P_CAM_CC_PLL2_OUT_EVEN, 3 }, 447 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 448}; 449 450static const struct clk_parent_data cam_cc_parent_data_1[] = { 451 { .index = DT_BI_TCXO }, 452 { .hw = &cam_cc_pll2.clkr.hw }, 453 { .hw = &cam_cc_pll2.clkr.hw }, 454}; 455 456static const struct parent_map cam_cc_parent_map_2[] = { 457 { P_BI_TCXO, 0 }, 458 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 459}; 460 461static const struct clk_parent_data cam_cc_parent_data_2[] = { 462 { .index = DT_BI_TCXO }, 463 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 464}; 465 466static const struct parent_map cam_cc_parent_map_3[] = { 467 { P_BI_TCXO, 0 }, 468 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 469}; 470 471static const struct clk_parent_data cam_cc_parent_data_3[] = { 472 { .index = DT_BI_TCXO }, 473 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 474}; 475 476static const struct parent_map cam_cc_parent_map_4[] = { 477 { P_BI_TCXO, 0 }, 478 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 479}; 480 481static const struct clk_parent_data cam_cc_parent_data_4[] = { 482 { .index = DT_BI_TCXO }, 483 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 484}; 485 486static const struct parent_map cam_cc_parent_map_5[] = { 487 { P_BI_TCXO, 0 }, 488 { P_CAM_CC_PLL6_OUT_EVEN, 6 }, 489}; 490 491static const struct clk_parent_data cam_cc_parent_data_5[] = { 492 { .index = DT_BI_TCXO }, 493 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 494}; 495 496static const struct parent_map cam_cc_parent_map_6[] = { 497 { P_SLEEP_CLK, 0 }, 498}; 499 500static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 501 { .index = DT_SLEEP_CLK }, 502}; 503 504static const struct parent_map cam_cc_parent_map_7[] = { 505 { P_BI_TCXO, 0 }, 506}; 507 508static const struct clk_parent_data cam_cc_parent_data_7_ao[] = { 509 { .index = DT_BI_TCXO_AO }, 510}; 511 512static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 513 F(19200000, P_BI_TCXO, 1, 0, 0), 514 F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 515 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 516 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 517 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 518 { } 519}; 520 521static struct clk_rcg2 cam_cc_bps_clk_src = { 522 .cmd_rcgr = 0x10278, 523 .mnd_width = 0, 524 .hid_width = 5, 525 .parent_map = cam_cc_parent_map_0, 526 .freq_tbl = ftbl_cam_cc_bps_clk_src, 527 .clkr.hw.init = &(const struct clk_init_data) { 528 .name = "cam_cc_bps_clk_src", 529 .parent_data = cam_cc_parent_data_0, 530 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 531 .flags = CLK_SET_RATE_PARENT, 532 .ops = &clk_rcg2_shared_ops, 533 }, 534}; 535 536static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { 537 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 538 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 539 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 540 { } 541}; 542 543static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { 544 .cmd_rcgr = 0x138f8, 545 .mnd_width = 0, 546 .hid_width = 5, 547 .parent_map = cam_cc_parent_map_0, 548 .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, 549 .clkr.hw.init = &(const struct clk_init_data) { 550 .name = "cam_cc_camnoc_axi_rt_clk_src", 551 .parent_data = cam_cc_parent_data_0, 552 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 553 .flags = CLK_SET_RATE_PARENT, 554 .ops = &clk_rcg2_shared_ops, 555 }, 556}; 557 558static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 559 F(19200000, P_BI_TCXO, 1, 0, 0), 560 F(30000000, P_CAM_CC_PLL8_OUT_EVEN, 16, 0, 0), 561 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 562 { } 563}; 564 565static struct clk_rcg2 cam_cc_cci_0_clk_src = { 566 .cmd_rcgr = 0x1365c, 567 .mnd_width = 8, 568 .hid_width = 5, 569 .parent_map = cam_cc_parent_map_0, 570 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 571 .clkr.hw.init = &(const struct clk_init_data) { 572 .name = "cam_cc_cci_0_clk_src", 573 .parent_data = cam_cc_parent_data_0, 574 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 575 .flags = CLK_SET_RATE_PARENT, 576 .ops = &clk_rcg2_ops, 577 }, 578}; 579 580static struct clk_rcg2 cam_cc_cci_1_clk_src = { 581 .cmd_rcgr = 0x1378c, 582 .mnd_width = 8, 583 .hid_width = 5, 584 .parent_map = cam_cc_parent_map_0, 585 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 586 .clkr.hw.init = &(const struct clk_init_data) { 587 .name = "cam_cc_cci_1_clk_src", 588 .parent_data = cam_cc_parent_data_0, 589 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 590 .flags = CLK_SET_RATE_PARENT, 591 .ops = &clk_rcg2_ops, 592 }, 593}; 594 595static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 596 F(19200000, P_BI_TCXO, 1, 0, 0), 597 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 598 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 599 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 600 { } 601}; 602 603static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 604 .cmd_rcgr = 0x11164, 605 .mnd_width = 0, 606 .hid_width = 5, 607 .parent_map = cam_cc_parent_map_0, 608 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 609 .clkr.hw.init = &(const struct clk_init_data) { 610 .name = "cam_cc_cphy_rx_clk_src", 611 .parent_data = cam_cc_parent_data_0, 612 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 613 .flags = CLK_SET_RATE_PARENT, 614 .ops = &clk_rcg2_ops, 615 }, 616}; 617 618static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 619 F(19200000, P_BI_TCXO, 1, 0, 0), 620 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 621 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 622 { } 623}; 624 625static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 626 .cmd_rcgr = 0x150e0, 627 .mnd_width = 0, 628 .hid_width = 5, 629 .parent_map = cam_cc_parent_map_0, 630 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 631 .clkr.hw.init = &(const struct clk_init_data) { 632 .name = "cam_cc_csi0phytimer_clk_src", 633 .parent_data = cam_cc_parent_data_0, 634 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 635 .flags = CLK_SET_RATE_PARENT, 636 .ops = &clk_rcg2_ops, 637 }, 638}; 639 640static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 641 .cmd_rcgr = 0x15104, 642 .mnd_width = 0, 643 .hid_width = 5, 644 .parent_map = cam_cc_parent_map_0, 645 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 646 .clkr.hw.init = &(const struct clk_init_data) { 647 .name = "cam_cc_csi1phytimer_clk_src", 648 .parent_data = cam_cc_parent_data_0, 649 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 650 .flags = CLK_SET_RATE_PARENT, 651 .ops = &clk_rcg2_ops, 652 }, 653}; 654 655static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 656 .cmd_rcgr = 0x15124, 657 .mnd_width = 0, 658 .hid_width = 5, 659 .parent_map = cam_cc_parent_map_0, 660 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 661 .clkr.hw.init = &(const struct clk_init_data) { 662 .name = "cam_cc_csi2phytimer_clk_src", 663 .parent_data = cam_cc_parent_data_0, 664 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 665 .flags = CLK_SET_RATE_PARENT, 666 .ops = &clk_rcg2_ops, 667 }, 668}; 669 670static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 671 .cmd_rcgr = 0x15258, 672 .mnd_width = 0, 673 .hid_width = 5, 674 .parent_map = cam_cc_parent_map_0, 675 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 676 .clkr.hw.init = &(const struct clk_init_data) { 677 .name = "cam_cc_csi3phytimer_clk_src", 678 .parent_data = cam_cc_parent_data_0, 679 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 680 .flags = CLK_SET_RATE_PARENT, 681 .ops = &clk_rcg2_ops, 682 }, 683}; 684 685static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 686 .cmd_rcgr = 0x1538c, 687 .mnd_width = 0, 688 .hid_width = 5, 689 .parent_map = cam_cc_parent_map_0, 690 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 691 .clkr.hw.init = &(const struct clk_init_data) { 692 .name = "cam_cc_csi4phytimer_clk_src", 693 .parent_data = cam_cc_parent_data_0, 694 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 695 .flags = CLK_SET_RATE_PARENT, 696 .ops = &clk_rcg2_ops, 697 }, 698}; 699 700static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 701 .cmd_rcgr = 0x154c0, 702 .mnd_width = 0, 703 .hid_width = 5, 704 .parent_map = cam_cc_parent_map_0, 705 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 706 .clkr.hw.init = &(const struct clk_init_data) { 707 .name = "cam_cc_csi5phytimer_clk_src", 708 .parent_data = cam_cc_parent_data_0, 709 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 710 .flags = CLK_SET_RATE_PARENT, 711 .ops = &clk_rcg2_ops, 712 }, 713}; 714 715static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { 716 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 717 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 718 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 719 { } 720}; 721 722static struct clk_rcg2 cam_cc_csid_clk_src = { 723 .cmd_rcgr = 0x138d4, 724 .mnd_width = 0, 725 .hid_width = 5, 726 .parent_map = cam_cc_parent_map_0, 727 .freq_tbl = ftbl_cam_cc_csid_clk_src, 728 .clkr.hw.init = &(const struct clk_init_data) { 729 .name = "cam_cc_csid_clk_src", 730 .parent_data = cam_cc_parent_data_0, 731 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 732 .flags = CLK_SET_RATE_PARENT, 733 .ops = &clk_rcg2_shared_ops, 734 }, 735}; 736 737static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 738 F(19200000, P_BI_TCXO, 1, 0, 0), 739 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 740 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 741 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 742 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 743 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 744 { } 745}; 746 747static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 748 .cmd_rcgr = 0x10018, 749 .mnd_width = 0, 750 .hid_width = 5, 751 .parent_map = cam_cc_parent_map_0, 752 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 753 .clkr.hw.init = &(const struct clk_init_data) { 754 .name = "cam_cc_fast_ahb_clk_src", 755 .parent_data = cam_cc_parent_data_0, 756 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 757 .flags = CLK_SET_RATE_PARENT, 758 .ops = &clk_rcg2_shared_ops, 759 }, 760}; 761 762static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 763 F(19200000, P_BI_TCXO, 1, 0, 0), 764 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 765 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 766 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 767 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 768 { } 769}; 770 771static struct clk_rcg2 cam_cc_icp_clk_src = { 772 .cmd_rcgr = 0x13520, 773 .mnd_width = 0, 774 .hid_width = 5, 775 .parent_map = cam_cc_parent_map_0, 776 .freq_tbl = ftbl_cam_cc_icp_clk_src, 777 .clkr.hw.init = &(const struct clk_init_data) { 778 .name = "cam_cc_icp_clk_src", 779 .parent_data = cam_cc_parent_data_0, 780 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 781 .flags = CLK_SET_RATE_PARENT, 782 .ops = &clk_rcg2_shared_ops, 783 }, 784}; 785 786static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 787 F(19200000, P_BI_TCXO, 1, 0, 0), 788 F(345600000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 789 F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 790 F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 791 F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 792 F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 793 { } 794}; 795 796static struct clk_rcg2 cam_cc_ife_0_clk_src = { 797 .cmd_rcgr = 0x11018, 798 .mnd_width = 0, 799 .hid_width = 5, 800 .parent_map = cam_cc_parent_map_2, 801 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 802 .clkr.hw.init = &(const struct clk_init_data) { 803 .name = "cam_cc_ife_0_clk_src", 804 .parent_data = cam_cc_parent_data_2, 805 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 806 .flags = CLK_SET_RATE_PARENT, 807 .ops = &clk_rcg2_shared_ops, 808 }, 809}; 810 811static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 812 F(19200000, P_BI_TCXO, 1, 0, 0), 813 F(345600000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 814 F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 815 F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 816 F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 817 F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 818 { } 819}; 820 821static struct clk_rcg2 cam_cc_ife_1_clk_src = { 822 .cmd_rcgr = 0x12018, 823 .mnd_width = 0, 824 .hid_width = 5, 825 .parent_map = cam_cc_parent_map_3, 826 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 827 .clkr.hw.init = &(const struct clk_init_data) { 828 .name = "cam_cc_ife_1_clk_src", 829 .parent_data = cam_cc_parent_data_3, 830 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 831 .flags = CLK_SET_RATE_PARENT, 832 .ops = &clk_rcg2_shared_ops, 833 }, 834}; 835 836static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { 837 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 838 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 839 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 840 { } 841}; 842 843static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 844 .cmd_rcgr = 0x13000, 845 .mnd_width = 0, 846 .hid_width = 5, 847 .parent_map = cam_cc_parent_map_0, 848 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 849 .clkr.hw.init = &(const struct clk_init_data) { 850 .name = "cam_cc_ife_lite_clk_src", 851 .parent_data = cam_cc_parent_data_0, 852 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 853 .flags = CLK_SET_RATE_PARENT, 854 .ops = &clk_rcg2_shared_ops, 855 }, 856}; 857 858static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 859 .cmd_rcgr = 0x1313c, 860 .mnd_width = 0, 861 .hid_width = 5, 862 .parent_map = cam_cc_parent_map_0, 863 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 864 .clkr.hw.init = &(const struct clk_init_data) { 865 .name = "cam_cc_ife_lite_csid_clk_src", 866 .parent_data = cam_cc_parent_data_0, 867 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 868 .flags = CLK_SET_RATE_PARENT, 869 .ops = &clk_rcg2_shared_ops, 870 }, 871}; 872 873static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 874 F(304000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 875 F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 876 F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 877 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 878 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 879 { } 880}; 881 882static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 883 .cmd_rcgr = 0x103cc, 884 .mnd_width = 0, 885 .hid_width = 5, 886 .parent_map = cam_cc_parent_map_4, 887 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 888 .clkr.hw.init = &(const struct clk_init_data) { 889 .name = "cam_cc_ipe_nps_clk_src", 890 .parent_data = cam_cc_parent_data_4, 891 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 892 .flags = CLK_SET_RATE_PARENT, 893 .ops = &clk_rcg2_shared_ops, 894 }, 895}; 896 897static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 898 F(19200000, P_BI_TCXO, 1, 0, 0), 899 F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 900 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 901 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 902 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 903 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 904 { } 905}; 906 907static struct clk_rcg2 cam_cc_jpeg_clk_src = { 908 .cmd_rcgr = 0x133dc, 909 .mnd_width = 0, 910 .hid_width = 5, 911 .parent_map = cam_cc_parent_map_0, 912 .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 913 .clkr.hw.init = &(const struct clk_init_data) { 914 .name = "cam_cc_jpeg_clk_src", 915 .parent_data = cam_cc_parent_data_0, 916 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 917 .flags = CLK_SET_RATE_PARENT, 918 .ops = &clk_rcg2_shared_ops, 919 }, 920}; 921 922static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 923 F(19200000, P_BI_TCXO, 1, 0, 0), 924 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 925 F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), 926 { } 927}; 928 929static struct clk_rcg2 cam_cc_mclk0_clk_src = { 930 .cmd_rcgr = 0x15000, 931 .mnd_width = 8, 932 .hid_width = 5, 933 .parent_map = cam_cc_parent_map_1, 934 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 935 .clkr.hw.init = &(const struct clk_init_data) { 936 .name = "cam_cc_mclk0_clk_src", 937 .parent_data = cam_cc_parent_data_1, 938 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 939 .flags = CLK_SET_RATE_PARENT, 940 .ops = &clk_rcg2_ops, 941 }, 942}; 943 944static struct clk_rcg2 cam_cc_mclk1_clk_src = { 945 .cmd_rcgr = 0x1501c, 946 .mnd_width = 8, 947 .hid_width = 5, 948 .parent_map = cam_cc_parent_map_1, 949 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 950 .clkr.hw.init = &(const struct clk_init_data) { 951 .name = "cam_cc_mclk1_clk_src", 952 .parent_data = cam_cc_parent_data_1, 953 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 954 .flags = CLK_SET_RATE_PARENT, 955 .ops = &clk_rcg2_ops, 956 }, 957}; 958 959static struct clk_rcg2 cam_cc_mclk2_clk_src = { 960 .cmd_rcgr = 0x15038, 961 .mnd_width = 8, 962 .hid_width = 5, 963 .parent_map = cam_cc_parent_map_1, 964 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 965 .clkr.hw.init = &(const struct clk_init_data) { 966 .name = "cam_cc_mclk2_clk_src", 967 .parent_data = cam_cc_parent_data_1, 968 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 969 .flags = CLK_SET_RATE_PARENT, 970 .ops = &clk_rcg2_ops, 971 }, 972}; 973 974static struct clk_rcg2 cam_cc_mclk3_clk_src = { 975 .cmd_rcgr = 0x15054, 976 .mnd_width = 8, 977 .hid_width = 5, 978 .parent_map = cam_cc_parent_map_1, 979 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 980 .clkr.hw.init = &(const struct clk_init_data) { 981 .name = "cam_cc_mclk3_clk_src", 982 .parent_data = cam_cc_parent_data_1, 983 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 984 .flags = CLK_SET_RATE_PARENT, 985 .ops = &clk_rcg2_ops, 986 }, 987}; 988 989static struct clk_rcg2 cam_cc_mclk4_clk_src = { 990 .cmd_rcgr = 0x15070, 991 .mnd_width = 8, 992 .hid_width = 5, 993 .parent_map = cam_cc_parent_map_1, 994 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 995 .clkr.hw.init = &(const struct clk_init_data) { 996 .name = "cam_cc_mclk4_clk_src", 997 .parent_data = cam_cc_parent_data_1, 998 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 999 .flags = CLK_SET_RATE_PARENT, 1000 .ops = &clk_rcg2_ops, 1001 }, 1002}; 1003 1004static struct clk_rcg2 cam_cc_mclk5_clk_src = { 1005 .cmd_rcgr = 0x1508c, 1006 .mnd_width = 8, 1007 .hid_width = 5, 1008 .parent_map = cam_cc_parent_map_1, 1009 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1010 .clkr.hw.init = &(const struct clk_init_data) { 1011 .name = "cam_cc_mclk5_clk_src", 1012 .parent_data = cam_cc_parent_data_1, 1013 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_rcg2_ops, 1016 }, 1017}; 1018 1019static struct clk_rcg2 cam_cc_mclk6_clk_src = { 1020 .cmd_rcgr = 0x150a8, 1021 .mnd_width = 8, 1022 .hid_width = 5, 1023 .parent_map = cam_cc_parent_map_1, 1024 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1025 .clkr.hw.init = &(const struct clk_init_data) { 1026 .name = "cam_cc_mclk6_clk_src", 1027 .parent_data = cam_cc_parent_data_1, 1028 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1029 .flags = CLK_SET_RATE_PARENT, 1030 .ops = &clk_rcg2_ops, 1031 }, 1032}; 1033 1034static struct clk_rcg2 cam_cc_mclk7_clk_src = { 1035 .cmd_rcgr = 0x150c4, 1036 .mnd_width = 8, 1037 .hid_width = 5, 1038 .parent_map = cam_cc_parent_map_1, 1039 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1040 .clkr.hw.init = &(const struct clk_init_data) { 1041 .name = "cam_cc_mclk7_clk_src", 1042 .parent_data = cam_cc_parent_data_1, 1043 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1044 .flags = CLK_SET_RATE_PARENT, 1045 .ops = &clk_rcg2_ops, 1046 }, 1047}; 1048 1049static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { 1050 F(345600000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1051 F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1052 F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1053 F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1054 F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1055 { } 1056}; 1057 1058static struct clk_rcg2 cam_cc_sfe_0_clk_src = { 1059 .cmd_rcgr = 0x13294, 1060 .mnd_width = 0, 1061 .hid_width = 5, 1062 .parent_map = cam_cc_parent_map_5, 1063 .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, 1064 .clkr.hw.init = &(const struct clk_init_data) { 1065 .name = "cam_cc_sfe_0_clk_src", 1066 .parent_data = cam_cc_parent_data_5, 1067 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1068 .flags = CLK_SET_RATE_PARENT, 1069 .ops = &clk_rcg2_shared_ops, 1070 }, 1071}; 1072 1073static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 1074 F(32000, P_SLEEP_CLK, 1, 0, 0), 1075 { } 1076}; 1077 1078static struct clk_rcg2 cam_cc_sleep_clk_src = { 1079 .cmd_rcgr = 0x13aa0, 1080 .mnd_width = 0, 1081 .hid_width = 5, 1082 .parent_map = cam_cc_parent_map_6, 1083 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 1084 .clkr.hw.init = &(const struct clk_init_data) { 1085 .name = "cam_cc_sleep_clk_src", 1086 .parent_data = cam_cc_parent_data_6_ao, 1087 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 1088 .flags = CLK_SET_RATE_PARENT, 1089 .ops = &clk_rcg2_ops, 1090 }, 1091}; 1092 1093static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 1094 F(19200000, P_BI_TCXO, 1, 0, 0), 1095 F(64000000, P_CAM_CC_PLL8_OUT_EVEN, 7.5, 0, 0), 1096 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 1097 { } 1098}; 1099 1100static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 1101 .cmd_rcgr = 0x10148, 1102 .mnd_width = 8, 1103 .hid_width = 5, 1104 .parent_map = cam_cc_parent_map_0, 1105 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 1106 .clkr.hw.init = &(const struct clk_init_data) { 1107 .name = "cam_cc_slow_ahb_clk_src", 1108 .parent_data = cam_cc_parent_data_0, 1109 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1110 .flags = CLK_SET_RATE_PARENT, 1111 .ops = &clk_rcg2_shared_ops, 1112 }, 1113}; 1114 1115static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1116 F(19200000, P_BI_TCXO, 1, 0, 0), 1117 { } 1118}; 1119 1120static struct clk_rcg2 cam_cc_xo_clk_src = { 1121 .cmd_rcgr = 0x13a84, 1122 .mnd_width = 0, 1123 .hid_width = 5, 1124 .parent_map = cam_cc_parent_map_7, 1125 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1126 .clkr.hw.init = &(const struct clk_init_data) { 1127 .name = "cam_cc_xo_clk_src", 1128 .parent_data = cam_cc_parent_data_7_ao, 1129 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7_ao), 1130 .flags = CLK_SET_RATE_PARENT, 1131 .ops = &clk_rcg2_ops, 1132 }, 1133}; 1134 1135static struct clk_branch cam_cc_bps_ahb_clk = { 1136 .halt_reg = 0x10274, 1137 .halt_check = BRANCH_HALT, 1138 .clkr = { 1139 .enable_reg = 0x10274, 1140 .enable_mask = BIT(0), 1141 .hw.init = &(const struct clk_init_data) { 1142 .name = "cam_cc_bps_ahb_clk", 1143 .parent_hws = (const struct clk_hw*[]) { 1144 &cam_cc_slow_ahb_clk_src.clkr.hw, 1145 }, 1146 .num_parents = 1, 1147 .flags = CLK_SET_RATE_PARENT, 1148 .ops = &clk_branch2_ops, 1149 }, 1150 }, 1151}; 1152 1153static struct clk_branch cam_cc_bps_clk = { 1154 .halt_reg = 0x103a4, 1155 .halt_check = BRANCH_HALT, 1156 .clkr = { 1157 .enable_reg = 0x103a4, 1158 .enable_mask = BIT(0), 1159 .hw.init = &(const struct clk_init_data) { 1160 .name = "cam_cc_bps_clk", 1161 .parent_hws = (const struct clk_hw*[]) { 1162 &cam_cc_bps_clk_src.clkr.hw, 1163 }, 1164 .num_parents = 1, 1165 .flags = CLK_SET_RATE_PARENT, 1166 .ops = &clk_branch2_ops, 1167 }, 1168 }, 1169}; 1170 1171static struct clk_branch cam_cc_bps_fast_ahb_clk = { 1172 .halt_reg = 0x10144, 1173 .halt_check = BRANCH_HALT, 1174 .clkr = { 1175 .enable_reg = 0x10144, 1176 .enable_mask = BIT(0), 1177 .hw.init = &(const struct clk_init_data) { 1178 .name = "cam_cc_bps_fast_ahb_clk", 1179 .parent_hws = (const struct clk_hw*[]) { 1180 &cam_cc_fast_ahb_clk_src.clkr.hw, 1181 }, 1182 .num_parents = 1, 1183 .flags = CLK_SET_RATE_PARENT, 1184 .ops = &clk_branch2_ops, 1185 }, 1186 }, 1187}; 1188 1189static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { 1190 .halt_reg = 0x13920, 1191 .halt_check = BRANCH_HALT, 1192 .clkr = { 1193 .enable_reg = 0x13920, 1194 .enable_mask = BIT(0), 1195 .hw.init = &(const struct clk_init_data) { 1196 .name = "cam_cc_camnoc_axi_nrt_clk", 1197 .parent_hws = (const struct clk_hw*[]) { 1198 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1199 }, 1200 .num_parents = 1, 1201 .flags = CLK_SET_RATE_PARENT, 1202 .ops = &clk_branch2_ops, 1203 }, 1204 }, 1205}; 1206 1207static struct clk_branch cam_cc_camnoc_axi_rt_clk = { 1208 .halt_reg = 0x13910, 1209 .halt_check = BRANCH_HALT, 1210 .clkr = { 1211 .enable_reg = 0x13910, 1212 .enable_mask = BIT(0), 1213 .hw.init = &(const struct clk_init_data) { 1214 .name = "cam_cc_camnoc_axi_rt_clk", 1215 .parent_hws = (const struct clk_hw*[]) { 1216 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1217 }, 1218 .num_parents = 1, 1219 .flags = CLK_SET_RATE_PARENT, 1220 .ops = &clk_branch2_ops, 1221 }, 1222 }, 1223}; 1224 1225static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1226 .halt_reg = 0x1392c, 1227 .halt_check = BRANCH_HALT, 1228 .clkr = { 1229 .enable_reg = 0x1392c, 1230 .enable_mask = BIT(0), 1231 .hw.init = &(const struct clk_init_data) { 1232 .name = "cam_cc_camnoc_dcd_xo_clk", 1233 .parent_hws = (const struct clk_hw*[]) { 1234 &cam_cc_xo_clk_src.clkr.hw, 1235 }, 1236 .num_parents = 1, 1237 .flags = CLK_SET_RATE_PARENT, 1238 .ops = &clk_branch2_ops, 1239 }, 1240 }, 1241}; 1242 1243static struct clk_branch cam_cc_camnoc_xo_clk = { 1244 .halt_reg = 0x13930, 1245 .halt_check = BRANCH_HALT, 1246 .clkr = { 1247 .enable_reg = 0x13930, 1248 .enable_mask = BIT(0), 1249 .hw.init = &(const struct clk_init_data) { 1250 .name = "cam_cc_camnoc_xo_clk", 1251 .parent_hws = (const struct clk_hw*[]) { 1252 &cam_cc_xo_clk_src.clkr.hw, 1253 }, 1254 .num_parents = 1, 1255 .flags = CLK_SET_RATE_PARENT, 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259}; 1260 1261static struct clk_branch cam_cc_cci_0_clk = { 1262 .halt_reg = 0x13788, 1263 .halt_check = BRANCH_HALT, 1264 .clkr = { 1265 .enable_reg = 0x13788, 1266 .enable_mask = BIT(0), 1267 .hw.init = &(const struct clk_init_data) { 1268 .name = "cam_cc_cci_0_clk", 1269 .parent_hws = (const struct clk_hw*[]) { 1270 &cam_cc_cci_0_clk_src.clkr.hw, 1271 }, 1272 .num_parents = 1, 1273 .flags = CLK_SET_RATE_PARENT, 1274 .ops = &clk_branch2_ops, 1275 }, 1276 }, 1277}; 1278 1279static struct clk_branch cam_cc_cci_1_clk = { 1280 .halt_reg = 0x138b8, 1281 .halt_check = BRANCH_HALT, 1282 .clkr = { 1283 .enable_reg = 0x138b8, 1284 .enable_mask = BIT(0), 1285 .hw.init = &(const struct clk_init_data) { 1286 .name = "cam_cc_cci_1_clk", 1287 .parent_hws = (const struct clk_hw*[]) { 1288 &cam_cc_cci_1_clk_src.clkr.hw, 1289 }, 1290 .num_parents = 1, 1291 .flags = CLK_SET_RATE_PARENT, 1292 .ops = &clk_branch2_ops, 1293 }, 1294 }, 1295}; 1296 1297static struct clk_branch cam_cc_core_ahb_clk = { 1298 .halt_reg = 0x13a80, 1299 .halt_check = BRANCH_HALT_VOTED, 1300 .clkr = { 1301 .enable_reg = 0x13a80, 1302 .enable_mask = BIT(0), 1303 .hw.init = &(const struct clk_init_data) { 1304 .name = "cam_cc_core_ahb_clk", 1305 .parent_hws = (const struct clk_hw*[]) { 1306 &cam_cc_slow_ahb_clk_src.clkr.hw, 1307 }, 1308 .num_parents = 1, 1309 .flags = CLK_SET_RATE_PARENT, 1310 .ops = &clk_branch2_ops, 1311 }, 1312 }, 1313}; 1314 1315static struct clk_branch cam_cc_cpas_ahb_clk = { 1316 .halt_reg = 0x138bc, 1317 .halt_check = BRANCH_HALT, 1318 .clkr = { 1319 .enable_reg = 0x138bc, 1320 .enable_mask = BIT(0), 1321 .hw.init = &(const struct clk_init_data) { 1322 .name = "cam_cc_cpas_ahb_clk", 1323 .parent_hws = (const struct clk_hw*[]) { 1324 &cam_cc_slow_ahb_clk_src.clkr.hw, 1325 }, 1326 .num_parents = 1, 1327 .flags = CLK_SET_RATE_PARENT, 1328 .ops = &clk_branch2_ops, 1329 }, 1330 }, 1331}; 1332 1333static struct clk_branch cam_cc_cpas_bps_clk = { 1334 .halt_reg = 0x103b0, 1335 .halt_check = BRANCH_HALT, 1336 .clkr = { 1337 .enable_reg = 0x103b0, 1338 .enable_mask = BIT(0), 1339 .hw.init = &(const struct clk_init_data) { 1340 .name = "cam_cc_cpas_bps_clk", 1341 .parent_hws = (const struct clk_hw*[]) { 1342 &cam_cc_bps_clk_src.clkr.hw, 1343 }, 1344 .num_parents = 1, 1345 .flags = CLK_SET_RATE_PARENT, 1346 .ops = &clk_branch2_ops, 1347 }, 1348 }, 1349}; 1350 1351static struct clk_branch cam_cc_cpas_fast_ahb_clk = { 1352 .halt_reg = 0x138c8, 1353 .halt_check = BRANCH_HALT, 1354 .clkr = { 1355 .enable_reg = 0x138c8, 1356 .enable_mask = BIT(0), 1357 .hw.init = &(const struct clk_init_data) { 1358 .name = "cam_cc_cpas_fast_ahb_clk", 1359 .parent_hws = (const struct clk_hw*[]) { 1360 &cam_cc_fast_ahb_clk_src.clkr.hw, 1361 }, 1362 .num_parents = 1, 1363 .flags = CLK_SET_RATE_PARENT, 1364 .ops = &clk_branch2_ops, 1365 }, 1366 }, 1367}; 1368 1369static struct clk_branch cam_cc_cpas_ife_0_clk = { 1370 .halt_reg = 0x11150, 1371 .halt_check = BRANCH_HALT, 1372 .clkr = { 1373 .enable_reg = 0x11150, 1374 .enable_mask = BIT(0), 1375 .hw.init = &(const struct clk_init_data) { 1376 .name = "cam_cc_cpas_ife_0_clk", 1377 .parent_hws = (const struct clk_hw*[]) { 1378 &cam_cc_ife_0_clk_src.clkr.hw, 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_SET_RATE_PARENT, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385}; 1386 1387static struct clk_branch cam_cc_cpas_ife_1_clk = { 1388 .halt_reg = 0x1203c, 1389 .halt_check = BRANCH_HALT, 1390 .clkr = { 1391 .enable_reg = 0x1203c, 1392 .enable_mask = BIT(0), 1393 .hw.init = &(const struct clk_init_data) { 1394 .name = "cam_cc_cpas_ife_1_clk", 1395 .parent_hws = (const struct clk_hw*[]) { 1396 &cam_cc_ife_1_clk_src.clkr.hw, 1397 }, 1398 .num_parents = 1, 1399 .flags = CLK_SET_RATE_PARENT, 1400 .ops = &clk_branch2_ops, 1401 }, 1402 }, 1403}; 1404 1405static struct clk_branch cam_cc_cpas_ife_lite_clk = { 1406 .halt_reg = 0x13138, 1407 .halt_check = BRANCH_HALT, 1408 .clkr = { 1409 .enable_reg = 0x13138, 1410 .enable_mask = BIT(0), 1411 .hw.init = &(const struct clk_init_data) { 1412 .name = "cam_cc_cpas_ife_lite_clk", 1413 .parent_hws = (const struct clk_hw*[]) { 1414 &cam_cc_ife_lite_clk_src.clkr.hw, 1415 }, 1416 .num_parents = 1, 1417 .flags = CLK_SET_RATE_PARENT, 1418 .ops = &clk_branch2_ops, 1419 }, 1420 }, 1421}; 1422 1423static struct clk_branch cam_cc_cpas_ipe_nps_clk = { 1424 .halt_reg = 0x10504, 1425 .halt_check = BRANCH_HALT, 1426 .clkr = { 1427 .enable_reg = 0x10504, 1428 .enable_mask = BIT(0), 1429 .hw.init = &(const struct clk_init_data) { 1430 .name = "cam_cc_cpas_ipe_nps_clk", 1431 .parent_hws = (const struct clk_hw*[]) { 1432 &cam_cc_ipe_nps_clk_src.clkr.hw, 1433 }, 1434 .num_parents = 1, 1435 .flags = CLK_SET_RATE_PARENT, 1436 .ops = &clk_branch2_ops, 1437 }, 1438 }, 1439}; 1440 1441static struct clk_branch cam_cc_cpas_sfe_0_clk = { 1442 .halt_reg = 0x133cc, 1443 .halt_check = BRANCH_HALT, 1444 .clkr = { 1445 .enable_reg = 0x133cc, 1446 .enable_mask = BIT(0), 1447 .hw.init = &(const struct clk_init_data) { 1448 .name = "cam_cc_cpas_sfe_0_clk", 1449 .parent_hws = (const struct clk_hw*[]) { 1450 &cam_cc_sfe_0_clk_src.clkr.hw, 1451 }, 1452 .num_parents = 1, 1453 .flags = CLK_SET_RATE_PARENT, 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457}; 1458 1459static struct clk_branch cam_cc_csi0phytimer_clk = { 1460 .halt_reg = 0x150f8, 1461 .halt_check = BRANCH_HALT, 1462 .clkr = { 1463 .enable_reg = 0x150f8, 1464 .enable_mask = BIT(0), 1465 .hw.init = &(const struct clk_init_data) { 1466 .name = "cam_cc_csi0phytimer_clk", 1467 .parent_hws = (const struct clk_hw*[]) { 1468 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1469 }, 1470 .num_parents = 1, 1471 .flags = CLK_SET_RATE_PARENT, 1472 .ops = &clk_branch2_ops, 1473 }, 1474 }, 1475}; 1476 1477static struct clk_branch cam_cc_csi1phytimer_clk = { 1478 .halt_reg = 0x1511c, 1479 .halt_check = BRANCH_HALT, 1480 .clkr = { 1481 .enable_reg = 0x1511c, 1482 .enable_mask = BIT(0), 1483 .hw.init = &(const struct clk_init_data) { 1484 .name = "cam_cc_csi1phytimer_clk", 1485 .parent_hws = (const struct clk_hw*[]) { 1486 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1487 }, 1488 .num_parents = 1, 1489 .flags = CLK_SET_RATE_PARENT, 1490 .ops = &clk_branch2_ops, 1491 }, 1492 }, 1493}; 1494 1495static struct clk_branch cam_cc_csi2phytimer_clk = { 1496 .halt_reg = 0x15250, 1497 .halt_check = BRANCH_HALT, 1498 .clkr = { 1499 .enable_reg = 0x15250, 1500 .enable_mask = BIT(0), 1501 .hw.init = &(const struct clk_init_data) { 1502 .name = "cam_cc_csi2phytimer_clk", 1503 .parent_hws = (const struct clk_hw*[]) { 1504 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1505 }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT, 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511}; 1512 1513static struct clk_branch cam_cc_csi3phytimer_clk = { 1514 .halt_reg = 0x15384, 1515 .halt_check = BRANCH_HALT, 1516 .clkr = { 1517 .enable_reg = 0x15384, 1518 .enable_mask = BIT(0), 1519 .hw.init = &(const struct clk_init_data) { 1520 .name = "cam_cc_csi3phytimer_clk", 1521 .parent_hws = (const struct clk_hw*[]) { 1522 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1523 }, 1524 .num_parents = 1, 1525 .flags = CLK_SET_RATE_PARENT, 1526 .ops = &clk_branch2_ops, 1527 }, 1528 }, 1529}; 1530 1531static struct clk_branch cam_cc_csi4phytimer_clk = { 1532 .halt_reg = 0x154b8, 1533 .halt_check = BRANCH_HALT, 1534 .clkr = { 1535 .enable_reg = 0x154b8, 1536 .enable_mask = BIT(0), 1537 .hw.init = &(const struct clk_init_data) { 1538 .name = "cam_cc_csi4phytimer_clk", 1539 .parent_hws = (const struct clk_hw*[]) { 1540 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1541 }, 1542 .num_parents = 1, 1543 .flags = CLK_SET_RATE_PARENT, 1544 .ops = &clk_branch2_ops, 1545 }, 1546 }, 1547}; 1548 1549static struct clk_branch cam_cc_csi5phytimer_clk = { 1550 .halt_reg = 0x155ec, 1551 .halt_check = BRANCH_HALT, 1552 .clkr = { 1553 .enable_reg = 0x155ec, 1554 .enable_mask = BIT(0), 1555 .hw.init = &(const struct clk_init_data) { 1556 .name = "cam_cc_csi5phytimer_clk", 1557 .parent_hws = (const struct clk_hw*[]) { 1558 &cam_cc_csi5phytimer_clk_src.clkr.hw, 1559 }, 1560 .num_parents = 1, 1561 .flags = CLK_SET_RATE_PARENT, 1562 .ops = &clk_branch2_ops, 1563 }, 1564 }, 1565}; 1566 1567static struct clk_branch cam_cc_csid_clk = { 1568 .halt_reg = 0x138ec, 1569 .halt_check = BRANCH_HALT, 1570 .clkr = { 1571 .enable_reg = 0x138ec, 1572 .enable_mask = BIT(0), 1573 .hw.init = &(const struct clk_init_data) { 1574 .name = "cam_cc_csid_clk", 1575 .parent_hws = (const struct clk_hw*[]) { 1576 &cam_cc_csid_clk_src.clkr.hw, 1577 }, 1578 .num_parents = 1, 1579 .flags = CLK_SET_RATE_PARENT, 1580 .ops = &clk_branch2_ops, 1581 }, 1582 }, 1583}; 1584 1585static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1586 .halt_reg = 0x15100, 1587 .halt_check = BRANCH_HALT, 1588 .clkr = { 1589 .enable_reg = 0x15100, 1590 .enable_mask = BIT(0), 1591 .hw.init = &(const struct clk_init_data) { 1592 .name = "cam_cc_csid_csiphy_rx_clk", 1593 .parent_hws = (const struct clk_hw*[]) { 1594 &cam_cc_cphy_rx_clk_src.clkr.hw, 1595 }, 1596 .num_parents = 1, 1597 .flags = CLK_SET_RATE_PARENT, 1598 .ops = &clk_branch2_ops, 1599 }, 1600 }, 1601}; 1602 1603static struct clk_branch cam_cc_csiphy0_clk = { 1604 .halt_reg = 0x150fc, 1605 .halt_check = BRANCH_HALT, 1606 .clkr = { 1607 .enable_reg = 0x150fc, 1608 .enable_mask = BIT(0), 1609 .hw.init = &(const struct clk_init_data) { 1610 .name = "cam_cc_csiphy0_clk", 1611 .parent_hws = (const struct clk_hw*[]) { 1612 &cam_cc_cphy_rx_clk_src.clkr.hw, 1613 }, 1614 .num_parents = 1, 1615 .flags = CLK_SET_RATE_PARENT, 1616 .ops = &clk_branch2_ops, 1617 }, 1618 }, 1619}; 1620 1621static struct clk_branch cam_cc_csiphy1_clk = { 1622 .halt_reg = 0x15120, 1623 .halt_check = BRANCH_HALT, 1624 .clkr = { 1625 .enable_reg = 0x15120, 1626 .enable_mask = BIT(0), 1627 .hw.init = &(const struct clk_init_data) { 1628 .name = "cam_cc_csiphy1_clk", 1629 .parent_hws = (const struct clk_hw*[]) { 1630 &cam_cc_cphy_rx_clk_src.clkr.hw, 1631 }, 1632 .num_parents = 1, 1633 .flags = CLK_SET_RATE_PARENT, 1634 .ops = &clk_branch2_ops, 1635 }, 1636 }, 1637}; 1638 1639static struct clk_branch cam_cc_csiphy2_clk = { 1640 .halt_reg = 0x15254, 1641 .halt_check = BRANCH_HALT, 1642 .clkr = { 1643 .enable_reg = 0x15254, 1644 .enable_mask = BIT(0), 1645 .hw.init = &(const struct clk_init_data) { 1646 .name = "cam_cc_csiphy2_clk", 1647 .parent_hws = (const struct clk_hw*[]) { 1648 &cam_cc_cphy_rx_clk_src.clkr.hw, 1649 }, 1650 .num_parents = 1, 1651 .flags = CLK_SET_RATE_PARENT, 1652 .ops = &clk_branch2_ops, 1653 }, 1654 }, 1655}; 1656 1657static struct clk_branch cam_cc_csiphy3_clk = { 1658 .halt_reg = 0x15388, 1659 .halt_check = BRANCH_HALT, 1660 .clkr = { 1661 .enable_reg = 0x15388, 1662 .enable_mask = BIT(0), 1663 .hw.init = &(const struct clk_init_data) { 1664 .name = "cam_cc_csiphy3_clk", 1665 .parent_hws = (const struct clk_hw*[]) { 1666 &cam_cc_cphy_rx_clk_src.clkr.hw, 1667 }, 1668 .num_parents = 1, 1669 .flags = CLK_SET_RATE_PARENT, 1670 .ops = &clk_branch2_ops, 1671 }, 1672 }, 1673}; 1674 1675static struct clk_branch cam_cc_csiphy4_clk = { 1676 .halt_reg = 0x154bc, 1677 .halt_check = BRANCH_HALT, 1678 .clkr = { 1679 .enable_reg = 0x154bc, 1680 .enable_mask = BIT(0), 1681 .hw.init = &(const struct clk_init_data) { 1682 .name = "cam_cc_csiphy4_clk", 1683 .parent_hws = (const struct clk_hw*[]) { 1684 &cam_cc_cphy_rx_clk_src.clkr.hw, 1685 }, 1686 .num_parents = 1, 1687 .flags = CLK_SET_RATE_PARENT, 1688 .ops = &clk_branch2_ops, 1689 }, 1690 }, 1691}; 1692 1693static struct clk_branch cam_cc_csiphy5_clk = { 1694 .halt_reg = 0x155f0, 1695 .halt_check = BRANCH_HALT, 1696 .clkr = { 1697 .enable_reg = 0x155f0, 1698 .enable_mask = BIT(0), 1699 .hw.init = &(const struct clk_init_data) { 1700 .name = "cam_cc_csiphy5_clk", 1701 .parent_hws = (const struct clk_hw*[]) { 1702 &cam_cc_cphy_rx_clk_src.clkr.hw, 1703 }, 1704 .num_parents = 1, 1705 .flags = CLK_SET_RATE_PARENT, 1706 .ops = &clk_branch2_ops, 1707 }, 1708 }, 1709}; 1710 1711static struct clk_branch cam_cc_icp_ahb_clk = { 1712 .halt_reg = 0x13658, 1713 .halt_check = BRANCH_HALT, 1714 .clkr = { 1715 .enable_reg = 0x13658, 1716 .enable_mask = BIT(0), 1717 .hw.init = &(const struct clk_init_data) { 1718 .name = "cam_cc_icp_ahb_clk", 1719 .parent_hws = (const struct clk_hw*[]) { 1720 &cam_cc_slow_ahb_clk_src.clkr.hw, 1721 }, 1722 .num_parents = 1, 1723 .flags = CLK_SET_RATE_PARENT, 1724 .ops = &clk_branch2_ops, 1725 }, 1726 }, 1727}; 1728 1729static struct clk_branch cam_cc_icp_clk = { 1730 .halt_reg = 0x1364c, 1731 .halt_check = BRANCH_HALT, 1732 .clkr = { 1733 .enable_reg = 0x1364c, 1734 .enable_mask = BIT(0), 1735 .hw.init = &(const struct clk_init_data) { 1736 .name = "cam_cc_icp_clk", 1737 .parent_hws = (const struct clk_hw*[]) { 1738 &cam_cc_icp_clk_src.clkr.hw, 1739 }, 1740 .num_parents = 1, 1741 .flags = CLK_SET_RATE_PARENT, 1742 .ops = &clk_branch2_ops, 1743 }, 1744 }, 1745}; 1746 1747static struct clk_branch cam_cc_ife_0_clk = { 1748 .halt_reg = 0x11144, 1749 .halt_check = BRANCH_HALT, 1750 .clkr = { 1751 .enable_reg = 0x11144, 1752 .enable_mask = BIT(0), 1753 .hw.init = &(const struct clk_init_data) { 1754 .name = "cam_cc_ife_0_clk", 1755 .parent_hws = (const struct clk_hw*[]) { 1756 &cam_cc_ife_0_clk_src.clkr.hw, 1757 }, 1758 .num_parents = 1, 1759 .flags = CLK_SET_RATE_PARENT, 1760 .ops = &clk_branch2_ops, 1761 }, 1762 }, 1763}; 1764 1765static struct clk_branch cam_cc_ife_0_dsp_clk = { 1766 .halt_reg = 0x11154, 1767 .halt_check = BRANCH_HALT, 1768 .clkr = { 1769 .enable_reg = 0x11154, 1770 .enable_mask = BIT(0), 1771 .hw.init = &(const struct clk_init_data) { 1772 .name = "cam_cc_ife_0_dsp_clk", 1773 .parent_hws = (const struct clk_hw*[]) { 1774 &cam_cc_ife_0_clk_src.clkr.hw, 1775 }, 1776 .num_parents = 1, 1777 .flags = CLK_SET_RATE_PARENT, 1778 .ops = &clk_branch2_ops, 1779 }, 1780 }, 1781}; 1782 1783static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { 1784 .halt_reg = 0x11160, 1785 .halt_check = BRANCH_HALT, 1786 .clkr = { 1787 .enable_reg = 0x11160, 1788 .enable_mask = BIT(0), 1789 .hw.init = &(const struct clk_init_data) { 1790 .name = "cam_cc_ife_0_fast_ahb_clk", 1791 .parent_hws = (const struct clk_hw*[]) { 1792 &cam_cc_fast_ahb_clk_src.clkr.hw, 1793 }, 1794 .num_parents = 1, 1795 .flags = CLK_SET_RATE_PARENT, 1796 .ops = &clk_branch2_ops, 1797 }, 1798 }, 1799}; 1800 1801static struct clk_branch cam_cc_ife_1_clk = { 1802 .halt_reg = 0x12030, 1803 .halt_check = BRANCH_HALT, 1804 .clkr = { 1805 .enable_reg = 0x12030, 1806 .enable_mask = BIT(0), 1807 .hw.init = &(const struct clk_init_data) { 1808 .name = "cam_cc_ife_1_clk", 1809 .parent_hws = (const struct clk_hw*[]) { 1810 &cam_cc_ife_1_clk_src.clkr.hw, 1811 }, 1812 .num_parents = 1, 1813 .flags = CLK_SET_RATE_PARENT, 1814 .ops = &clk_branch2_ops, 1815 }, 1816 }, 1817}; 1818 1819static struct clk_branch cam_cc_ife_1_dsp_clk = { 1820 .halt_reg = 0x12040, 1821 .halt_check = BRANCH_HALT, 1822 .clkr = { 1823 .enable_reg = 0x12040, 1824 .enable_mask = BIT(0), 1825 .hw.init = &(const struct clk_init_data) { 1826 .name = "cam_cc_ife_1_dsp_clk", 1827 .parent_hws = (const struct clk_hw*[]) { 1828 &cam_cc_ife_1_clk_src.clkr.hw, 1829 }, 1830 .num_parents = 1, 1831 .flags = CLK_SET_RATE_PARENT, 1832 .ops = &clk_branch2_ops, 1833 }, 1834 }, 1835}; 1836 1837static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { 1838 .halt_reg = 0x1204c, 1839 .halt_check = BRANCH_HALT, 1840 .clkr = { 1841 .enable_reg = 0x1204c, 1842 .enable_mask = BIT(0), 1843 .hw.init = &(const struct clk_init_data) { 1844 .name = "cam_cc_ife_1_fast_ahb_clk", 1845 .parent_hws = (const struct clk_hw*[]) { 1846 &cam_cc_fast_ahb_clk_src.clkr.hw, 1847 }, 1848 .num_parents = 1, 1849 .flags = CLK_SET_RATE_PARENT, 1850 .ops = &clk_branch2_ops, 1851 }, 1852 }, 1853}; 1854 1855static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1856 .halt_reg = 0x13278, 1857 .halt_check = BRANCH_HALT, 1858 .clkr = { 1859 .enable_reg = 0x13278, 1860 .enable_mask = BIT(0), 1861 .hw.init = &(const struct clk_init_data) { 1862 .name = "cam_cc_ife_lite_ahb_clk", 1863 .parent_hws = (const struct clk_hw*[]) { 1864 &cam_cc_slow_ahb_clk_src.clkr.hw, 1865 }, 1866 .num_parents = 1, 1867 .flags = CLK_SET_RATE_PARENT, 1868 .ops = &clk_branch2_ops, 1869 }, 1870 }, 1871}; 1872 1873static struct clk_branch cam_cc_ife_lite_clk = { 1874 .halt_reg = 0x1312c, 1875 .halt_check = BRANCH_HALT, 1876 .clkr = { 1877 .enable_reg = 0x1312c, 1878 .enable_mask = BIT(0), 1879 .hw.init = &(const struct clk_init_data) { 1880 .name = "cam_cc_ife_lite_clk", 1881 .parent_hws = (const struct clk_hw*[]) { 1882 &cam_cc_ife_lite_clk_src.clkr.hw, 1883 }, 1884 .num_parents = 1, 1885 .flags = CLK_SET_RATE_PARENT, 1886 .ops = &clk_branch2_ops, 1887 }, 1888 }, 1889}; 1890 1891static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1892 .halt_reg = 0x13274, 1893 .halt_check = BRANCH_HALT, 1894 .clkr = { 1895 .enable_reg = 0x13274, 1896 .enable_mask = BIT(0), 1897 .hw.init = &(const struct clk_init_data) { 1898 .name = "cam_cc_ife_lite_cphy_rx_clk", 1899 .parent_hws = (const struct clk_hw*[]) { 1900 &cam_cc_cphy_rx_clk_src.clkr.hw, 1901 }, 1902 .num_parents = 1, 1903 .flags = CLK_SET_RATE_PARENT, 1904 .ops = &clk_branch2_ops, 1905 }, 1906 }, 1907}; 1908 1909static struct clk_branch cam_cc_ife_lite_csid_clk = { 1910 .halt_reg = 0x13268, 1911 .halt_check = BRANCH_HALT, 1912 .clkr = { 1913 .enable_reg = 0x13268, 1914 .enable_mask = BIT(0), 1915 .hw.init = &(const struct clk_init_data) { 1916 .name = "cam_cc_ife_lite_csid_clk", 1917 .parent_hws = (const struct clk_hw*[]) { 1918 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1919 }, 1920 .num_parents = 1, 1921 .flags = CLK_SET_RATE_PARENT, 1922 .ops = &clk_branch2_ops, 1923 }, 1924 }, 1925}; 1926 1927static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1928 .halt_reg = 0x1051c, 1929 .halt_check = BRANCH_HALT, 1930 .clkr = { 1931 .enable_reg = 0x1051c, 1932 .enable_mask = BIT(0), 1933 .hw.init = &(const struct clk_init_data) { 1934 .name = "cam_cc_ipe_nps_ahb_clk", 1935 .parent_hws = (const struct clk_hw*[]) { 1936 &cam_cc_slow_ahb_clk_src.clkr.hw, 1937 }, 1938 .num_parents = 1, 1939 .flags = CLK_SET_RATE_PARENT, 1940 .ops = &clk_branch2_ops, 1941 }, 1942 }, 1943}; 1944 1945static struct clk_branch cam_cc_ipe_nps_clk = { 1946 .halt_reg = 0x104f8, 1947 .halt_check = BRANCH_HALT, 1948 .clkr = { 1949 .enable_reg = 0x104f8, 1950 .enable_mask = BIT(0), 1951 .hw.init = &(const struct clk_init_data) { 1952 .name = "cam_cc_ipe_nps_clk", 1953 .parent_hws = (const struct clk_hw*[]) { 1954 &cam_cc_ipe_nps_clk_src.clkr.hw, 1955 }, 1956 .num_parents = 1, 1957 .flags = CLK_SET_RATE_PARENT, 1958 .ops = &clk_branch2_ops, 1959 }, 1960 }, 1961}; 1962 1963static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1964 .halt_reg = 0x10520, 1965 .halt_check = BRANCH_HALT, 1966 .clkr = { 1967 .enable_reg = 0x10520, 1968 .enable_mask = BIT(0), 1969 .hw.init = &(const struct clk_init_data) { 1970 .name = "cam_cc_ipe_nps_fast_ahb_clk", 1971 .parent_hws = (const struct clk_hw*[]) { 1972 &cam_cc_fast_ahb_clk_src.clkr.hw, 1973 }, 1974 .num_parents = 1, 1975 .flags = CLK_SET_RATE_PARENT, 1976 .ops = &clk_branch2_ops, 1977 }, 1978 }, 1979}; 1980 1981static struct clk_branch cam_cc_ipe_pps_clk = { 1982 .halt_reg = 0x10508, 1983 .halt_check = BRANCH_HALT, 1984 .clkr = { 1985 .enable_reg = 0x10508, 1986 .enable_mask = BIT(0), 1987 .hw.init = &(const struct clk_init_data) { 1988 .name = "cam_cc_ipe_pps_clk", 1989 .parent_hws = (const struct clk_hw*[]) { 1990 &cam_cc_ipe_nps_clk_src.clkr.hw, 1991 }, 1992 .num_parents = 1, 1993 .flags = CLK_SET_RATE_PARENT, 1994 .ops = &clk_branch2_ops, 1995 }, 1996 }, 1997}; 1998 1999static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 2000 .halt_reg = 0x10524, 2001 .halt_check = BRANCH_HALT, 2002 .clkr = { 2003 .enable_reg = 0x10524, 2004 .enable_mask = BIT(0), 2005 .hw.init = &(const struct clk_init_data) { 2006 .name = "cam_cc_ipe_pps_fast_ahb_clk", 2007 .parent_hws = (const struct clk_hw*[]) { 2008 &cam_cc_fast_ahb_clk_src.clkr.hw, 2009 }, 2010 .num_parents = 1, 2011 .flags = CLK_SET_RATE_PARENT, 2012 .ops = &clk_branch2_ops, 2013 }, 2014 }, 2015}; 2016 2017static struct clk_branch cam_cc_jpeg_clk = { 2018 .halt_reg = 0x13508, 2019 .halt_check = BRANCH_HALT, 2020 .clkr = { 2021 .enable_reg = 0x13508, 2022 .enable_mask = BIT(0), 2023 .hw.init = &(const struct clk_init_data) { 2024 .name = "cam_cc_jpeg_clk", 2025 .parent_hws = (const struct clk_hw*[]) { 2026 &cam_cc_jpeg_clk_src.clkr.hw, 2027 }, 2028 .num_parents = 1, 2029 .flags = CLK_SET_RATE_PARENT, 2030 .ops = &clk_branch2_ops, 2031 }, 2032 }, 2033}; 2034 2035static struct clk_branch cam_cc_mclk0_clk = { 2036 .halt_reg = 0x15018, 2037 .halt_check = BRANCH_HALT, 2038 .clkr = { 2039 .enable_reg = 0x15018, 2040 .enable_mask = BIT(0), 2041 .hw.init = &(const struct clk_init_data) { 2042 .name = "cam_cc_mclk0_clk", 2043 .parent_hws = (const struct clk_hw*[]) { 2044 &cam_cc_mclk0_clk_src.clkr.hw, 2045 }, 2046 .num_parents = 1, 2047 .flags = CLK_SET_RATE_PARENT, 2048 .ops = &clk_branch2_ops, 2049 }, 2050 }, 2051}; 2052 2053static struct clk_branch cam_cc_mclk1_clk = { 2054 .halt_reg = 0x15034, 2055 .halt_check = BRANCH_HALT, 2056 .clkr = { 2057 .enable_reg = 0x15034, 2058 .enable_mask = BIT(0), 2059 .hw.init = &(const struct clk_init_data) { 2060 .name = "cam_cc_mclk1_clk", 2061 .parent_hws = (const struct clk_hw*[]) { 2062 &cam_cc_mclk1_clk_src.clkr.hw, 2063 }, 2064 .num_parents = 1, 2065 .flags = CLK_SET_RATE_PARENT, 2066 .ops = &clk_branch2_ops, 2067 }, 2068 }, 2069}; 2070 2071static struct clk_branch cam_cc_mclk2_clk = { 2072 .halt_reg = 0x15050, 2073 .halt_check = BRANCH_HALT, 2074 .clkr = { 2075 .enable_reg = 0x15050, 2076 .enable_mask = BIT(0), 2077 .hw.init = &(const struct clk_init_data) { 2078 .name = "cam_cc_mclk2_clk", 2079 .parent_hws = (const struct clk_hw*[]) { 2080 &cam_cc_mclk2_clk_src.clkr.hw, 2081 }, 2082 .num_parents = 1, 2083 .flags = CLK_SET_RATE_PARENT, 2084 .ops = &clk_branch2_ops, 2085 }, 2086 }, 2087}; 2088 2089static struct clk_branch cam_cc_mclk3_clk = { 2090 .halt_reg = 0x1506c, 2091 .halt_check = BRANCH_HALT, 2092 .clkr = { 2093 .enable_reg = 0x1506c, 2094 .enable_mask = BIT(0), 2095 .hw.init = &(const struct clk_init_data) { 2096 .name = "cam_cc_mclk3_clk", 2097 .parent_hws = (const struct clk_hw*[]) { 2098 &cam_cc_mclk3_clk_src.clkr.hw, 2099 }, 2100 .num_parents = 1, 2101 .flags = CLK_SET_RATE_PARENT, 2102 .ops = &clk_branch2_ops, 2103 }, 2104 }, 2105}; 2106 2107static struct clk_branch cam_cc_mclk4_clk = { 2108 .halt_reg = 0x15088, 2109 .halt_check = BRANCH_HALT, 2110 .clkr = { 2111 .enable_reg = 0x15088, 2112 .enable_mask = BIT(0), 2113 .hw.init = &(const struct clk_init_data) { 2114 .name = "cam_cc_mclk4_clk", 2115 .parent_hws = (const struct clk_hw*[]) { 2116 &cam_cc_mclk4_clk_src.clkr.hw, 2117 }, 2118 .num_parents = 1, 2119 .flags = CLK_SET_RATE_PARENT, 2120 .ops = &clk_branch2_ops, 2121 }, 2122 }, 2123}; 2124 2125static struct clk_branch cam_cc_mclk5_clk = { 2126 .halt_reg = 0x150a4, 2127 .halt_check = BRANCH_HALT, 2128 .clkr = { 2129 .enable_reg = 0x150a4, 2130 .enable_mask = BIT(0), 2131 .hw.init = &(const struct clk_init_data) { 2132 .name = "cam_cc_mclk5_clk", 2133 .parent_hws = (const struct clk_hw*[]) { 2134 &cam_cc_mclk5_clk_src.clkr.hw, 2135 }, 2136 .num_parents = 1, 2137 .flags = CLK_SET_RATE_PARENT, 2138 .ops = &clk_branch2_ops, 2139 }, 2140 }, 2141}; 2142 2143static struct clk_branch cam_cc_mclk6_clk = { 2144 .halt_reg = 0x150c0, 2145 .halt_check = BRANCH_HALT, 2146 .clkr = { 2147 .enable_reg = 0x150c0, 2148 .enable_mask = BIT(0), 2149 .hw.init = &(const struct clk_init_data) { 2150 .name = "cam_cc_mclk6_clk", 2151 .parent_hws = (const struct clk_hw*[]) { 2152 &cam_cc_mclk6_clk_src.clkr.hw, 2153 }, 2154 .num_parents = 1, 2155 .flags = CLK_SET_RATE_PARENT, 2156 .ops = &clk_branch2_ops, 2157 }, 2158 }, 2159}; 2160 2161static struct clk_branch cam_cc_mclk7_clk = { 2162 .halt_reg = 0x150dc, 2163 .halt_check = BRANCH_HALT, 2164 .clkr = { 2165 .enable_reg = 0x150dc, 2166 .enable_mask = BIT(0), 2167 .hw.init = &(const struct clk_init_data) { 2168 .name = "cam_cc_mclk7_clk", 2169 .parent_hws = (const struct clk_hw*[]) { 2170 &cam_cc_mclk7_clk_src.clkr.hw, 2171 }, 2172 .num_parents = 1, 2173 .flags = CLK_SET_RATE_PARENT, 2174 .ops = &clk_branch2_ops, 2175 }, 2176 }, 2177}; 2178 2179static struct clk_branch cam_cc_sfe_0_clk = { 2180 .halt_reg = 0x133c0, 2181 .halt_check = BRANCH_HALT, 2182 .clkr = { 2183 .enable_reg = 0x133c0, 2184 .enable_mask = BIT(0), 2185 .hw.init = &(const struct clk_init_data) { 2186 .name = "cam_cc_sfe_0_clk", 2187 .parent_hws = (const struct clk_hw*[]) { 2188 &cam_cc_sfe_0_clk_src.clkr.hw, 2189 }, 2190 .num_parents = 1, 2191 .flags = CLK_SET_RATE_PARENT, 2192 .ops = &clk_branch2_ops, 2193 }, 2194 }, 2195}; 2196 2197static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { 2198 .halt_reg = 0x133d8, 2199 .halt_check = BRANCH_HALT, 2200 .clkr = { 2201 .enable_reg = 0x133d8, 2202 .enable_mask = BIT(0), 2203 .hw.init = &(const struct clk_init_data) { 2204 .name = "cam_cc_sfe_0_fast_ahb_clk", 2205 .parent_hws = (const struct clk_hw*[]) { 2206 &cam_cc_fast_ahb_clk_src.clkr.hw, 2207 }, 2208 .num_parents = 1, 2209 .flags = CLK_SET_RATE_PARENT, 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213}; 2214 2215static struct gdsc cam_cc_bps_gdsc = { 2216 .gdscr = 0x10004, 2217 .en_rest_wait_val = 0x2, 2218 .en_few_wait_val = 0x2, 2219 .clk_dis_wait_val = 0xf, 2220 .pd = { 2221 .name = "cam_cc_bps_gdsc", 2222 }, 2223 .pwrsts = PWRSTS_OFF_ON, 2224 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2225}; 2226 2227static struct gdsc cam_cc_ife_0_gdsc = { 2228 .gdscr = 0x11004, 2229 .en_rest_wait_val = 0x2, 2230 .en_few_wait_val = 0x2, 2231 .clk_dis_wait_val = 0xf, 2232 .pd = { 2233 .name = "cam_cc_ife_0_gdsc", 2234 }, 2235 .pwrsts = PWRSTS_OFF_ON, 2236 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2237}; 2238 2239static struct gdsc cam_cc_ife_1_gdsc = { 2240 .gdscr = 0x12004, 2241 .en_rest_wait_val = 0x2, 2242 .en_few_wait_val = 0x2, 2243 .clk_dis_wait_val = 0xf, 2244 .pd = { 2245 .name = "cam_cc_ife_1_gdsc", 2246 }, 2247 .pwrsts = PWRSTS_OFF_ON, 2248 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2249}; 2250 2251static struct gdsc cam_cc_ipe_0_gdsc = { 2252 .gdscr = 0x103b8, 2253 .en_rest_wait_val = 0x2, 2254 .en_few_wait_val = 0x2, 2255 .clk_dis_wait_val = 0xf, 2256 .pd = { 2257 .name = "cam_cc_ipe_0_gdsc", 2258 }, 2259 .pwrsts = PWRSTS_OFF_ON, 2260 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2261}; 2262 2263static struct gdsc cam_cc_sfe_0_gdsc = { 2264 .gdscr = 0x13280, 2265 .en_rest_wait_val = 0x2, 2266 .en_few_wait_val = 0x2, 2267 .clk_dis_wait_val = 0xf, 2268 .pd = { 2269 .name = "cam_cc_sfe_0_gdsc", 2270 }, 2271 .pwrsts = PWRSTS_OFF_ON, 2272 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2273}; 2274 2275static struct gdsc cam_cc_titan_top_gdsc = { 2276 .gdscr = 0x13a6c, 2277 .en_rest_wait_val = 0x2, 2278 .en_few_wait_val = 0x2, 2279 .clk_dis_wait_val = 0xf, 2280 .pd = { 2281 .name = "cam_cc_titan_top_gdsc", 2282 }, 2283 .pwrsts = PWRSTS_OFF_ON, 2284 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2285}; 2286 2287static struct clk_regmap *cam_cc_x1e80100_clocks[] = { 2288 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 2289 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 2290 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 2291 [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, 2292 [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, 2293 [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, 2294 [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, 2295 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2296 [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2297 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2298 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2299 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2300 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2301 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2302 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2303 [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, 2304 [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, 2305 [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, 2306 [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, 2307 [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, 2308 [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, 2309 [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, 2310 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2311 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2312 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2313 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2314 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2315 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2316 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2317 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2318 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2319 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2320 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2321 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2322 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2323 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2324 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2325 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2326 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2327 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2328 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2329 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2330 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2331 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2332 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2333 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2334 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2335 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2336 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2337 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2338 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2339 [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, 2340 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 2341 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 2342 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 2343 [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, 2344 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2345 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2346 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2347 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2348 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2349 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2350 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2351 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2352 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2353 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2354 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2355 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2356 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2357 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2358 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2359 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2360 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2361 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2362 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2363 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2364 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2365 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2366 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2367 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2368 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, 2369 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, 2370 [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, 2371 [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, 2372 [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, 2373 [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, 2374 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2375 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2376 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2377 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2378 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2379 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2380 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2381 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2382 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2383 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2384 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2385 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2386 [CAM_CC_PLL8] = &cam_cc_pll8.clkr, 2387 [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, 2388 [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, 2389 [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, 2390 [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, 2391 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2392 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2393 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2394}; 2395 2396static struct gdsc *cam_cc_x1e80100_gdscs[] = { 2397 [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, 2398 [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, 2399 [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, 2400 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2401 [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc, 2402 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2403}; 2404 2405static const struct qcom_reset_map cam_cc_x1e80100_resets[] = { 2406 [CAM_CC_BPS_BCR] = { 0x10000 }, 2407 [CAM_CC_ICP_BCR] = { 0x1351c }, 2408 [CAM_CC_IFE_0_BCR] = { 0x11000 }, 2409 [CAM_CC_IFE_1_BCR] = { 0x12000 }, 2410 [CAM_CC_IPE_0_BCR] = { 0x103b4 }, 2411 [CAM_CC_SFE_0_BCR] = { 0x1327c }, 2412}; 2413 2414static const struct regmap_config cam_cc_x1e80100_regmap_config = { 2415 .reg_bits = 32, 2416 .reg_stride = 4, 2417 .val_bits = 32, 2418 .max_register = 0x1603c, 2419 .fast_io = true, 2420}; 2421 2422static const struct qcom_cc_desc cam_cc_x1e80100_desc = { 2423 .config = &cam_cc_x1e80100_regmap_config, 2424 .clks = cam_cc_x1e80100_clocks, 2425 .num_clks = ARRAY_SIZE(cam_cc_x1e80100_clocks), 2426 .resets = cam_cc_x1e80100_resets, 2427 .num_resets = ARRAY_SIZE(cam_cc_x1e80100_resets), 2428 .gdscs = cam_cc_x1e80100_gdscs, 2429 .num_gdscs = ARRAY_SIZE(cam_cc_x1e80100_gdscs), 2430}; 2431 2432static const struct of_device_id cam_cc_x1e80100_match_table[] = { 2433 { .compatible = "qcom,x1e80100-camcc" }, 2434 { } 2435}; 2436MODULE_DEVICE_TABLE(of, cam_cc_x1e80100_match_table); 2437 2438static int cam_cc_x1e80100_probe(struct platform_device *pdev) 2439{ 2440 struct regmap *regmap; 2441 int ret; 2442 2443 ret = devm_pm_runtime_enable(&pdev->dev); 2444 if (ret) 2445 return ret; 2446 2447 ret = pm_runtime_resume_and_get(&pdev->dev); 2448 if (ret) 2449 return ret; 2450 2451 regmap = qcom_cc_map(pdev, &cam_cc_x1e80100_desc); 2452 if (IS_ERR(regmap)) { 2453 pm_runtime_put(&pdev->dev); 2454 return PTR_ERR(regmap); 2455 } 2456 2457 clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 2458 clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 2459 clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 2460 clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 2461 clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); 2462 clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); 2463 clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); 2464 2465 /* Keep clocks always enabled */ 2466 qcom_branch_set_clk_en(regmap, 0x13a9c); /* CAM_CC_GDSC_CLK */ 2467 qcom_branch_set_clk_en(regmap, 0x13ab8); /* CAM_CC_SLEEP_CLK */ 2468 2469 ret = qcom_cc_really_probe(pdev, &cam_cc_x1e80100_desc, regmap); 2470 2471 pm_runtime_put(&pdev->dev); 2472 2473 return ret; 2474} 2475 2476static struct platform_driver cam_cc_x1e80100_driver = { 2477 .probe = cam_cc_x1e80100_probe, 2478 .driver = { 2479 .name = "camcc-x1e80100", 2480 .of_match_table = cam_cc_x1e80100_match_table, 2481 }, 2482}; 2483 2484module_platform_driver(cam_cc_x1e80100_driver); 2485 2486MODULE_DESCRIPTION("QTI Camera Clock Controller X1E80100 Driver"); 2487MODULE_LICENSE("GPL"); 2488