1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk-provider.h> 7#include <linux/err.h> 8#include <linux/kernel.h> 9#include <linux/module.h> 10#include <linux/of.h> 11#include <linux/platform_device.h> 12#include <linux/regmap.h> 13 14#include <dt-bindings/clock/qcom,camcc-sc7280.h> 15 16#include "clk-alpha-pll.h" 17#include "clk-branch.h" 18#include "clk-rcg.h" 19#include "common.h" 20#include "gdsc.h" 21#include "reset.h" 22 23enum { 24 P_BI_TCXO, 25 P_CAM_CC_PLL0_OUT_EVEN, 26 P_CAM_CC_PLL0_OUT_MAIN, 27 P_CAM_CC_PLL0_OUT_ODD, 28 P_CAM_CC_PLL1_OUT_EVEN, 29 P_CAM_CC_PLL2_OUT_AUX2, 30 P_CAM_CC_PLL2_OUT_EARLY, 31 P_CAM_CC_PLL3_OUT_EVEN, 32 P_CAM_CC_PLL4_OUT_EVEN, 33 P_CAM_CC_PLL5_OUT_EVEN, 34 P_CAM_CC_PLL6_OUT_EVEN, 35 P_CAM_CC_PLL6_OUT_MAIN, 36 P_CAM_CC_PLL6_OUT_ODD, 37 P_SLEEP_CLK, 38}; 39 40static struct pll_vco lucid_vco[] = { 41 { 249600000, 2000000000, 0 }, 42}; 43 44static struct pll_vco zonda_vco[] = { 45 { 595200000UL, 3600000000UL, 0 }, 46}; 47 48/* 1200MHz Configuration */ 49static const struct alpha_pll_config cam_cc_pll0_config = { 50 .l = 0x3E, 51 .alpha = 0x8000, 52 .config_ctl_val = 0x20485699, 53 .config_ctl_hi_val = 0x00002261, 54 .config_ctl_hi1_val = 0x329A299C, 55 .user_ctl_val = 0x00003101, 56 .user_ctl_hi_val = 0x00000805, 57 .user_ctl_hi1_val = 0x00000000, 58}; 59 60static struct clk_alpha_pll cam_cc_pll0 = { 61 .offset = 0x0, 62 .vco_table = lucid_vco, 63 .num_vco = ARRAY_SIZE(lucid_vco), 64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 65 .clkr = { 66 .hw.init = &(struct clk_init_data){ 67 .name = "cam_cc_pll0", 68 .parent_data = &(const struct clk_parent_data){ 69 .fw_name = "bi_tcxo", 70 }, 71 .num_parents = 1, 72 .ops = &clk_alpha_pll_lucid_ops, 73 }, 74 }, 75}; 76 77static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 78 { 0x1, 2 }, 79 { } 80}; 81 82static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 83 .offset = 0x0, 84 .post_div_shift = 8, 85 .post_div_table = post_div_table_cam_cc_pll0_out_even, 86 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 87 .width = 4, 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 89 .clkr.hw.init = &(struct clk_init_data){ 90 .name = "cam_cc_pll0_out_even", 91 .parent_hws = (const struct clk_hw*[]) { 92 &cam_cc_pll0.clkr.hw, 93 }, 94 .num_parents = 1, 95 .flags = CLK_SET_RATE_PARENT, 96 .ops = &clk_alpha_pll_postdiv_lucid_ops, 97 }, 98}; 99 100static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 101 { 0x3, 3 }, 102 { } 103}; 104 105static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 106 .offset = 0x0, 107 .post_div_shift = 12, 108 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 109 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 110 .width = 4, 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 112 .clkr.hw.init = &(struct clk_init_data){ 113 .name = "cam_cc_pll0_out_odd", 114 .parent_hws = (const struct clk_hw*[]) { 115 &cam_cc_pll0.clkr.hw, 116 }, 117 .num_parents = 1, 118 .flags = CLK_SET_RATE_PARENT, 119 .ops = &clk_alpha_pll_postdiv_lucid_ops, 120 }, 121}; 122 123/* 600MHz Configuration */ 124static const struct alpha_pll_config cam_cc_pll1_config = { 125 .l = 0x1F, 126 .alpha = 0x4000, 127 .config_ctl_val = 0x20485699, 128 .config_ctl_hi_val = 0x00002261, 129 .config_ctl_hi1_val = 0x329A299C, 130 .user_ctl_val = 0x00000101, 131 .user_ctl_hi_val = 0x00000805, 132 .user_ctl_hi1_val = 0x00000000, 133}; 134 135static struct clk_alpha_pll cam_cc_pll1 = { 136 .offset = 0x1000, 137 .vco_table = lucid_vco, 138 .num_vco = ARRAY_SIZE(lucid_vco), 139 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 140 .clkr = { 141 .hw.init = &(struct clk_init_data){ 142 .name = "cam_cc_pll1", 143 .parent_data = &(const struct clk_parent_data){ 144 .fw_name = "bi_tcxo", 145 }, 146 .num_parents = 1, 147 .ops = &clk_alpha_pll_lucid_ops, 148 }, 149 }, 150}; 151 152static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 153 { 0x1, 2 }, 154 { } 155}; 156 157static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 158 .offset = 0x1000, 159 .post_div_shift = 8, 160 .post_div_table = post_div_table_cam_cc_pll1_out_even, 161 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 162 .width = 4, 163 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 164 .clkr.hw.init = &(struct clk_init_data){ 165 .name = "cam_cc_pll1_out_even", 166 .parent_hws = (const struct clk_hw*[]) { 167 &cam_cc_pll1.clkr.hw, 168 }, 169 .num_parents = 1, 170 .flags = CLK_SET_RATE_PARENT, 171 .ops = &clk_alpha_pll_postdiv_lucid_ops, 172 }, 173}; 174 175/* 1440MHz Configuration */ 176static const struct alpha_pll_config cam_cc_pll2_config = { 177 .l = 0x4B, 178 .alpha = 0x0, 179 .config_ctl_val = 0x08200800, 180 .config_ctl_hi_val = 0x05022011, 181 .config_ctl_hi1_val = 0x08000000, 182 .user_ctl_val = 0x00000301, 183}; 184 185static struct clk_alpha_pll cam_cc_pll2 = { 186 .offset = 0x2000, 187 .vco_table = zonda_vco, 188 .num_vco = ARRAY_SIZE(zonda_vco), 189 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 190 .clkr = { 191 .hw.init = &(struct clk_init_data){ 192 .name = "cam_cc_pll2", 193 .parent_data = &(const struct clk_parent_data){ 194 .fw_name = "bi_tcxo", 195 }, 196 .num_parents = 1, 197 .ops = &clk_alpha_pll_zonda_ops, 198 }, 199 }, 200}; 201 202static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = { 203 { 0x3, 4 }, 204 { } 205}; 206 207static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { 208 .offset = 0x2000, 209 .post_div_shift = 8, 210 .post_div_table = post_div_table_cam_cc_pll2_out_aux, 211 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux), 212 .width = 2, 213 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 214 .clkr.hw.init = &(struct clk_init_data){ 215 .name = "cam_cc_pll2_out_aux", 216 .parent_hws = (const struct clk_hw*[]) { 217 &cam_cc_pll2.clkr.hw, 218 }, 219 .num_parents = 1, 220 .flags = CLK_SET_RATE_PARENT, 221 .ops = &clk_alpha_pll_postdiv_zonda_ops, 222 }, 223}; 224 225static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = { 226 { 0x3, 4 }, 227 { } 228}; 229 230static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = { 231 .offset = 0x2000, 232 .post_div_shift = 8, 233 .post_div_table = post_div_table_cam_cc_pll2_out_aux2, 234 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2), 235 .width = 2, 236 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 237 .clkr.hw.init = &(struct clk_init_data){ 238 .name = "cam_cc_pll2_out_aux2", 239 .parent_hws = (const struct clk_hw*[]) { 240 &cam_cc_pll2.clkr.hw, 241 }, 242 .num_parents = 1, 243 .flags = CLK_SET_RATE_PARENT, 244 .ops = &clk_alpha_pll_postdiv_zonda_ops, 245 }, 246}; 247 248/* 760MHz Configuration */ 249static const struct alpha_pll_config cam_cc_pll3_config = { 250 .l = 0x27, 251 .alpha = 0x9555, 252 .config_ctl_val = 0x20485699, 253 .config_ctl_hi_val = 0x00002261, 254 .config_ctl_hi1_val = 0x329A299C, 255 .user_ctl_val = 0x00000101, 256 .user_ctl_hi_val = 0x00000805, 257 .user_ctl_hi1_val = 0x00000000, 258}; 259 260static struct clk_alpha_pll cam_cc_pll3 = { 261 .offset = 0x3000, 262 .vco_table = lucid_vco, 263 .num_vco = ARRAY_SIZE(lucid_vco), 264 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 265 .clkr = { 266 .hw.init = &(struct clk_init_data){ 267 .name = "cam_cc_pll3", 268 .parent_data = &(const struct clk_parent_data){ 269 .fw_name = "bi_tcxo", 270 }, 271 .num_parents = 1, 272 .ops = &clk_alpha_pll_lucid_ops, 273 }, 274 }, 275}; 276 277static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 278 { 0x1, 2 }, 279 { } 280}; 281 282static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 283 .offset = 0x3000, 284 .post_div_shift = 8, 285 .post_div_table = post_div_table_cam_cc_pll3_out_even, 286 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 287 .width = 4, 288 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 289 .clkr.hw.init = &(struct clk_init_data){ 290 .name = "cam_cc_pll3_out_even", 291 .parent_hws = (const struct clk_hw*[]) { 292 &cam_cc_pll3.clkr.hw, 293 }, 294 .num_parents = 1, 295 .flags = CLK_SET_RATE_PARENT, 296 .ops = &clk_alpha_pll_postdiv_lucid_ops, 297 }, 298}; 299 300/* 760MHz Configuration */ 301static const struct alpha_pll_config cam_cc_pll4_config = { 302 .l = 0x27, 303 .alpha = 0x9555, 304 .config_ctl_val = 0x20485699, 305 .config_ctl_hi_val = 0x00002261, 306 .config_ctl_hi1_val = 0x329A299C, 307 .user_ctl_val = 0x00000101, 308 .user_ctl_hi_val = 0x00000805, 309 .user_ctl_hi1_val = 0x00000000, 310}; 311 312static struct clk_alpha_pll cam_cc_pll4 = { 313 .offset = 0x4000, 314 .vco_table = lucid_vco, 315 .num_vco = ARRAY_SIZE(lucid_vco), 316 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 317 .clkr = { 318 .hw.init = &(struct clk_init_data){ 319 .name = "cam_cc_pll4", 320 .parent_data = &(const struct clk_parent_data){ 321 .fw_name = "bi_tcxo", 322 }, 323 .num_parents = 1, 324 .ops = &clk_alpha_pll_lucid_ops, 325 }, 326 }, 327}; 328 329static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 330 { 0x1, 2 }, 331 { } 332}; 333 334static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 335 .offset = 0x4000, 336 .post_div_shift = 8, 337 .post_div_table = post_div_table_cam_cc_pll4_out_even, 338 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 339 .width = 4, 340 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 341 .clkr.hw.init = &(struct clk_init_data){ 342 .name = "cam_cc_pll4_out_even", 343 .parent_hws = (const struct clk_hw*[]) { 344 &cam_cc_pll4.clkr.hw, 345 }, 346 .num_parents = 1, 347 .flags = CLK_SET_RATE_PARENT, 348 .ops = &clk_alpha_pll_postdiv_lucid_ops, 349 }, 350}; 351 352/* 760MHz Configuration */ 353static const struct alpha_pll_config cam_cc_pll5_config = { 354 .l = 0x27, 355 .alpha = 0x9555, 356 .config_ctl_val = 0x20485699, 357 .config_ctl_hi_val = 0x00002261, 358 .config_ctl_hi1_val = 0x329A299C, 359 .user_ctl_val = 0x00000101, 360 .user_ctl_hi_val = 0x00000805, 361 .user_ctl_hi1_val = 0x00000000, 362}; 363 364static struct clk_alpha_pll cam_cc_pll5 = { 365 .offset = 0x5000, 366 .vco_table = lucid_vco, 367 .num_vco = ARRAY_SIZE(lucid_vco), 368 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 369 .clkr = { 370 .hw.init = &(struct clk_init_data){ 371 .name = "cam_cc_pll5", 372 .parent_data = &(const struct clk_parent_data){ 373 .fw_name = "bi_tcxo", 374 }, 375 .num_parents = 1, 376 .ops = &clk_alpha_pll_lucid_ops, 377 }, 378 }, 379}; 380 381static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 382 { 0x1, 2 }, 383 { } 384}; 385 386static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 387 .offset = 0x5000, 388 .post_div_shift = 8, 389 .post_div_table = post_div_table_cam_cc_pll5_out_even, 390 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 391 .width = 4, 392 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 393 .clkr.hw.init = &(struct clk_init_data){ 394 .name = "cam_cc_pll5_out_even", 395 .parent_hws = (const struct clk_hw*[]) { 396 &cam_cc_pll5.clkr.hw, 397 }, 398 .num_parents = 1, 399 .flags = CLK_SET_RATE_PARENT, 400 .ops = &clk_alpha_pll_postdiv_lucid_ops, 401 }, 402}; 403 404/* 960MHz Configuration */ 405static const struct alpha_pll_config cam_cc_pll6_config = { 406 .l = 0x32, 407 .alpha = 0x0, 408 .config_ctl_val = 0x20485699, 409 .config_ctl_hi_val = 0x00002261, 410 .config_ctl_hi1_val = 0x329A299C, 411 .user_ctl_val = 0x00003101, 412 .user_ctl_hi_val = 0x00000805, 413 .user_ctl_hi1_val = 0x00000000, 414}; 415 416static struct clk_alpha_pll cam_cc_pll6 = { 417 .offset = 0x6000, 418 .vco_table = lucid_vco, 419 .num_vco = ARRAY_SIZE(lucid_vco), 420 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 421 .clkr = { 422 .hw.init = &(struct clk_init_data){ 423 .name = "cam_cc_pll6", 424 .parent_data = &(const struct clk_parent_data){ 425 .fw_name = "bi_tcxo", 426 }, 427 .num_parents = 1, 428 .ops = &clk_alpha_pll_lucid_ops, 429 }, 430 }, 431}; 432 433static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 434 { 0x1, 2 }, 435 { } 436}; 437 438static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 439 .offset = 0x6000, 440 .post_div_shift = 8, 441 .post_div_table = post_div_table_cam_cc_pll6_out_even, 442 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 443 .width = 4, 444 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 445 .clkr.hw.init = &(struct clk_init_data){ 446 .name = "cam_cc_pll6_out_even", 447 .parent_hws = (const struct clk_hw*[]) { 448 &cam_cc_pll6.clkr.hw, 449 }, 450 .num_parents = 1, 451 .flags = CLK_SET_RATE_PARENT, 452 .ops = &clk_alpha_pll_postdiv_lucid_ops, 453 }, 454}; 455 456static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] = { 457 { 0x3, 3 }, 458 { } 459}; 460 461static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = { 462 .offset = 0x6000, 463 .post_div_shift = 12, 464 .post_div_table = post_div_table_cam_cc_pll6_out_odd, 465 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd), 466 .width = 4, 467 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 468 .clkr.hw.init = &(struct clk_init_data){ 469 .name = "cam_cc_pll6_out_odd", 470 .parent_hws = (const struct clk_hw*[]) { 471 &cam_cc_pll6.clkr.hw, 472 }, 473 .num_parents = 1, 474 .flags = CLK_SET_RATE_PARENT, 475 .ops = &clk_alpha_pll_postdiv_lucid_ops, 476 }, 477}; 478 479static const struct parent_map cam_cc_parent_map_0[] = { 480 { P_BI_TCXO, 0 }, 481 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 482 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 483 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 484 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 485}; 486 487static const struct clk_parent_data cam_cc_parent_data_0[] = { 488 { .fw_name = "bi_tcxo" }, 489 { .hw = &cam_cc_pll0.clkr.hw }, 490 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 491 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 492 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 493}; 494 495static const struct parent_map cam_cc_parent_map_1[] = { 496 { P_BI_TCXO, 0 }, 497 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 498 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 499 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 500 { P_CAM_CC_PLL6_OUT_MAIN, 4 }, 501 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 502}; 503 504static const struct clk_parent_data cam_cc_parent_data_1[] = { 505 { .fw_name = "bi_tcxo" }, 506 { .hw = &cam_cc_pll0.clkr.hw }, 507 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 508 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 509 { .hw = &cam_cc_pll6.clkr.hw }, 510 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 511}; 512 513static const struct parent_map cam_cc_parent_map_2[] = { 514 { P_BI_TCXO, 0 }, 515 { P_CAM_CC_PLL2_OUT_AUX2, 3 }, 516 { P_CAM_CC_PLL2_OUT_EARLY, 5 }, 517}; 518 519static const struct clk_parent_data cam_cc_parent_data_2[] = { 520 { .fw_name = "bi_tcxo" }, 521 { .hw = &cam_cc_pll2_out_aux2.clkr.hw }, 522 { .hw = &cam_cc_pll2.clkr.hw }, 523}; 524 525static const struct parent_map cam_cc_parent_map_3[] = { 526 { P_BI_TCXO, 0 }, 527 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 528 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 529 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 530 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 531 { P_CAM_CC_PLL6_OUT_ODD, 6 }, 532}; 533 534static const struct clk_parent_data cam_cc_parent_data_3[] = { 535 { .fw_name = "bi_tcxo" }, 536 { .hw = &cam_cc_pll0.clkr.hw }, 537 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 538 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 539 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 540 { .hw = &cam_cc_pll6_out_odd.clkr.hw }, 541}; 542 543static const struct parent_map cam_cc_parent_map_4[] = { 544 { P_BI_TCXO, 0 }, 545 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 546}; 547 548static const struct clk_parent_data cam_cc_parent_data_4[] = { 549 { .fw_name = "bi_tcxo" }, 550 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 551}; 552 553static const struct parent_map cam_cc_parent_map_5[] = { 554 { P_BI_TCXO, 0 }, 555 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 556}; 557 558static const struct clk_parent_data cam_cc_parent_data_5[] = { 559 { .fw_name = "bi_tcxo" }, 560 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 561}; 562 563static const struct parent_map cam_cc_parent_map_6[] = { 564 { P_BI_TCXO, 0 }, 565 { P_CAM_CC_PLL5_OUT_EVEN, 6 }, 566}; 567 568static const struct clk_parent_data cam_cc_parent_data_6[] = { 569 { .fw_name = "bi_tcxo" }, 570 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 571}; 572 573static const struct parent_map cam_cc_parent_map_7[] = { 574 { P_BI_TCXO, 0 }, 575 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 576}; 577 578static const struct clk_parent_data cam_cc_parent_data_7[] = { 579 { .fw_name = "bi_tcxo" }, 580 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 581}; 582 583static const struct parent_map cam_cc_parent_map_8[] = { 584 { P_SLEEP_CLK, 0 }, 585}; 586 587static const struct clk_parent_data cam_cc_parent_data_8[] = { 588 { .fw_name = "sleep_clk" }, 589}; 590 591static const struct parent_map cam_cc_parent_map_9[] = { 592 { P_BI_TCXO, 0 }, 593}; 594 595static const struct clk_parent_data cam_cc_parent_data_9_ao[] = { 596 { .fw_name = "bi_tcxo_ao" }, 597}; 598 599static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 600 F(19200000, P_BI_TCXO, 1, 0, 0), 601 F(100000000, P_CAM_CC_PLL0_OUT_ODD, 4, 0, 0), 602 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 603 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 604 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 605 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 606 { } 607}; 608 609static struct clk_rcg2 cam_cc_bps_clk_src = { 610 .cmd_rcgr = 0x7010, 611 .mnd_width = 0, 612 .hid_width = 5, 613 .parent_map = cam_cc_parent_map_0, 614 .freq_tbl = ftbl_cam_cc_bps_clk_src, 615 .clkr.hw.init = &(struct clk_init_data){ 616 .name = "cam_cc_bps_clk_src", 617 .parent_data = cam_cc_parent_data_0, 618 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 619 .ops = &clk_rcg2_shared_ops, 620 }, 621}; 622 623static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 624 F(19200000, P_BI_TCXO, 1, 0, 0), 625 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 626 F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0), 627 F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0), 628 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 629 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 630 { } 631}; 632 633static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 634 .cmd_rcgr = 0xc124, 635 .mnd_width = 0, 636 .hid_width = 5, 637 .parent_map = cam_cc_parent_map_3, 638 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 639 .clkr.hw.init = &(struct clk_init_data){ 640 .name = "cam_cc_camnoc_axi_clk_src", 641 .parent_data = cam_cc_parent_data_3, 642 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 643 .ops = &clk_rcg2_shared_ops, 644 }, 645}; 646 647static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 648 F(19200000, P_BI_TCXO, 1, 0, 0), 649 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 650 { } 651}; 652 653static struct clk_rcg2 cam_cc_cci_0_clk_src = { 654 .cmd_rcgr = 0xc0e0, 655 .mnd_width = 8, 656 .hid_width = 5, 657 .parent_map = cam_cc_parent_map_0, 658 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 659 .clkr.hw.init = &(struct clk_init_data){ 660 .name = "cam_cc_cci_0_clk_src", 661 .parent_data = cam_cc_parent_data_0, 662 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 663 .ops = &clk_rcg2_shared_ops, 664 }, 665}; 666 667static struct clk_rcg2 cam_cc_cci_1_clk_src = { 668 .cmd_rcgr = 0xc0fc, 669 .mnd_width = 8, 670 .hid_width = 5, 671 .parent_map = cam_cc_parent_map_0, 672 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 673 .clkr.hw.init = &(struct clk_init_data){ 674 .name = "cam_cc_cci_1_clk_src", 675 .parent_data = cam_cc_parent_data_0, 676 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 677 .ops = &clk_rcg2_shared_ops, 678 }, 679}; 680 681static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 682 F(19200000, P_BI_TCXO, 1, 0, 0), 683 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 684 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 685 { } 686}; 687 688static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 689 .cmd_rcgr = 0xa064, 690 .mnd_width = 0, 691 .hid_width = 5, 692 .parent_map = cam_cc_parent_map_1, 693 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 694 .clkr.hw.init = &(struct clk_init_data){ 695 .name = "cam_cc_cphy_rx_clk_src", 696 .parent_data = cam_cc_parent_data_1, 697 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 698 .ops = &clk_rcg2_shared_ops, 699 }, 700}; 701 702static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 703 F(19200000, P_BI_TCXO, 1, 0, 0), 704 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 705 { } 706}; 707 708static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 709 .cmd_rcgr = 0xe0ac, 710 .mnd_width = 0, 711 .hid_width = 5, 712 .parent_map = cam_cc_parent_map_0, 713 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 714 .clkr.hw.init = &(struct clk_init_data){ 715 .name = "cam_cc_csi0phytimer_clk_src", 716 .parent_data = cam_cc_parent_data_0, 717 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 718 .ops = &clk_rcg2_shared_ops, 719 }, 720}; 721 722static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 723 .cmd_rcgr = 0xe0d0, 724 .mnd_width = 0, 725 .hid_width = 5, 726 .parent_map = cam_cc_parent_map_0, 727 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 728 .clkr.hw.init = &(struct clk_init_data){ 729 .name = "cam_cc_csi1phytimer_clk_src", 730 .parent_data = cam_cc_parent_data_0, 731 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 732 .ops = &clk_rcg2_shared_ops, 733 }, 734}; 735 736static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 737 .cmd_rcgr = 0xe0f4, 738 .mnd_width = 0, 739 .hid_width = 5, 740 .parent_map = cam_cc_parent_map_0, 741 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 742 .clkr.hw.init = &(struct clk_init_data){ 743 .name = "cam_cc_csi2phytimer_clk_src", 744 .parent_data = cam_cc_parent_data_0, 745 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 746 .ops = &clk_rcg2_shared_ops, 747 }, 748}; 749 750static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 751 .cmd_rcgr = 0xe11c, 752 .mnd_width = 0, 753 .hid_width = 5, 754 .parent_map = cam_cc_parent_map_0, 755 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 756 .clkr.hw.init = &(struct clk_init_data){ 757 .name = "cam_cc_csi3phytimer_clk_src", 758 .parent_data = cam_cc_parent_data_0, 759 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 760 .ops = &clk_rcg2_shared_ops, 761 }, 762}; 763 764static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 765 .cmd_rcgr = 0xe140, 766 .mnd_width = 0, 767 .hid_width = 5, 768 .parent_map = cam_cc_parent_map_0, 769 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 770 .clkr.hw.init = &(struct clk_init_data){ 771 .name = "cam_cc_csi4phytimer_clk_src", 772 .parent_data = cam_cc_parent_data_0, 773 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 774 .ops = &clk_rcg2_shared_ops, 775 }, 776}; 777 778static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 779 F(19200000, P_BI_TCXO, 1, 0, 0), 780 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 781 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 782 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 783 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 784 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 785 { } 786}; 787 788static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 789 .cmd_rcgr = 0x703c, 790 .mnd_width = 0, 791 .hid_width = 5, 792 .parent_map = cam_cc_parent_map_0, 793 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 794 .clkr.hw.init = &(struct clk_init_data){ 795 .name = "cam_cc_fast_ahb_clk_src", 796 .parent_data = cam_cc_parent_data_0, 797 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 798 .ops = &clk_rcg2_shared_ops, 799 }, 800}; 801 802static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 803 F(19200000, P_BI_TCXO, 1, 0, 0), 804 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 805 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 806 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 807 { } 808}; 809 810static struct clk_rcg2 cam_cc_icp_clk_src = { 811 .cmd_rcgr = 0xc0b8, 812 .mnd_width = 0, 813 .hid_width = 5, 814 .parent_map = cam_cc_parent_map_0, 815 .freq_tbl = ftbl_cam_cc_icp_clk_src, 816 .clkr.hw.init = &(struct clk_init_data){ 817 .name = "cam_cc_icp_clk_src", 818 .parent_data = cam_cc_parent_data_0, 819 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 820 .ops = &clk_rcg2_shared_ops, 821 }, 822}; 823 824static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 825 F(19200000, P_BI_TCXO, 1, 0, 0), 826 F(380000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 827 F(510000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 828 F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 829 F(760000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 830 { } 831}; 832 833static struct clk_rcg2 cam_cc_ife_0_clk_src = { 834 .cmd_rcgr = 0xa010, 835 .mnd_width = 0, 836 .hid_width = 5, 837 .parent_map = cam_cc_parent_map_4, 838 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 839 .clkr.hw.init = &(struct clk_init_data){ 840 .name = "cam_cc_ife_0_clk_src", 841 .parent_data = cam_cc_parent_data_4, 842 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 843 .flags = CLK_SET_RATE_PARENT, 844 .ops = &clk_rcg2_shared_ops, 845 }, 846}; 847 848static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 849 F(19200000, P_BI_TCXO, 1, 0, 0), 850 F(380000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 851 F(510000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 852 F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 853 F(760000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 854 { } 855}; 856 857static struct clk_rcg2 cam_cc_ife_1_clk_src = { 858 .cmd_rcgr = 0xb010, 859 .mnd_width = 0, 860 .hid_width = 5, 861 .parent_map = cam_cc_parent_map_5, 862 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 863 .clkr.hw.init = &(struct clk_init_data){ 864 .name = "cam_cc_ife_1_clk_src", 865 .parent_data = cam_cc_parent_data_5, 866 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 867 .flags = CLK_SET_RATE_PARENT, 868 .ops = &clk_rcg2_shared_ops, 869 }, 870}; 871 872static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 873 F(19200000, P_BI_TCXO, 1, 0, 0), 874 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 875 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 876 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 877 { } 878}; 879 880static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 881 .cmd_rcgr = 0xa03c, 882 .mnd_width = 0, 883 .hid_width = 5, 884 .parent_map = cam_cc_parent_map_1, 885 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 886 .clkr.hw.init = &(struct clk_init_data){ 887 .name = "cam_cc_ife_0_csid_clk_src", 888 .parent_data = cam_cc_parent_data_1, 889 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 890 .ops = &clk_rcg2_shared_ops, 891 }, 892}; 893 894static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 895 .cmd_rcgr = 0xb03c, 896 .mnd_width = 0, 897 .hid_width = 5, 898 .parent_map = cam_cc_parent_map_1, 899 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 900 .clkr.hw.init = &(struct clk_init_data){ 901 .name = "cam_cc_ife_1_csid_clk_src", 902 .parent_data = cam_cc_parent_data_1, 903 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 904 .ops = &clk_rcg2_shared_ops, 905 }, 906}; 907 908static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { 909 F(19200000, P_BI_TCXO, 1, 0, 0), 910 F(380000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 911 F(510000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 912 F(637000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 913 F(760000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 914 { } 915}; 916 917static struct clk_rcg2 cam_cc_ife_2_clk_src = { 918 .cmd_rcgr = 0xb07c, 919 .mnd_width = 0, 920 .hid_width = 5, 921 .parent_map = cam_cc_parent_map_6, 922 .freq_tbl = ftbl_cam_cc_ife_2_clk_src, 923 .clkr.hw.init = &(struct clk_init_data){ 924 .name = "cam_cc_ife_2_clk_src", 925 .parent_data = cam_cc_parent_data_6, 926 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 927 .flags = CLK_SET_RATE_PARENT, 928 .ops = &clk_rcg2_shared_ops, 929 }, 930}; 931 932static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = { 933 .cmd_rcgr = 0xb0a8, 934 .mnd_width = 0, 935 .hid_width = 5, 936 .parent_map = cam_cc_parent_map_1, 937 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 938 .clkr.hw.init = &(struct clk_init_data){ 939 .name = "cam_cc_ife_2_csid_clk_src", 940 .parent_data = cam_cc_parent_data_1, 941 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 942 .ops = &clk_rcg2_shared_ops, 943 }, 944}; 945 946static const struct freq_tbl ftbl_cam_cc_ife_lite_0_clk_src[] = { 947 F(19200000, P_BI_TCXO, 1, 0, 0), 948 F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0), 949 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 950 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 951 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 952 { } 953}; 954 955static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = { 956 .cmd_rcgr = 0xc004, 957 .mnd_width = 0, 958 .hid_width = 5, 959 .parent_map = cam_cc_parent_map_3, 960 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, 961 .clkr.hw.init = &(struct clk_init_data){ 962 .name = "cam_cc_ife_lite_0_clk_src", 963 .parent_data = cam_cc_parent_data_3, 964 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 965 .ops = &clk_rcg2_shared_ops, 966 }, 967}; 968 969static struct clk_rcg2 cam_cc_ife_lite_0_csid_clk_src = { 970 .cmd_rcgr = 0xc020, 971 .mnd_width = 0, 972 .hid_width = 5, 973 .parent_map = cam_cc_parent_map_1, 974 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 975 .clkr.hw.init = &(struct clk_init_data){ 976 .name = "cam_cc_ife_lite_0_csid_clk_src", 977 .parent_data = cam_cc_parent_data_1, 978 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 979 .ops = &clk_rcg2_shared_ops, 980 }, 981}; 982 983static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = { 984 .cmd_rcgr = 0xc048, 985 .mnd_width = 0, 986 .hid_width = 5, 987 .parent_map = cam_cc_parent_map_3, 988 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, 989 .clkr.hw.init = &(struct clk_init_data){ 990 .name = "cam_cc_ife_lite_1_clk_src", 991 .parent_data = cam_cc_parent_data_3, 992 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 993 .ops = &clk_rcg2_shared_ops, 994 }, 995}; 996 997static struct clk_rcg2 cam_cc_ife_lite_1_csid_clk_src = { 998 .cmd_rcgr = 0xc064, 999 .mnd_width = 0, 1000 .hid_width = 5, 1001 .parent_map = cam_cc_parent_map_1, 1002 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 1003 .clkr.hw.init = &(struct clk_init_data){ 1004 .name = "cam_cc_ife_lite_1_csid_clk_src", 1005 .parent_data = cam_cc_parent_data_1, 1006 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1007 .ops = &clk_rcg2_shared_ops, 1008 }, 1009}; 1010 1011static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 1012 F(19200000, P_BI_TCXO, 1, 0, 0), 1013 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 1014 F(430000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 1015 F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 1016 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 1017 { } 1018}; 1019 1020static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 1021 .cmd_rcgr = 0x8010, 1022 .mnd_width = 0, 1023 .hid_width = 5, 1024 .parent_map = cam_cc_parent_map_7, 1025 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 1026 .clkr.hw.init = &(struct clk_init_data){ 1027 .name = "cam_cc_ipe_0_clk_src", 1028 .parent_data = cam_cc_parent_data_7, 1029 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 1030 .flags = CLK_SET_RATE_PARENT, 1031 .ops = &clk_rcg2_shared_ops, 1032 }, 1033}; 1034 1035static struct clk_rcg2 cam_cc_jpeg_clk_src = { 1036 .cmd_rcgr = 0xc08c, 1037 .mnd_width = 0, 1038 .hid_width = 5, 1039 .parent_map = cam_cc_parent_map_0, 1040 .freq_tbl = ftbl_cam_cc_bps_clk_src, 1041 .clkr.hw.init = &(struct clk_init_data){ 1042 .name = "cam_cc_jpeg_clk_src", 1043 .parent_data = cam_cc_parent_data_0, 1044 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1045 .ops = &clk_rcg2_shared_ops, 1046 }, 1047}; 1048 1049static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 1050 F(19200000, P_BI_TCXO, 1, 0, 0), 1051 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 1052 F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0), 1053 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 1054 F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0), 1055 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 1056 { } 1057}; 1058 1059static struct clk_rcg2 cam_cc_lrme_clk_src = { 1060 .cmd_rcgr = 0xc150, 1061 .mnd_width = 0, 1062 .hid_width = 5, 1063 .parent_map = cam_cc_parent_map_3, 1064 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 1065 .clkr.hw.init = &(struct clk_init_data){ 1066 .name = "cam_cc_lrme_clk_src", 1067 .parent_data = cam_cc_parent_data_3, 1068 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 1069 .ops = &clk_rcg2_shared_ops, 1070 }, 1071}; 1072 1073static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 1074 F(19200000, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 75), 1075 F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6), 1076 F(34285714, P_CAM_CC_PLL2_OUT_EARLY, 2, 1, 21), 1077 { } 1078}; 1079 1080static struct clk_rcg2 cam_cc_mclk0_clk_src = { 1081 .cmd_rcgr = 0xe000, 1082 .mnd_width = 8, 1083 .hid_width = 5, 1084 .parent_map = cam_cc_parent_map_2, 1085 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1086 .clkr.hw.init = &(struct clk_init_data){ 1087 .name = "cam_cc_mclk0_clk_src", 1088 .parent_data = cam_cc_parent_data_2, 1089 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 1090 .ops = &clk_rcg2_shared_ops, 1091 }, 1092}; 1093 1094static struct clk_rcg2 cam_cc_mclk1_clk_src = { 1095 .cmd_rcgr = 0xe01c, 1096 .mnd_width = 8, 1097 .hid_width = 5, 1098 .parent_map = cam_cc_parent_map_2, 1099 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1100 .clkr.hw.init = &(struct clk_init_data){ 1101 .name = "cam_cc_mclk1_clk_src", 1102 .parent_data = cam_cc_parent_data_2, 1103 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 1104 .ops = &clk_rcg2_shared_ops, 1105 }, 1106}; 1107 1108static struct clk_rcg2 cam_cc_mclk2_clk_src = { 1109 .cmd_rcgr = 0xe038, 1110 .mnd_width = 8, 1111 .hid_width = 5, 1112 .parent_map = cam_cc_parent_map_2, 1113 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1114 .clkr.hw.init = &(struct clk_init_data){ 1115 .name = "cam_cc_mclk2_clk_src", 1116 .parent_data = cam_cc_parent_data_2, 1117 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 1118 .ops = &clk_rcg2_shared_ops, 1119 }, 1120}; 1121 1122static struct clk_rcg2 cam_cc_mclk3_clk_src = { 1123 .cmd_rcgr = 0xe054, 1124 .mnd_width = 8, 1125 .hid_width = 5, 1126 .parent_map = cam_cc_parent_map_2, 1127 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1128 .clkr.hw.init = &(struct clk_init_data){ 1129 .name = "cam_cc_mclk3_clk_src", 1130 .parent_data = cam_cc_parent_data_2, 1131 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 1132 .ops = &clk_rcg2_shared_ops, 1133 }, 1134}; 1135 1136static struct clk_rcg2 cam_cc_mclk4_clk_src = { 1137 .cmd_rcgr = 0xe070, 1138 .mnd_width = 8, 1139 .hid_width = 5, 1140 .parent_map = cam_cc_parent_map_2, 1141 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1142 .clkr.hw.init = &(struct clk_init_data){ 1143 .name = "cam_cc_mclk4_clk_src", 1144 .parent_data = cam_cc_parent_data_2, 1145 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 1146 .ops = &clk_rcg2_shared_ops, 1147 }, 1148}; 1149 1150static struct clk_rcg2 cam_cc_mclk5_clk_src = { 1151 .cmd_rcgr = 0xe08c, 1152 .mnd_width = 8, 1153 .hid_width = 5, 1154 .parent_map = cam_cc_parent_map_2, 1155 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1156 .clkr.hw.init = &(struct clk_init_data){ 1157 .name = "cam_cc_mclk5_clk_src", 1158 .parent_data = cam_cc_parent_data_2, 1159 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 1160 .ops = &clk_rcg2_shared_ops, 1161 }, 1162}; 1163 1164static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 1165 F(32000, P_SLEEP_CLK, 1, 0, 0), 1166 { } 1167}; 1168 1169static struct clk_rcg2 cam_cc_sleep_clk_src = { 1170 .cmd_rcgr = 0xc1c0, 1171 .mnd_width = 0, 1172 .hid_width = 5, 1173 .parent_map = cam_cc_parent_map_8, 1174 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 1175 .clkr.hw.init = &(struct clk_init_data){ 1176 .name = "cam_cc_sleep_clk_src", 1177 .parent_data = cam_cc_parent_data_8, 1178 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), 1179 .ops = &clk_rcg2_ops, 1180 }, 1181}; 1182 1183static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 1184 F(19200000, P_BI_TCXO, 1, 0, 0), 1185 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 1186 { } 1187}; 1188 1189static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 1190 .cmd_rcgr = 0x7058, 1191 .mnd_width = 8, 1192 .hid_width = 5, 1193 .parent_map = cam_cc_parent_map_0, 1194 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 1195 .clkr.hw.init = &(struct clk_init_data){ 1196 .name = "cam_cc_slow_ahb_clk_src", 1197 .parent_data = cam_cc_parent_data_0, 1198 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1199 .ops = &clk_rcg2_shared_ops, 1200 }, 1201}; 1202 1203static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1204 F(19200000, P_BI_TCXO, 1, 0, 0), 1205 { } 1206}; 1207 1208static struct clk_rcg2 cam_cc_xo_clk_src = { 1209 .cmd_rcgr = 0xc1a4, 1210 .mnd_width = 0, 1211 .hid_width = 5, 1212 .parent_map = cam_cc_parent_map_9, 1213 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1214 .clkr.hw.init = &(struct clk_init_data){ 1215 .name = "cam_cc_xo_clk_src", 1216 .parent_data = cam_cc_parent_data_9_ao, 1217 .num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao), 1218 .ops = &clk_rcg2_ops, 1219 }, 1220}; 1221 1222static struct clk_branch cam_cc_bps_ahb_clk = { 1223 .halt_reg = 0x7070, 1224 .halt_check = BRANCH_HALT, 1225 .clkr = { 1226 .enable_reg = 0x7070, 1227 .enable_mask = BIT(0), 1228 .hw.init = &(struct clk_init_data){ 1229 .name = "cam_cc_bps_ahb_clk", 1230 .parent_hws = (const struct clk_hw*[]) { 1231 &cam_cc_slow_ahb_clk_src.clkr.hw, 1232 }, 1233 .num_parents = 1, 1234 .flags = CLK_SET_RATE_PARENT, 1235 .ops = &clk_branch2_ops, 1236 }, 1237 }, 1238}; 1239 1240static struct clk_branch cam_cc_bps_areg_clk = { 1241 .halt_reg = 0x7054, 1242 .halt_check = BRANCH_HALT, 1243 .clkr = { 1244 .enable_reg = 0x7054, 1245 .enable_mask = BIT(0), 1246 .hw.init = &(struct clk_init_data){ 1247 .name = "cam_cc_bps_areg_clk", 1248 .parent_hws = (const struct clk_hw*[]) { 1249 &cam_cc_fast_ahb_clk_src.clkr.hw, 1250 }, 1251 .num_parents = 1, 1252 .flags = CLK_SET_RATE_PARENT, 1253 .ops = &clk_branch2_ops, 1254 }, 1255 }, 1256}; 1257 1258static struct clk_branch cam_cc_bps_axi_clk = { 1259 .halt_reg = 0x7038, 1260 .halt_check = BRANCH_HALT, 1261 .clkr = { 1262 .enable_reg = 0x7038, 1263 .enable_mask = BIT(0), 1264 .hw.init = &(struct clk_init_data){ 1265 .name = "cam_cc_bps_axi_clk", 1266 .parent_hws = (const struct clk_hw*[]) { 1267 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1268 }, 1269 .num_parents = 1, 1270 .flags = CLK_SET_RATE_PARENT, 1271 .ops = &clk_branch2_ops, 1272 }, 1273 }, 1274}; 1275 1276static struct clk_branch cam_cc_bps_clk = { 1277 .halt_reg = 0x7028, 1278 .halt_check = BRANCH_HALT, 1279 .clkr = { 1280 .enable_reg = 0x7028, 1281 .enable_mask = BIT(0), 1282 .hw.init = &(struct clk_init_data){ 1283 .name = "cam_cc_bps_clk", 1284 .parent_hws = (const struct clk_hw*[]) { 1285 &cam_cc_bps_clk_src.clkr.hw, 1286 }, 1287 .num_parents = 1, 1288 .flags = CLK_SET_RATE_PARENT, 1289 .ops = &clk_branch2_ops, 1290 }, 1291 }, 1292}; 1293 1294static struct clk_branch cam_cc_camnoc_axi_clk = { 1295 .halt_reg = 0xc140, 1296 .halt_check = BRANCH_HALT, 1297 .clkr = { 1298 .enable_reg = 0xc140, 1299 .enable_mask = BIT(0), 1300 .hw.init = &(struct clk_init_data){ 1301 .name = "cam_cc_camnoc_axi_clk", 1302 .parent_hws = (const struct clk_hw*[]) { 1303 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1304 }, 1305 .num_parents = 1, 1306 .flags = CLK_SET_RATE_PARENT, 1307 .ops = &clk_branch2_ops, 1308 }, 1309 }, 1310}; 1311 1312static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1313 .halt_reg = 0xc148, 1314 .halt_check = BRANCH_HALT, 1315 .clkr = { 1316 .enable_reg = 0xc148, 1317 .enable_mask = BIT(0), 1318 .hw.init = &(struct clk_init_data){ 1319 .name = "cam_cc_camnoc_dcd_xo_clk", 1320 .parent_hws = (const struct clk_hw*[]) { 1321 &cam_cc_xo_clk_src.clkr.hw, 1322 }, 1323 .num_parents = 1, 1324 .flags = CLK_SET_RATE_PARENT, 1325 .ops = &clk_branch2_ops, 1326 }, 1327 }, 1328}; 1329 1330static struct clk_branch cam_cc_cci_0_clk = { 1331 .halt_reg = 0xc0f8, 1332 .halt_check = BRANCH_HALT, 1333 .clkr = { 1334 .enable_reg = 0xc0f8, 1335 .enable_mask = BIT(0), 1336 .hw.init = &(struct clk_init_data){ 1337 .name = "cam_cc_cci_0_clk", 1338 .parent_hws = (const struct clk_hw*[]) { 1339 &cam_cc_cci_0_clk_src.clkr.hw, 1340 }, 1341 .num_parents = 1, 1342 .flags = CLK_SET_RATE_PARENT, 1343 .ops = &clk_branch2_ops, 1344 }, 1345 }, 1346}; 1347 1348static struct clk_branch cam_cc_cci_1_clk = { 1349 .halt_reg = 0xc114, 1350 .halt_check = BRANCH_HALT, 1351 .clkr = { 1352 .enable_reg = 0xc114, 1353 .enable_mask = BIT(0), 1354 .hw.init = &(struct clk_init_data){ 1355 .name = "cam_cc_cci_1_clk", 1356 .parent_hws = (const struct clk_hw*[]) { 1357 &cam_cc_cci_1_clk_src.clkr.hw, 1358 }, 1359 .num_parents = 1, 1360 .flags = CLK_SET_RATE_PARENT, 1361 .ops = &clk_branch2_ops, 1362 }, 1363 }, 1364}; 1365 1366static struct clk_branch cam_cc_core_ahb_clk = { 1367 .halt_reg = 0xc1a0, 1368 .halt_check = BRANCH_HALT_DELAY, 1369 .clkr = { 1370 .enable_reg = 0xc1a0, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(struct clk_init_data){ 1373 .name = "cam_cc_core_ahb_clk", 1374 .parent_hws = (const struct clk_hw*[]) { 1375 &cam_cc_slow_ahb_clk_src.clkr.hw, 1376 }, 1377 .num_parents = 1, 1378 .flags = CLK_SET_RATE_PARENT, 1379 .ops = &clk_branch2_ops, 1380 }, 1381 }, 1382}; 1383 1384static struct clk_branch cam_cc_cpas_ahb_clk = { 1385 .halt_reg = 0xc11c, 1386 .halt_check = BRANCH_HALT, 1387 .clkr = { 1388 .enable_reg = 0xc11c, 1389 .enable_mask = BIT(0), 1390 .hw.init = &(struct clk_init_data){ 1391 .name = "cam_cc_cpas_ahb_clk", 1392 .parent_hws = (const struct clk_hw*[]) { 1393 &cam_cc_slow_ahb_clk_src.clkr.hw, 1394 }, 1395 .num_parents = 1, 1396 .flags = CLK_SET_RATE_PARENT, 1397 .ops = &clk_branch2_ops, 1398 }, 1399 }, 1400}; 1401 1402static struct clk_branch cam_cc_csi0phytimer_clk = { 1403 .halt_reg = 0xe0c4, 1404 .halt_check = BRANCH_HALT, 1405 .clkr = { 1406 .enable_reg = 0xe0c4, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "cam_cc_csi0phytimer_clk", 1410 .parent_hws = (const struct clk_hw*[]) { 1411 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1412 }, 1413 .num_parents = 1, 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418}; 1419 1420static struct clk_branch cam_cc_csi1phytimer_clk = { 1421 .halt_reg = 0xe0e8, 1422 .halt_check = BRANCH_HALT, 1423 .clkr = { 1424 .enable_reg = 0xe0e8, 1425 .enable_mask = BIT(0), 1426 .hw.init = &(struct clk_init_data){ 1427 .name = "cam_cc_csi1phytimer_clk", 1428 .parent_hws = (const struct clk_hw*[]) { 1429 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1430 }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT, 1433 .ops = &clk_branch2_ops, 1434 }, 1435 }, 1436}; 1437 1438static struct clk_branch cam_cc_csi2phytimer_clk = { 1439 .halt_reg = 0xe10c, 1440 .halt_check = BRANCH_HALT, 1441 .clkr = { 1442 .enable_reg = 0xe10c, 1443 .enable_mask = BIT(0), 1444 .hw.init = &(struct clk_init_data){ 1445 .name = "cam_cc_csi2phytimer_clk", 1446 .parent_hws = (const struct clk_hw*[]) { 1447 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1448 }, 1449 .num_parents = 1, 1450 .flags = CLK_SET_RATE_PARENT, 1451 .ops = &clk_branch2_ops, 1452 }, 1453 }, 1454}; 1455 1456static struct clk_branch cam_cc_csi3phytimer_clk = { 1457 .halt_reg = 0xe134, 1458 .halt_check = BRANCH_HALT, 1459 .clkr = { 1460 .enable_reg = 0xe134, 1461 .enable_mask = BIT(0), 1462 .hw.init = &(struct clk_init_data){ 1463 .name = "cam_cc_csi3phytimer_clk", 1464 .parent_hws = (const struct clk_hw*[]) { 1465 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1466 }, 1467 .num_parents = 1, 1468 .flags = CLK_SET_RATE_PARENT, 1469 .ops = &clk_branch2_ops, 1470 }, 1471 }, 1472}; 1473 1474static struct clk_branch cam_cc_csi4phytimer_clk = { 1475 .halt_reg = 0xe158, 1476 .halt_check = BRANCH_HALT, 1477 .clkr = { 1478 .enable_reg = 0xe158, 1479 .enable_mask = BIT(0), 1480 .hw.init = &(struct clk_init_data){ 1481 .name = "cam_cc_csi4phytimer_clk", 1482 .parent_hws = (const struct clk_hw*[]) { 1483 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1484 }, 1485 .num_parents = 1, 1486 .flags = CLK_SET_RATE_PARENT, 1487 .ops = &clk_branch2_ops, 1488 }, 1489 }, 1490}; 1491 1492static struct clk_branch cam_cc_csiphy0_clk = { 1493 .halt_reg = 0xe0c8, 1494 .halt_check = BRANCH_HALT, 1495 .clkr = { 1496 .enable_reg = 0xe0c8, 1497 .enable_mask = BIT(0), 1498 .hw.init = &(struct clk_init_data){ 1499 .name = "cam_cc_csiphy0_clk", 1500 .parent_hws = (const struct clk_hw*[]) { 1501 &cam_cc_cphy_rx_clk_src.clkr.hw, 1502 }, 1503 .num_parents = 1, 1504 .flags = CLK_SET_RATE_PARENT, 1505 .ops = &clk_branch2_ops, 1506 }, 1507 }, 1508}; 1509 1510static struct clk_branch cam_cc_csiphy1_clk = { 1511 .halt_reg = 0xe0ec, 1512 .halt_check = BRANCH_HALT, 1513 .clkr = { 1514 .enable_reg = 0xe0ec, 1515 .enable_mask = BIT(0), 1516 .hw.init = &(struct clk_init_data){ 1517 .name = "cam_cc_csiphy1_clk", 1518 .parent_hws = (const struct clk_hw*[]) { 1519 &cam_cc_cphy_rx_clk_src.clkr.hw, 1520 }, 1521 .num_parents = 1, 1522 .flags = CLK_SET_RATE_PARENT, 1523 .ops = &clk_branch2_ops, 1524 }, 1525 }, 1526}; 1527 1528static struct clk_branch cam_cc_csiphy2_clk = { 1529 .halt_reg = 0xe110, 1530 .halt_check = BRANCH_HALT, 1531 .clkr = { 1532 .enable_reg = 0xe110, 1533 .enable_mask = BIT(0), 1534 .hw.init = &(struct clk_init_data){ 1535 .name = "cam_cc_csiphy2_clk", 1536 .parent_hws = (const struct clk_hw*[]) { 1537 &cam_cc_cphy_rx_clk_src.clkr.hw, 1538 }, 1539 .num_parents = 1, 1540 .flags = CLK_SET_RATE_PARENT, 1541 .ops = &clk_branch2_ops, 1542 }, 1543 }, 1544}; 1545 1546static struct clk_branch cam_cc_csiphy3_clk = { 1547 .halt_reg = 0xe138, 1548 .halt_check = BRANCH_HALT, 1549 .clkr = { 1550 .enable_reg = 0xe138, 1551 .enable_mask = BIT(0), 1552 .hw.init = &(struct clk_init_data){ 1553 .name = "cam_cc_csiphy3_clk", 1554 .parent_hws = (const struct clk_hw*[]) { 1555 &cam_cc_cphy_rx_clk_src.clkr.hw, 1556 }, 1557 .num_parents = 1, 1558 .flags = CLK_SET_RATE_PARENT, 1559 .ops = &clk_branch2_ops, 1560 }, 1561 }, 1562}; 1563 1564static struct clk_branch cam_cc_csiphy4_clk = { 1565 .halt_reg = 0xe15c, 1566 .halt_check = BRANCH_HALT, 1567 .clkr = { 1568 .enable_reg = 0xe15c, 1569 .enable_mask = BIT(0), 1570 .hw.init = &(struct clk_init_data){ 1571 .name = "cam_cc_csiphy4_clk", 1572 .parent_hws = (const struct clk_hw*[]) { 1573 &cam_cc_cphy_rx_clk_src.clkr.hw, 1574 }, 1575 .num_parents = 1, 1576 .flags = CLK_SET_RATE_PARENT, 1577 .ops = &clk_branch2_ops, 1578 }, 1579 }, 1580}; 1581 1582static struct clk_branch cam_cc_gdsc_clk = { 1583 .halt_reg = 0xc1bc, 1584 .halt_check = BRANCH_HALT, 1585 .clkr = { 1586 .enable_reg = 0xc1bc, 1587 .enable_mask = BIT(0), 1588 .hw.init = &(struct clk_init_data){ 1589 .name = "cam_cc_gdsc_clk", 1590 .parent_hws = (const struct clk_hw*[]) { 1591 &cam_cc_xo_clk_src.clkr.hw, 1592 }, 1593 .num_parents = 1, 1594 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1595 .ops = &clk_branch2_ops, 1596 }, 1597 }, 1598}; 1599 1600static struct clk_branch cam_cc_icp_ahb_clk = { 1601 .halt_reg = 0xc0d8, 1602 .halt_check = BRANCH_HALT, 1603 .clkr = { 1604 .enable_reg = 0xc0d8, 1605 .enable_mask = BIT(0), 1606 .hw.init = &(struct clk_init_data){ 1607 .name = "cam_cc_icp_ahb_clk", 1608 .parent_hws = (const struct clk_hw*[]) { 1609 &cam_cc_slow_ahb_clk_src.clkr.hw, 1610 }, 1611 .num_parents = 1, 1612 .flags = CLK_SET_RATE_PARENT, 1613 .ops = &clk_branch2_ops, 1614 }, 1615 }, 1616}; 1617 1618static struct clk_branch cam_cc_icp_clk = { 1619 .halt_reg = 0xc0d0, 1620 .halt_check = BRANCH_HALT, 1621 .clkr = { 1622 .enable_reg = 0xc0d0, 1623 .enable_mask = BIT(0), 1624 .hw.init = &(struct clk_init_data){ 1625 .name = "cam_cc_icp_clk", 1626 .parent_hws = (const struct clk_hw*[]) { 1627 &cam_cc_icp_clk_src.clkr.hw, 1628 }, 1629 .num_parents = 1, 1630 .flags = CLK_SET_RATE_PARENT, 1631 .ops = &clk_branch2_ops, 1632 }, 1633 }, 1634}; 1635 1636static struct clk_branch cam_cc_ife_0_axi_clk = { 1637 .halt_reg = 0xa080, 1638 .halt_check = BRANCH_HALT, 1639 .clkr = { 1640 .enable_reg = 0xa080, 1641 .enable_mask = BIT(0), 1642 .hw.init = &(struct clk_init_data){ 1643 .name = "cam_cc_ife_0_axi_clk", 1644 .parent_hws = (const struct clk_hw*[]) { 1645 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1646 }, 1647 .num_parents = 1, 1648 .flags = CLK_SET_RATE_PARENT, 1649 .ops = &clk_branch2_ops, 1650 }, 1651 }, 1652}; 1653 1654static struct clk_branch cam_cc_ife_0_clk = { 1655 .halt_reg = 0xa028, 1656 .halt_check = BRANCH_HALT, 1657 .clkr = { 1658 .enable_reg = 0xa028, 1659 .enable_mask = BIT(0), 1660 .hw.init = &(struct clk_init_data){ 1661 .name = "cam_cc_ife_0_clk", 1662 .parent_hws = (const struct clk_hw*[]) { 1663 &cam_cc_ife_0_clk_src.clkr.hw, 1664 }, 1665 .num_parents = 1, 1666 .flags = CLK_SET_RATE_PARENT, 1667 .ops = &clk_branch2_ops, 1668 }, 1669 }, 1670}; 1671 1672static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1673 .halt_reg = 0xa07c, 1674 .halt_check = BRANCH_HALT, 1675 .clkr = { 1676 .enable_reg = 0xa07c, 1677 .enable_mask = BIT(0), 1678 .hw.init = &(struct clk_init_data){ 1679 .name = "cam_cc_ife_0_cphy_rx_clk", 1680 .parent_hws = (const struct clk_hw*[]) { 1681 &cam_cc_cphy_rx_clk_src.clkr.hw, 1682 }, 1683 .num_parents = 1, 1684 .flags = CLK_SET_RATE_PARENT, 1685 .ops = &clk_branch2_ops, 1686 }, 1687 }, 1688}; 1689 1690static struct clk_branch cam_cc_ife_0_csid_clk = { 1691 .halt_reg = 0xa054, 1692 .halt_check = BRANCH_HALT, 1693 .clkr = { 1694 .enable_reg = 0xa054, 1695 .enable_mask = BIT(0), 1696 .hw.init = &(struct clk_init_data){ 1697 .name = "cam_cc_ife_0_csid_clk", 1698 .parent_hws = (const struct clk_hw*[]) { 1699 &cam_cc_ife_0_csid_clk_src.clkr.hw, 1700 }, 1701 .num_parents = 1, 1702 .flags = CLK_SET_RATE_PARENT, 1703 .ops = &clk_branch2_ops, 1704 }, 1705 }, 1706}; 1707 1708static struct clk_branch cam_cc_ife_0_dsp_clk = { 1709 .halt_reg = 0xa038, 1710 .halt_check = BRANCH_HALT, 1711 .clkr = { 1712 .enable_reg = 0xa038, 1713 .enable_mask = BIT(0), 1714 .hw.init = &(struct clk_init_data){ 1715 .name = "cam_cc_ife_0_dsp_clk", 1716 .parent_hws = (const struct clk_hw*[]) { 1717 &cam_cc_ife_0_clk_src.clkr.hw, 1718 }, 1719 .num_parents = 1, 1720 .flags = CLK_SET_RATE_PARENT, 1721 .ops = &clk_branch2_ops, 1722 }, 1723 }, 1724}; 1725 1726static struct clk_branch cam_cc_ife_1_axi_clk = { 1727 .halt_reg = 0xb068, 1728 .halt_check = BRANCH_HALT, 1729 .clkr = { 1730 .enable_reg = 0xb068, 1731 .enable_mask = BIT(0), 1732 .hw.init = &(struct clk_init_data){ 1733 .name = "cam_cc_ife_1_axi_clk", 1734 .parent_hws = (const struct clk_hw*[]) { 1735 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1736 }, 1737 .num_parents = 1, 1738 .flags = CLK_SET_RATE_PARENT, 1739 .ops = &clk_branch2_ops, 1740 }, 1741 }, 1742}; 1743 1744static struct clk_branch cam_cc_ife_1_clk = { 1745 .halt_reg = 0xb028, 1746 .halt_check = BRANCH_HALT, 1747 .clkr = { 1748 .enable_reg = 0xb028, 1749 .enable_mask = BIT(0), 1750 .hw.init = &(struct clk_init_data){ 1751 .name = "cam_cc_ife_1_clk", 1752 .parent_hws = (const struct clk_hw*[]) { 1753 &cam_cc_ife_1_clk_src.clkr.hw, 1754 }, 1755 .num_parents = 1, 1756 .flags = CLK_SET_RATE_PARENT, 1757 .ops = &clk_branch2_ops, 1758 }, 1759 }, 1760}; 1761 1762static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1763 .halt_reg = 0xb064, 1764 .halt_check = BRANCH_HALT, 1765 .clkr = { 1766 .enable_reg = 0xb064, 1767 .enable_mask = BIT(0), 1768 .hw.init = &(struct clk_init_data){ 1769 .name = "cam_cc_ife_1_cphy_rx_clk", 1770 .parent_hws = (const struct clk_hw*[]) { 1771 &cam_cc_cphy_rx_clk_src.clkr.hw, 1772 }, 1773 .num_parents = 1, 1774 .flags = CLK_SET_RATE_PARENT, 1775 .ops = &clk_branch2_ops, 1776 }, 1777 }, 1778}; 1779 1780static struct clk_branch cam_cc_ife_1_csid_clk = { 1781 .halt_reg = 0xb054, 1782 .halt_check = BRANCH_HALT, 1783 .clkr = { 1784 .enable_reg = 0xb054, 1785 .enable_mask = BIT(0), 1786 .hw.init = &(struct clk_init_data){ 1787 .name = "cam_cc_ife_1_csid_clk", 1788 .parent_hws = (const struct clk_hw*[]) { 1789 &cam_cc_ife_1_csid_clk_src.clkr.hw, 1790 }, 1791 .num_parents = 1, 1792 .flags = CLK_SET_RATE_PARENT, 1793 .ops = &clk_branch2_ops, 1794 }, 1795 }, 1796}; 1797 1798static struct clk_branch cam_cc_ife_1_dsp_clk = { 1799 .halt_reg = 0xb038, 1800 .halt_check = BRANCH_HALT, 1801 .clkr = { 1802 .enable_reg = 0xb038, 1803 .enable_mask = BIT(0), 1804 .hw.init = &(struct clk_init_data){ 1805 .name = "cam_cc_ife_1_dsp_clk", 1806 .parent_hws = (const struct clk_hw*[]) { 1807 &cam_cc_ife_1_clk_src.clkr.hw, 1808 }, 1809 .num_parents = 1, 1810 .flags = CLK_SET_RATE_PARENT, 1811 .ops = &clk_branch2_ops, 1812 }, 1813 }, 1814}; 1815 1816static struct clk_branch cam_cc_ife_2_axi_clk = { 1817 .halt_reg = 0xb0d4, 1818 .halt_check = BRANCH_HALT, 1819 .clkr = { 1820 .enable_reg = 0xb0d4, 1821 .enable_mask = BIT(0), 1822 .hw.init = &(struct clk_init_data){ 1823 .name = "cam_cc_ife_2_axi_clk", 1824 .parent_hws = (const struct clk_hw*[]) { 1825 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1826 }, 1827 .num_parents = 1, 1828 .flags = CLK_SET_RATE_PARENT, 1829 .ops = &clk_branch2_ops, 1830 }, 1831 }, 1832}; 1833 1834static struct clk_branch cam_cc_ife_2_clk = { 1835 .halt_reg = 0xb094, 1836 .halt_check = BRANCH_HALT, 1837 .clkr = { 1838 .enable_reg = 0xb094, 1839 .enable_mask = BIT(0), 1840 .hw.init = &(struct clk_init_data){ 1841 .name = "cam_cc_ife_2_clk", 1842 .parent_hws = (const struct clk_hw*[]) { 1843 &cam_cc_ife_2_clk_src.clkr.hw, 1844 }, 1845 .num_parents = 1, 1846 .flags = CLK_SET_RATE_PARENT, 1847 .ops = &clk_branch2_ops, 1848 }, 1849 }, 1850}; 1851 1852static struct clk_branch cam_cc_ife_2_cphy_rx_clk = { 1853 .halt_reg = 0xb0d0, 1854 .halt_check = BRANCH_HALT, 1855 .clkr = { 1856 .enable_reg = 0xb0d0, 1857 .enable_mask = BIT(0), 1858 .hw.init = &(struct clk_init_data){ 1859 .name = "cam_cc_ife_2_cphy_rx_clk", 1860 .parent_hws = (const struct clk_hw*[]) { 1861 &cam_cc_cphy_rx_clk_src.clkr.hw, 1862 }, 1863 .num_parents = 1, 1864 .flags = CLK_SET_RATE_PARENT, 1865 .ops = &clk_branch2_ops, 1866 }, 1867 }, 1868}; 1869 1870static struct clk_branch cam_cc_ife_2_csid_clk = { 1871 .halt_reg = 0xb0c0, 1872 .halt_check = BRANCH_HALT, 1873 .clkr = { 1874 .enable_reg = 0xb0c0, 1875 .enable_mask = BIT(0), 1876 .hw.init = &(struct clk_init_data){ 1877 .name = "cam_cc_ife_2_csid_clk", 1878 .parent_hws = (const struct clk_hw*[]) { 1879 &cam_cc_ife_2_csid_clk_src.clkr.hw, 1880 }, 1881 .num_parents = 1, 1882 .flags = CLK_SET_RATE_PARENT, 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886}; 1887 1888static struct clk_branch cam_cc_ife_2_dsp_clk = { 1889 .halt_reg = 0xb0a4, 1890 .halt_check = BRANCH_HALT, 1891 .clkr = { 1892 .enable_reg = 0xb0a4, 1893 .enable_mask = BIT(0), 1894 .hw.init = &(struct clk_init_data){ 1895 .name = "cam_cc_ife_2_dsp_clk", 1896 .parent_hws = (const struct clk_hw*[]) { 1897 &cam_cc_ife_2_clk_src.clkr.hw, 1898 }, 1899 .num_parents = 1, 1900 .flags = CLK_SET_RATE_PARENT, 1901 .ops = &clk_branch2_ops, 1902 }, 1903 }, 1904}; 1905 1906static struct clk_branch cam_cc_ife_lite_0_clk = { 1907 .halt_reg = 0xc01c, 1908 .halt_check = BRANCH_HALT, 1909 .clkr = { 1910 .enable_reg = 0xc01c, 1911 .enable_mask = BIT(0), 1912 .hw.init = &(struct clk_init_data){ 1913 .name = "cam_cc_ife_lite_0_clk", 1914 .parent_hws = (const struct clk_hw*[]) { 1915 &cam_cc_ife_lite_0_clk_src.clkr.hw, 1916 }, 1917 .num_parents = 1, 1918 .flags = CLK_SET_RATE_PARENT, 1919 .ops = &clk_branch2_ops, 1920 }, 1921 }, 1922}; 1923 1924static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = { 1925 .halt_reg = 0xc040, 1926 .halt_check = BRANCH_HALT, 1927 .clkr = { 1928 .enable_reg = 0xc040, 1929 .enable_mask = BIT(0), 1930 .hw.init = &(struct clk_init_data){ 1931 .name = "cam_cc_ife_lite_0_cphy_rx_clk", 1932 .parent_hws = (const struct clk_hw*[]) { 1933 &cam_cc_cphy_rx_clk_src.clkr.hw, 1934 }, 1935 .num_parents = 1, 1936 .flags = CLK_SET_RATE_PARENT, 1937 .ops = &clk_branch2_ops, 1938 }, 1939 }, 1940}; 1941 1942static struct clk_branch cam_cc_ife_lite_0_csid_clk = { 1943 .halt_reg = 0xc038, 1944 .halt_check = BRANCH_HALT, 1945 .clkr = { 1946 .enable_reg = 0xc038, 1947 .enable_mask = BIT(0), 1948 .hw.init = &(struct clk_init_data){ 1949 .name = "cam_cc_ife_lite_0_csid_clk", 1950 .parent_hws = (const struct clk_hw*[]) { 1951 &cam_cc_ife_lite_0_csid_clk_src.clkr.hw, 1952 }, 1953 .num_parents = 1, 1954 .flags = CLK_SET_RATE_PARENT, 1955 .ops = &clk_branch2_ops, 1956 }, 1957 }, 1958}; 1959 1960static struct clk_branch cam_cc_ife_lite_1_clk = { 1961 .halt_reg = 0xc060, 1962 .halt_check = BRANCH_HALT, 1963 .clkr = { 1964 .enable_reg = 0xc060, 1965 .enable_mask = BIT(0), 1966 .hw.init = &(struct clk_init_data){ 1967 .name = "cam_cc_ife_lite_1_clk", 1968 .parent_hws = (const struct clk_hw*[]) { 1969 &cam_cc_ife_lite_1_clk_src.clkr.hw, 1970 }, 1971 .num_parents = 1, 1972 .flags = CLK_SET_RATE_PARENT, 1973 .ops = &clk_branch2_ops, 1974 }, 1975 }, 1976}; 1977 1978static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = { 1979 .halt_reg = 0xc084, 1980 .halt_check = BRANCH_HALT, 1981 .clkr = { 1982 .enable_reg = 0xc084, 1983 .enable_mask = BIT(0), 1984 .hw.init = &(struct clk_init_data){ 1985 .name = "cam_cc_ife_lite_1_cphy_rx_clk", 1986 .parent_hws = (const struct clk_hw*[]) { 1987 &cam_cc_cphy_rx_clk_src.clkr.hw, 1988 }, 1989 .num_parents = 1, 1990 .flags = CLK_SET_RATE_PARENT, 1991 .ops = &clk_branch2_ops, 1992 }, 1993 }, 1994}; 1995 1996static struct clk_branch cam_cc_ife_lite_1_csid_clk = { 1997 .halt_reg = 0xc07c, 1998 .halt_check = BRANCH_HALT, 1999 .clkr = { 2000 .enable_reg = 0xc07c, 2001 .enable_mask = BIT(0), 2002 .hw.init = &(struct clk_init_data){ 2003 .name = "cam_cc_ife_lite_1_csid_clk", 2004 .parent_hws = (const struct clk_hw*[]) { 2005 &cam_cc_ife_lite_1_csid_clk_src.clkr.hw, 2006 }, 2007 .num_parents = 1, 2008 .flags = CLK_SET_RATE_PARENT, 2009 .ops = &clk_branch2_ops, 2010 }, 2011 }, 2012}; 2013 2014static struct clk_branch cam_cc_ipe_0_ahb_clk = { 2015 .halt_reg = 0x8040, 2016 .halt_check = BRANCH_HALT, 2017 .clkr = { 2018 .enable_reg = 0x8040, 2019 .enable_mask = BIT(0), 2020 .hw.init = &(struct clk_init_data){ 2021 .name = "cam_cc_ipe_0_ahb_clk", 2022 .parent_hws = (const struct clk_hw*[]) { 2023 &cam_cc_slow_ahb_clk_src.clkr.hw, 2024 }, 2025 .num_parents = 1, 2026 .flags = CLK_SET_RATE_PARENT, 2027 .ops = &clk_branch2_ops, 2028 }, 2029 }, 2030}; 2031 2032static struct clk_branch cam_cc_ipe_0_areg_clk = { 2033 .halt_reg = 0x803c, 2034 .halt_check = BRANCH_HALT, 2035 .clkr = { 2036 .enable_reg = 0x803c, 2037 .enable_mask = BIT(0), 2038 .hw.init = &(struct clk_init_data){ 2039 .name = "cam_cc_ipe_0_areg_clk", 2040 .parent_hws = (const struct clk_hw*[]) { 2041 &cam_cc_fast_ahb_clk_src.clkr.hw, 2042 }, 2043 .num_parents = 1, 2044 .flags = CLK_SET_RATE_PARENT, 2045 .ops = &clk_branch2_ops, 2046 }, 2047 }, 2048}; 2049 2050static struct clk_branch cam_cc_ipe_0_axi_clk = { 2051 .halt_reg = 0x8038, 2052 .halt_check = BRANCH_HALT, 2053 .clkr = { 2054 .enable_reg = 0x8038, 2055 .enable_mask = BIT(0), 2056 .hw.init = &(struct clk_init_data){ 2057 .name = "cam_cc_ipe_0_axi_clk", 2058 .parent_hws = (const struct clk_hw*[]) { 2059 &cam_cc_camnoc_axi_clk_src.clkr.hw, 2060 }, 2061 .num_parents = 1, 2062 .flags = CLK_SET_RATE_PARENT, 2063 .ops = &clk_branch2_ops, 2064 }, 2065 }, 2066}; 2067 2068static struct clk_branch cam_cc_ipe_0_clk = { 2069 .halt_reg = 0x8028, 2070 .halt_check = BRANCH_HALT, 2071 .clkr = { 2072 .enable_reg = 0x8028, 2073 .enable_mask = BIT(0), 2074 .hw.init = &(struct clk_init_data){ 2075 .name = "cam_cc_ipe_0_clk", 2076 .parent_hws = (const struct clk_hw*[]) { 2077 &cam_cc_ipe_0_clk_src.clkr.hw, 2078 }, 2079 .num_parents = 1, 2080 .flags = CLK_SET_RATE_PARENT, 2081 .ops = &clk_branch2_ops, 2082 }, 2083 }, 2084}; 2085 2086static struct clk_branch cam_cc_jpeg_clk = { 2087 .halt_reg = 0xc0a4, 2088 .halt_check = BRANCH_HALT, 2089 .clkr = { 2090 .enable_reg = 0xc0a4, 2091 .enable_mask = BIT(0), 2092 .hw.init = &(struct clk_init_data){ 2093 .name = "cam_cc_jpeg_clk", 2094 .parent_hws = (const struct clk_hw*[]) { 2095 &cam_cc_jpeg_clk_src.clkr.hw, 2096 }, 2097 .num_parents = 1, 2098 .flags = CLK_SET_RATE_PARENT, 2099 .ops = &clk_branch2_ops, 2100 }, 2101 }, 2102}; 2103 2104static struct clk_branch cam_cc_lrme_clk = { 2105 .halt_reg = 0xc168, 2106 .halt_check = BRANCH_HALT, 2107 .clkr = { 2108 .enable_reg = 0xc168, 2109 .enable_mask = BIT(0), 2110 .hw.init = &(struct clk_init_data){ 2111 .name = "cam_cc_lrme_clk", 2112 .parent_hws = (const struct clk_hw*[]) { 2113 &cam_cc_lrme_clk_src.clkr.hw, 2114 }, 2115 .num_parents = 1, 2116 .flags = CLK_SET_RATE_PARENT, 2117 .ops = &clk_branch2_ops, 2118 }, 2119 }, 2120}; 2121 2122static struct clk_branch cam_cc_mclk0_clk = { 2123 .halt_reg = 0xe018, 2124 .halt_check = BRANCH_HALT, 2125 .clkr = { 2126 .enable_reg = 0xe018, 2127 .enable_mask = BIT(0), 2128 .hw.init = &(struct clk_init_data){ 2129 .name = "cam_cc_mclk0_clk", 2130 .parent_hws = (const struct clk_hw*[]) { 2131 &cam_cc_mclk0_clk_src.clkr.hw, 2132 }, 2133 .num_parents = 1, 2134 .flags = CLK_SET_RATE_PARENT, 2135 .ops = &clk_branch2_ops, 2136 }, 2137 }, 2138}; 2139 2140static struct clk_branch cam_cc_mclk1_clk = { 2141 .halt_reg = 0xe034, 2142 .halt_check = BRANCH_HALT, 2143 .clkr = { 2144 .enable_reg = 0xe034, 2145 .enable_mask = BIT(0), 2146 .hw.init = &(struct clk_init_data){ 2147 .name = "cam_cc_mclk1_clk", 2148 .parent_hws = (const struct clk_hw*[]) { 2149 &cam_cc_mclk1_clk_src.clkr.hw, 2150 }, 2151 .num_parents = 1, 2152 .flags = CLK_SET_RATE_PARENT, 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156}; 2157 2158static struct clk_branch cam_cc_mclk2_clk = { 2159 .halt_reg = 0xe050, 2160 .halt_check = BRANCH_HALT, 2161 .clkr = { 2162 .enable_reg = 0xe050, 2163 .enable_mask = BIT(0), 2164 .hw.init = &(struct clk_init_data){ 2165 .name = "cam_cc_mclk2_clk", 2166 .parent_hws = (const struct clk_hw*[]) { 2167 &cam_cc_mclk2_clk_src.clkr.hw, 2168 }, 2169 .num_parents = 1, 2170 .flags = CLK_SET_RATE_PARENT, 2171 .ops = &clk_branch2_ops, 2172 }, 2173 }, 2174}; 2175 2176static struct clk_branch cam_cc_mclk3_clk = { 2177 .halt_reg = 0xe06c, 2178 .halt_check = BRANCH_HALT, 2179 .clkr = { 2180 .enable_reg = 0xe06c, 2181 .enable_mask = BIT(0), 2182 .hw.init = &(struct clk_init_data){ 2183 .name = "cam_cc_mclk3_clk", 2184 .parent_hws = (const struct clk_hw*[]) { 2185 &cam_cc_mclk3_clk_src.clkr.hw, 2186 }, 2187 .num_parents = 1, 2188 .flags = CLK_SET_RATE_PARENT, 2189 .ops = &clk_branch2_ops, 2190 }, 2191 }, 2192}; 2193 2194static struct clk_branch cam_cc_mclk4_clk = { 2195 .halt_reg = 0xe088, 2196 .halt_check = BRANCH_HALT, 2197 .clkr = { 2198 .enable_reg = 0xe088, 2199 .enable_mask = BIT(0), 2200 .hw.init = &(struct clk_init_data){ 2201 .name = "cam_cc_mclk4_clk", 2202 .parent_hws = (const struct clk_hw*[]) { 2203 &cam_cc_mclk4_clk_src.clkr.hw, 2204 }, 2205 .num_parents = 1, 2206 .flags = CLK_SET_RATE_PARENT, 2207 .ops = &clk_branch2_ops, 2208 }, 2209 }, 2210}; 2211 2212static struct clk_branch cam_cc_mclk5_clk = { 2213 .halt_reg = 0xe0a4, 2214 .halt_check = BRANCH_HALT, 2215 .clkr = { 2216 .enable_reg = 0xe0a4, 2217 .enable_mask = BIT(0), 2218 .hw.init = &(struct clk_init_data){ 2219 .name = "cam_cc_mclk5_clk", 2220 .parent_hws = (const struct clk_hw*[]) { 2221 &cam_cc_mclk5_clk_src.clkr.hw, 2222 }, 2223 .num_parents = 1, 2224 .flags = CLK_SET_RATE_PARENT, 2225 .ops = &clk_branch2_ops, 2226 }, 2227 }, 2228}; 2229 2230static struct clk_branch cam_cc_sleep_clk = { 2231 .halt_reg = 0xc1d8, 2232 .halt_check = BRANCH_HALT, 2233 .clkr = { 2234 .enable_reg = 0xc1d8, 2235 .enable_mask = BIT(0), 2236 .hw.init = &(struct clk_init_data){ 2237 .name = "cam_cc_sleep_clk", 2238 .parent_hws = (const struct clk_hw*[]) { 2239 &cam_cc_sleep_clk_src.clkr.hw, 2240 }, 2241 .num_parents = 1, 2242 .flags = CLK_SET_RATE_PARENT, 2243 .ops = &clk_branch2_ops, 2244 }, 2245 }, 2246}; 2247 2248static struct gdsc cam_cc_titan_top_gdsc = { 2249 .gdscr = 0xc194, 2250 .pd = { 2251 .name = "cam_cc_titan_top_gdsc", 2252 }, 2253 .pwrsts = PWRSTS_OFF_ON, 2254 .flags = RETAIN_FF_ENABLE, 2255}; 2256 2257static struct gdsc cam_cc_bps_gdsc = { 2258 .gdscr = 0x7004, 2259 .pd = { 2260 .name = "cam_cc_bps_gdsc", 2261 }, 2262 .pwrsts = PWRSTS_OFF_ON, 2263 .flags = HW_CTRL | RETAIN_FF_ENABLE, 2264}; 2265 2266static struct gdsc cam_cc_ife_0_gdsc = { 2267 .gdscr = 0xa004, 2268 .pd = { 2269 .name = "cam_cc_ife_0_gdsc", 2270 }, 2271 .pwrsts = PWRSTS_OFF_ON, 2272 .flags = RETAIN_FF_ENABLE, 2273}; 2274 2275static struct gdsc cam_cc_ife_1_gdsc = { 2276 .gdscr = 0xb004, 2277 .pd = { 2278 .name = "cam_cc_ife_1_gdsc", 2279 }, 2280 .pwrsts = PWRSTS_OFF_ON, 2281 .flags = RETAIN_FF_ENABLE, 2282}; 2283 2284static struct gdsc cam_cc_ife_2_gdsc = { 2285 .gdscr = 0xb070, 2286 .pd = { 2287 .name = "cam_cc_ife_2_gdsc", 2288 }, 2289 .pwrsts = PWRSTS_OFF_ON, 2290 .flags = RETAIN_FF_ENABLE, 2291}; 2292 2293static struct gdsc cam_cc_ipe_0_gdsc = { 2294 .gdscr = 0x8004, 2295 .pd = { 2296 .name = "cam_cc_ipe_0_gdsc", 2297 }, 2298 .pwrsts = PWRSTS_OFF_ON, 2299 .flags = HW_CTRL | RETAIN_FF_ENABLE, 2300}; 2301 2302static struct clk_regmap *cam_cc_sc7280_clocks[] = { 2303 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 2304 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 2305 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 2306 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 2307 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 2308 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 2309 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 2310 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2311 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2312 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2313 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2314 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2315 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2316 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2317 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2318 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2319 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2320 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2321 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2322 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2323 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2324 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2325 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2326 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2327 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2328 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2329 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2330 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2331 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2332 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2333 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2334 [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr, 2335 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2336 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2337 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2338 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 2339 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2340 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2341 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 2342 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 2343 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 2344 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2345 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 2346 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 2347 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 2348 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 2349 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 2350 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 2351 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 2352 [CAM_CC_IFE_2_AXI_CLK] = &cam_cc_ife_2_axi_clk.clkr, 2353 [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, 2354 [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, 2355 [CAM_CC_IFE_2_CPHY_RX_CLK] = &cam_cc_ife_2_cphy_rx_clk.clkr, 2356 [CAM_CC_IFE_2_CSID_CLK] = &cam_cc_ife_2_csid_clk.clkr, 2357 [CAM_CC_IFE_2_CSID_CLK_SRC] = &cam_cc_ife_2_csid_clk_src.clkr, 2358 [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr, 2359 [CAM_CC_IFE_LITE_0_CLK] = &cam_cc_ife_lite_0_clk.clkr, 2360 [CAM_CC_IFE_LITE_0_CLK_SRC] = &cam_cc_ife_lite_0_clk_src.clkr, 2361 [CAM_CC_IFE_LITE_0_CPHY_RX_CLK] = &cam_cc_ife_lite_0_cphy_rx_clk.clkr, 2362 [CAM_CC_IFE_LITE_0_CSID_CLK] = &cam_cc_ife_lite_0_csid_clk.clkr, 2363 [CAM_CC_IFE_LITE_0_CSID_CLK_SRC] = &cam_cc_ife_lite_0_csid_clk_src.clkr, 2364 [CAM_CC_IFE_LITE_1_CLK] = &cam_cc_ife_lite_1_clk.clkr, 2365 [CAM_CC_IFE_LITE_1_CLK_SRC] = &cam_cc_ife_lite_1_clk_src.clkr, 2366 [CAM_CC_IFE_LITE_1_CPHY_RX_CLK] = &cam_cc_ife_lite_1_cphy_rx_clk.clkr, 2367 [CAM_CC_IFE_LITE_1_CSID_CLK] = &cam_cc_ife_lite_1_csid_clk.clkr, 2368 [CAM_CC_IFE_LITE_1_CSID_CLK_SRC] = &cam_cc_ife_lite_1_csid_clk_src.clkr, 2369 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 2370 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 2371 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 2372 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 2373 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 2374 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2375 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2376 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 2377 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 2378 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2379 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2380 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2381 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2382 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2383 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2384 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2385 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2386 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2387 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2388 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, 2389 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, 2390 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2391 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2392 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2393 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2394 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2395 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2396 [CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr, 2397 [CAM_CC_PLL2_OUT_AUX2] = &cam_cc_pll2_out_aux2.clkr, 2398 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2399 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2400 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2401 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2402 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2403 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 2404 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2405 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2406 [CAM_CC_PLL6_OUT_ODD] = &cam_cc_pll6_out_odd.clkr, 2407 [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr, 2408 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2409 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2410 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2411}; 2412 2413static struct gdsc *cam_cc_sc7280_gdscs[] = { 2414 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2415 [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, 2416 [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, 2417 [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, 2418 [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc, 2419 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2420}; 2421 2422static const struct regmap_config cam_cc_sc7280_regmap_config = { 2423 .reg_bits = 32, 2424 .reg_stride = 4, 2425 .val_bits = 32, 2426 .max_register = 0xf00c, 2427 .fast_io = true, 2428}; 2429 2430static const struct qcom_cc_desc cam_cc_sc7280_desc = { 2431 .config = &cam_cc_sc7280_regmap_config, 2432 .clks = cam_cc_sc7280_clocks, 2433 .num_clks = ARRAY_SIZE(cam_cc_sc7280_clocks), 2434 .gdscs = cam_cc_sc7280_gdscs, 2435 .num_gdscs = ARRAY_SIZE(cam_cc_sc7280_gdscs), 2436}; 2437 2438static const struct of_device_id cam_cc_sc7280_match_table[] = { 2439 { .compatible = "qcom,sc7280-camcc" }, 2440 { } 2441}; 2442MODULE_DEVICE_TABLE(of, cam_cc_sc7280_match_table); 2443 2444static int cam_cc_sc7280_probe(struct platform_device *pdev) 2445{ 2446 struct regmap *regmap; 2447 2448 regmap = qcom_cc_map(pdev, &cam_cc_sc7280_desc); 2449 if (IS_ERR(regmap)) 2450 return PTR_ERR(regmap); 2451 2452 clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 2453 clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 2454 clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 2455 clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 2456 clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); 2457 clk_lucid_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); 2458 clk_lucid_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); 2459 2460 return qcom_cc_really_probe(pdev, &cam_cc_sc7280_desc, regmap); 2461} 2462 2463static struct platform_driver cam_cc_sc7280_driver = { 2464 .probe = cam_cc_sc7280_probe, 2465 .driver = { 2466 .name = "cam_cc-sc7280", 2467 .of_match_table = cam_cc_sc7280_match_table, 2468 }, 2469}; 2470 2471module_platform_driver(cam_cc_sc7280_driver); 2472 2473MODULE_DESCRIPTION("QTI CAM_CC SC7280 Driver"); 2474MODULE_LICENSE("GPL v2"); 2475