1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2/* 3 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved 4 * Author: Yu Tu <yu.tu@amlogic.com> 5 */ 6 7#ifndef __MESON_S4_PERIPHERALS_H__ 8#define __MESON_S4_PERIPHERALS_H__ 9 10#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008 11#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c 12#define CLKCTRL_RTC_CTRL 0x010 13#define CLKCTRL_SYS_CLK_CTRL0 0x040 14#define CLKCTRL_SYS_CLK_EN0_REG0 0x044 15#define CLKCTRL_SYS_CLK_EN0_REG1 0x048 16#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c 17#define CLKCTRL_SYS_CLK_EN0_REG3 0x050 18#define CLKCTRL_CECA_CTRL0 0x088 19#define CLKCTRL_CECA_CTRL1 0x08c 20#define CLKCTRL_CECB_CTRL0 0x090 21#define CLKCTRL_CECB_CTRL1 0x094 22#define CLKCTRL_SC_CLK_CTRL 0x098 23#define CLKCTRL_CLK12_24_CTRL 0x0a8 24#define CLKCTRL_VID_CLK_CTRL 0x0c0 25#define CLKCTRL_VID_CLK_CTRL2 0x0c4 26#define CLKCTRL_VID_CLK_DIV 0x0c8 27#define CLKCTRL_VIID_CLK_DIV 0x0cc 28#define CLKCTRL_VIID_CLK_CTRL 0x0d0 29#define CLKCTRL_HDMI_CLK_CTRL 0x0e0 30#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4 31#define CLKCTRL_VPU_CLK_CTRL 0x0e8 32#define CLKCTRL_VPU_CLKB_CTRL 0x0ec 33#define CLKCTRL_VPU_CLKC_CTRL 0x0f0 34#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4 35#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 36#define CLKCTRL_VAPBCLK_CTRL 0x0fc 37#define CLKCTRL_HDCP22_CTRL 0x100 38#define CLKCTRL_VDEC_CLK_CTRL 0x140 39#define CLKCTRL_VDEC2_CLK_CTRL 0x144 40#define CLKCTRL_VDEC3_CLK_CTRL 0x148 41#define CLKCTRL_VDEC4_CLK_CTRL 0x14c 42#define CLKCTRL_TS_CLK_CTRL 0x158 43#define CLKCTRL_MALI_CLK_CTRL 0x15c 44#define CLKCTRL_NAND_CLK_CTRL 0x168 45#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c 46#define CLKCTRL_SPICC_CLK_CTRL 0x174 47#define CLKCTRL_GEN_CLK_CTRL 0x178 48#define CLKCTRL_SAR_CLK_CTRL 0x17c 49#define CLKCTRL_PWM_CLK_AB_CTRL 0x180 50#define CLKCTRL_PWM_CLK_CD_CTRL 0x184 51#define CLKCTRL_PWM_CLK_EF_CTRL 0x188 52#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c 53#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 54#define CLKCTRL_DEMOD_CLK_CTRL 0x200 55 56#endif /* __MESON_S4_PERIPHERALS_H__ */ 57