1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 *         Fabien Parent <fparent@baylibre.com>
6 * Copyright (c) 2023 Collabora Ltd.
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/mod_devicetable.h>
11#include <linux/platform_device.h>
12
13#include "clk-mtk.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt8516-clk.h>
17
18static const struct mtk_gate_regs aud_cg_regs = {
19	.set_ofs = 0x0,
20	.clr_ofs = 0x0,
21	.sta_ofs = 0x0,
22};
23
24#define GATE_AUD(_id, _name, _parent, _shift)			\
25	GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
26
27static const struct mtk_gate aud_clks[] = {
28	GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
29	GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
30	GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
31	GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
32	GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
33	GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
34	GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
35	GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
36	GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
37	GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
38	GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
39	GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
40	GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
41};
42
43static const struct mtk_clk_desc aud_desc = {
44	.clks = aud_clks,
45	.num_clks = ARRAY_SIZE(aud_clks),
46};
47
48static const struct of_device_id of_match_clk_mt8516_aud[] = {
49	{ .compatible = "mediatek,mt8516-audsys", .data = &aud_desc },
50	{ /* sentinel */ }
51};
52MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_aud);
53
54static struct platform_driver clk_mt8516_aud_drv = {
55	.probe = mtk_clk_simple_probe,
56	.remove_new = mtk_clk_simple_remove,
57	.driver = {
58		.name = "clk-mt8516-aud",
59		.of_match_table = of_match_clk_mt8516_aud,
60	},
61};
62module_platform_driver(clk_mt8516_aud_drv);
63
64MODULE_DESCRIPTION("MediaTek MT8516 audiosys clocks driver");
65MODULE_LICENSE("GPL");
66