1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6 * Author: Jianhui Zhao <zhaojh329@gmail.com>
7 * Author: Daniel Golle <daniel@makrotopia.org>
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/mod_devicetable.h>
12#include <linux/platform_device.h>
13
14#include "clk-gate.h"
15#include "clk-mtk.h"
16#include "clk-mux.h"
17#include "clk-pll.h"
18
19#include <dt-bindings/clock/mediatek,mt7981-clk.h>
20#include <linux/clk.h>
21
22#define MT7981_PLL_FMAX (2500UL * MHZ)
23#define CON0_MT7981_RST_BAR BIT(27)
24
25#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
26		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
27		 _div_table, _parent_name)                                     \
28	{                                                                      \
29		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
30		.en_mask = _en_mask, .flags = _flags,                          \
31		.rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX,  \
32		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
33		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
34		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
35		.parent_name = _parent_name,                                   \
36	}
37
38#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
39	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
40	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
41		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
42		 "clkxtal")
43
44static const struct mtk_pll_data plls[] = {
45	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
46	    32, 0x0200, 4, 0, 0x0204, 0),
47	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
48	    0x0210, 4, 0, 0x0214, 0),
49	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
50	    0x0220, 4, 0, 0x0224, 0),
51	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
52	    0x0230, 4, 0, 0x0234, 0),
53	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
54	    0x0240, 4, 0, 0x0244, 0),
55	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
56	    0x0250, 4, 0, 0x0254, 0),
57	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
58	    0x0260, 4, 0, 0x0264, 0),
59	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
60	    0x0278, 4, 0, 0x027C, 0),
61};
62
63static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
64	{ .compatible = "mediatek,mt7981-apmixedsys", },
65	{ /* sentinel */ }
66};
67MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_apmixed);
68
69static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
70{
71	struct clk_hw_onecell_data *clk_data;
72	struct device_node *node = pdev->dev.of_node;
73	int r;
74
75	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
76	if (!clk_data)
77		return -ENOMEM;
78
79	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
80
81	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
82	if (r) {
83		pr_err("%s(): could not register clock provider: %d\n",
84		       __func__, r);
85		goto free_apmixed_data;
86	}
87	return r;
88
89free_apmixed_data:
90	mtk_free_clk_data(clk_data);
91	return r;
92}
93
94static struct platform_driver clk_mt7981_apmixed_drv = {
95	.probe = clk_mt7981_apmixed_probe,
96	.driver = {
97		.name = "clk-mt7981-apmixed",
98		.of_match_table = of_match_clk_mt7981_apmixed,
99	},
100};
101builtin_platform_driver(clk_mt7981_apmixed_drv);
102MODULE_LICENSE("GPL");
103