1/*****************************************************************************
2 *
3 *     Author: Xilinx, Inc.
4 *
5 *     This program is free software; you can redistribute it and/or modify it
6 *     under the terms of the GNU General Public License as published by the
7 *     Free Software Foundation; either version 2 of the License, or (at your
8 *     option) any later version.
9 *
10 *     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
11 *     AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
12 *     SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
13 *     OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
14 *     APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
15 *     THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
16 *     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
17 *     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
18 *     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
19 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
20 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
21 *     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
22 *     FOR A PARTICULAR PURPOSE.
23 *
24 *     (c) Copyright 2003-2007 Xilinx Inc.
25 *     All rights reserved.
26 *
27 *     You should have received a copy of the GNU General Public License along
28 *     with this program; if not, write to the Free Software Foundation, Inc.,
29 *     675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 *****************************************************************************/
32
33#ifndef XILINX_HWICAP_H_	/* prevent circular inclusions */
34#define XILINX_HWICAP_H_	/* by using protection macros */
35
36#include <linux/types.h>
37#include <linux/cdev.h>
38#include <linux/platform_device.h>
39
40#include <linux/io.h>
41
42struct hwicap_drvdata {
43	u32 write_buffer_in_use;  /* Always in [0,3] */
44	u8 write_buffer[4];
45	u32 read_buffer_in_use;	  /* Always in [0,3] */
46	u8 read_buffer[4];
47	resource_size_t mem_start;/* phys. address of the control registers */
48	resource_size_t mem_end;  /* phys. address of the control registers */
49	resource_size_t mem_size;
50	void __iomem *base_address;/* virt. address of the control registers */
51
52	struct device *dev;
53	struct cdev cdev;	/* Char device structure */
54	dev_t devt;
55
56	const struct hwicap_driver_config *config;
57	const struct config_registers *config_regs;
58	void *private_data;
59	bool is_open;
60	struct mutex sem;
61};
62
63struct hwicap_driver_config {
64	/* Read configuration data given by size into the data buffer.
65	 * Return 0 if successful.
66	 */
67	int (*get_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
68			u32 size);
69	/* Write configuration data given by size from the data buffer.
70	 * Return 0 if successful.
71	 */
72	int (*set_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
73			u32 size);
74	/* Get the status register, bit pattern given by:
75	 * D8 - 0 = configuration error
76	 * D7 - 1 = alignment found
77	 * D6 - 1 = readback in progress
78	 * D5 - 0 = abort in progress
79	 * D4 - Always 1
80	 * D3 - Always 1
81	 * D2 - Always 1
82	 * D1 - Always 1
83	 * D0 - 1 = operation completed
84	 */
85	u32 (*get_status)(struct hwicap_drvdata *drvdata);
86	/* Reset the hw */
87	void (*reset)(struct hwicap_drvdata *drvdata);
88};
89
90/* Number of times to poll the done register. This has to be large
91 * enough to allow an entire configuration to complete. If an entire
92 * page (4kb) is configured at once, that could take up to 4k cycles
93 * with a byte-wide icap interface. In most cases, this driver is
94 * used with a much smaller fifo, but this should be sufficient in the
95 * worst case.
96 */
97#define XHI_MAX_RETRIES     5000
98
99/************ Constant Definitions *************/
100
101#define XHI_PAD_FRAMES              0x1
102
103/* Mask for calculating configuration packet headers */
104#define XHI_WORD_COUNT_MASK_TYPE_1  0x7FFUL
105#define XHI_WORD_COUNT_MASK_TYPE_2  0x1FFFFFUL
106#define XHI_TYPE_MASK               0x7
107#define XHI_REGISTER_MASK           0xF
108#define XHI_OP_MASK                 0x3
109
110#define XHI_TYPE_SHIFT              29
111#define XHI_REGISTER_SHIFT          13
112#define XHI_OP_SHIFT                27
113
114#define XHI_TYPE_1                  1
115#define XHI_TYPE_2                  2
116#define XHI_OP_WRITE                2
117#define XHI_OP_READ                 1
118
119/* Address Block Types */
120#define XHI_FAR_CLB_BLOCK           0
121#define XHI_FAR_BRAM_BLOCK          1
122#define XHI_FAR_BRAM_INT_BLOCK      2
123
124struct config_registers {
125	u32 CRC;
126	u32 FAR;
127	u32 FDRI;
128	u32 FDRO;
129	u32 CMD;
130	u32 CTL;
131	u32 MASK;
132	u32 STAT;
133	u32 LOUT;
134	u32 COR;
135	u32 MFWR;
136	u32 FLR;
137	u32 KEY;
138	u32 CBC;
139	u32 IDCODE;
140	u32 AXSS;
141	u32 C0R_1;
142	u32 CSOB;
143	u32 WBSTAR;
144	u32 TIMER;
145	u32 BOOTSTS;
146	u32 CTL_1;
147};
148
149/* Configuration Commands */
150#define XHI_CMD_NULL                0
151#define XHI_CMD_WCFG                1
152#define XHI_CMD_MFW                 2
153#define XHI_CMD_DGHIGH              3
154#define XHI_CMD_RCFG                4
155#define XHI_CMD_START               5
156#define XHI_CMD_RCAP                6
157#define XHI_CMD_RCRC                7
158#define XHI_CMD_AGHIGH              8
159#define XHI_CMD_SWITCH              9
160#define XHI_CMD_GRESTORE            10
161#define XHI_CMD_SHUTDOWN            11
162#define XHI_CMD_GCAPTURE            12
163#define XHI_CMD_DESYNCH             13
164#define XHI_CMD_IPROG               15 /* Only in Virtex5 */
165#define XHI_CMD_CRCC                16 /* Only in Virtex5 */
166#define XHI_CMD_LTIMER              17 /* Only in Virtex5 */
167
168/* Packet constants */
169#define XHI_SYNC_PACKET             0xAA995566UL
170#define XHI_DUMMY_PACKET            0xFFFFFFFFUL
171#define XHI_NOOP_PACKET             (XHI_TYPE_1 << XHI_TYPE_SHIFT)
172#define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
173			(XHI_OP_READ << XHI_OP_SHIFT))
174
175#define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
176			(XHI_OP_WRITE << XHI_OP_SHIFT))
177
178#define XHI_TYPE2_CNT_MASK          0x07FFFFFF
179
180#define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL
181#define XHI_TYPE_1_HEADER_BYTES     4
182#define XHI_TYPE_2_HEADER_BYTES     8
183
184/* Constant to use for CRC check when CRC has been disabled */
185#define XHI_DISABLED_AUTO_CRC       0x0000DEFCUL
186
187/* Meanings of the bits returned by get_status */
188#define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */
189#define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */
190#define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */
191#define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */
192#define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask  */
193
194/**
195 * hwicap_type_1_read - Generates a Type 1 read packet header.
196 * @reg: is the address of the register to be read back.
197 *
198 * Return:
199 * Generates a Type 1 read packet header, which is used to indirectly
200 * read registers in the configuration logic.  This packet must then
201 * be sent through the icap device, and a return packet received with
202 * the information.
203 */
204static inline u32 hwicap_type_1_read(u32 reg)
205{
206	return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
207		(reg << XHI_REGISTER_SHIFT) |
208		(XHI_OP_READ << XHI_OP_SHIFT);
209}
210
211/**
212 * hwicap_type_1_write - Generates a Type 1 write packet header
213 * @reg: is the address of the register to be read back.
214 *
215 * Return: Type 1 write packet header
216 */
217static inline u32 hwicap_type_1_write(u32 reg)
218{
219	return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
220		(reg << XHI_REGISTER_SHIFT) |
221		(XHI_OP_WRITE << XHI_OP_SHIFT);
222}
223
224#endif
225