1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * pata_optidma.c 	- Opti DMA PATA for new ATA layer
4 *			  (C) 2006 Red Hat Inc
5 *
6 *	The Opti DMA controllers are related to the older PIO PCI controllers
7 *	and indeed the VLB ones. The main differences are that the timing
8 *	numbers are now based off PCI clocks not VLB and differ, and that
9 *	MWDMA is supported.
10 *
11 *	This driver should support Viper-N+, FireStar, FireStar Plus.
12 *
13 *	These devices support virtual DMA for read (aka the CS5520). Later
14 *	chips support UDMA33, but only if the rest of the board logic does,
15 *	so you have to get this right. We don't support the virtual DMA
16 *	but we do handle UDMA.
17 *
18 *	Bits that are worth knowing
19 *		Most control registers are shadowed into I/O registers
20 *		0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
21 *		Virtual DMA registers *move* between rev 0x02 and rev 0x10
22 *		UDMA requires a 66MHz FSB
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <scsi/scsi_host.h>
32#include <linux/libata.h>
33
34#define DRV_NAME "pata_optidma"
35#define DRV_VERSION "0.3.2"
36
37enum {
38	READ_REG	= 0,	/* index of Read cycle timing register */
39	WRITE_REG 	= 1,	/* index of Write cycle timing register */
40	CNTRL_REG 	= 3,	/* index of Control register */
41	STRAP_REG 	= 5,	/* index of Strap register */
42	MISC_REG 	= 6	/* index of Miscellaneous register */
43};
44
45static int pci_clock;	/* 0 = 33 1 = 25 */
46
47/**
48 *	optidma_pre_reset		-	probe begin
49 *	@link: ATA link
50 *	@deadline: deadline jiffies for the operation
51 *
52 *	Set up cable type and use generic probe init
53 */
54
55static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
56{
57	struct ata_port *ap = link->ap;
58	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
59	static const struct pci_bits optidma_enable_bits = {
60		0x40, 1, 0x08, 0x00
61	};
62
63	if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
64		return -ENOENT;
65
66	return ata_sff_prereset(link, deadline);
67}
68
69/**
70 *	optidma_unlock		-	unlock control registers
71 *	@ap: ATA port
72 *
73 *	Unlock the control register block for this adapter. Registers must not
74 *	be unlocked in a situation where libata might look at them.
75 */
76
77static void optidma_unlock(struct ata_port *ap)
78{
79	void __iomem *regio = ap->ioaddr.cmd_addr;
80
81	/* These 3 unlock the control register access */
82	ioread16(regio + 1);
83	ioread16(regio + 1);
84	iowrite8(3, regio + 2);
85}
86
87/**
88 *	optidma_lock		-	issue temporary relock
89 *	@ap: ATA port
90 *
91 *	Re-lock the configuration register settings.
92 */
93
94static void optidma_lock(struct ata_port *ap)
95{
96	void __iomem *regio = ap->ioaddr.cmd_addr;
97
98	/* Relock */
99	iowrite8(0x83, regio + 2);
100}
101
102/**
103 *	optidma_mode_setup	-	set mode data
104 *	@ap: ATA interface
105 *	@adev: ATA device
106 *	@mode: Mode to set
107 *
108 *	Called to do the DMA or PIO mode setup. Timing numbers are all
109 *	pre computed to keep the code clean. There are two tables depending
110 *	on the hardware clock speed.
111 *
112 *	WARNING: While we do this the IDE registers vanish. If we take an
113 *	IRQ here we depend on the host set locking to avoid catastrophe.
114 */
115
116static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
117{
118	struct ata_device *pair = ata_dev_pair(adev);
119	int pio = adev->pio_mode - XFER_PIO_0;
120	int dma = adev->dma_mode - XFER_MW_DMA_0;
121	void __iomem *regio = ap->ioaddr.cmd_addr;
122	u8 addr;
123
124	/* Address table precomputed with a DCLK of 2 */
125	static const u8 addr_timing[2][5] = {
126		{ 0x30, 0x20, 0x20, 0x10, 0x10 },
127		{ 0x20, 0x20, 0x10, 0x10, 0x10 }
128	};
129	static const u8 data_rec_timing[2][5] = {
130		{ 0x59, 0x46, 0x30, 0x20, 0x20 },
131		{ 0x46, 0x32, 0x20, 0x20, 0x10 }
132	};
133	static const u8 dma_data_rec_timing[2][3] = {
134		{ 0x76, 0x20, 0x20 },
135		{ 0x54, 0x20, 0x10 }
136	};
137
138	/* Switch from IDE to control mode */
139	optidma_unlock(ap);
140
141
142	/*
143 	 *	As with many controllers the address setup time is shared
144 	 *	and must suit both devices if present. FIXME: Check if we
145 	 *	need to look at slowest of PIO/DMA mode of either device
146	 */
147
148	if (mode >= XFER_MW_DMA_0)
149		addr = 0;
150	else
151		addr = addr_timing[pci_clock][pio];
152
153	if (pair) {
154		u8 pair_addr;
155		/* Hardware constraint */
156		if (ata_dma_enabled(pair))
157			pair_addr = 0;
158		else
159			pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
160		if (pair_addr > addr)
161			addr = pair_addr;
162	}
163
164	/* Commence primary programming sequence */
165	/* First we load the device number into the timing select */
166	iowrite8(adev->devno, regio + MISC_REG);
167	/* Now we load the data timings into read data/write data */
168	if (mode < XFER_MW_DMA_0) {
169		iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
170		iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
171	} else if (mode < XFER_UDMA_0) {
172		iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
173		iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
174	}
175	/* Finally we load the address setup into the misc register */
176	iowrite8(addr | adev->devno, regio + MISC_REG);
177
178	/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
179	iowrite8(0x85, regio + CNTRL_REG);
180
181	/* Switch back to IDE mode */
182	optidma_lock(ap);
183
184	/* Note: at this point our programming is incomplete. We are
185	   not supposed to program PCI 0x43 "things we hacked onto the chip"
186	   until we've done both sets of PIO/DMA timings */
187}
188
189/**
190 *	optiplus_mode_setup	-	DMA setup for Firestar Plus
191 *	@ap: ATA port
192 *	@adev: device
193 *	@mode: desired mode
194 *
195 *	The Firestar plus has additional UDMA functionality for UDMA0-2 and
196 *	requires we do some additional work. Because the base work we must do
197 *	is mostly shared we wrap the Firestar setup functionality in this
198 *	one
199 */
200
201static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
202{
203	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
204	u8 udcfg;
205	u8 udslave;
206	int dev2 = 2 * adev->devno;
207	int unit = 2 * ap->port_no + adev->devno;
208	int udma = mode - XFER_UDMA_0;
209
210	pci_read_config_byte(pdev, 0x44, &udcfg);
211	if (mode <= XFER_UDMA_0) {
212		udcfg &= ~(1 << unit);
213		optidma_mode_setup(ap, adev, adev->dma_mode);
214	} else {
215		udcfg |=  (1 << unit);
216		if (ap->port_no) {
217			pci_read_config_byte(pdev, 0x45, &udslave);
218			udslave &= ~(0x03 << dev2);
219			udslave |= (udma << dev2);
220			pci_write_config_byte(pdev, 0x45, udslave);
221		} else {
222			udcfg &= ~(0x30 << dev2);
223			udcfg |= (udma << dev2);
224		}
225	}
226	pci_write_config_byte(pdev, 0x44, udcfg);
227}
228
229/**
230 *	optidma_set_pio_mode	-	PIO setup callback
231 *	@ap: ATA port
232 *	@adev: Device
233 *
234 *	The libata core provides separate functions for handling PIO and
235 *	DMA programming. The architecture of the Firestar makes it easier
236 *	for us to have a common function so we provide wrappers
237 */
238
239static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
240{
241	optidma_mode_setup(ap, adev, adev->pio_mode);
242}
243
244/**
245 *	optidma_set_dma_mode	-	DMA setup callback
246 *	@ap: ATA port
247 *	@adev: Device
248 *
249 *	The libata core provides separate functions for handling PIO and
250 *	DMA programming. The architecture of the Firestar makes it easier
251 *	for us to have a common function so we provide wrappers
252 */
253
254static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
255{
256	optidma_mode_setup(ap, adev, adev->dma_mode);
257}
258
259/**
260 *	optiplus_set_pio_mode	-	PIO setup callback
261 *	@ap: ATA port
262 *	@adev: Device
263 *
264 *	The libata core provides separate functions for handling PIO and
265 *	DMA programming. The architecture of the Firestar makes it easier
266 *	for us to have a common function so we provide wrappers
267 */
268
269static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
270{
271	optiplus_mode_setup(ap, adev, adev->pio_mode);
272}
273
274/**
275 *	optiplus_set_dma_mode	-	DMA setup callback
276 *	@ap: ATA port
277 *	@adev: Device
278 *
279 *	The libata core provides separate functions for handling PIO and
280 *	DMA programming. The architecture of the Firestar makes it easier
281 *	for us to have a common function so we provide wrappers
282 */
283
284static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
285{
286	optiplus_mode_setup(ap, adev, adev->dma_mode);
287}
288
289/**
290 *	optidma_make_bits43	-	PCI setup helper
291 *	@adev: ATA device
292 *
293 *	Turn the ATA device setup into PCI configuration bits
294 *	for register 0x43 and return the two bits needed.
295 */
296
297static u8 optidma_make_bits43(struct ata_device *adev)
298{
299	static const u8 bits43[5] = {
300		0, 0, 0, 1, 2
301	};
302	if (!ata_dev_enabled(adev))
303		return 0;
304	if (ata_dma_enabled(adev))
305		return adev->dma_mode - XFER_MW_DMA_0;
306	return bits43[adev->pio_mode - XFER_PIO_0];
307}
308
309/**
310 *	optidma_set_mode	-	mode setup
311 *	@link: link to set up
312 *	@r_failed: out parameter for failed device
313 *
314 *	Use the standard setup to tune the chipset and then finalise the
315 *	configuration by writing the nibble of extra bits of data into
316 *	the chip.
317 */
318
319static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
320{
321	struct ata_port *ap = link->ap;
322	u8 r;
323	int nybble = 4 * ap->port_no;
324	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
325	int rc  = ata_do_set_mode(link, r_failed);
326	if (rc == 0) {
327		pci_read_config_byte(pdev, 0x43, &r);
328
329		r &= (0x0F << nybble);
330		r |= (optidma_make_bits43(&link->device[0]) +
331		     (optidma_make_bits43(&link->device[0]) << 2)) << nybble;
332		pci_write_config_byte(pdev, 0x43, r);
333	}
334	return rc;
335}
336
337static const struct scsi_host_template optidma_sht = {
338	ATA_BMDMA_SHT(DRV_NAME),
339};
340
341static struct ata_port_operations optidma_port_ops = {
342	.inherits	= &ata_bmdma_port_ops,
343	.cable_detect	= ata_cable_40wire,
344	.set_piomode	= optidma_set_pio_mode,
345	.set_dmamode	= optidma_set_dma_mode,
346	.set_mode	= optidma_set_mode,
347	.prereset	= optidma_pre_reset,
348};
349
350static struct ata_port_operations optiplus_port_ops = {
351	.inherits	= &optidma_port_ops,
352	.set_piomode	= optiplus_set_pio_mode,
353	.set_dmamode	= optiplus_set_dma_mode,
354};
355
356/**
357 *	optiplus_with_udma	-	Look for UDMA capable setup
358 *	@pdev: ATA controller
359 */
360
361static int optiplus_with_udma(struct pci_dev *pdev)
362{
363	u8 r;
364	int ret = 0;
365	int ioport = 0x22;
366	struct pci_dev *dev1;
367
368	/* Find function 1 */
369	dev1 = pci_get_device(0x1045, 0xC701, NULL);
370	if (dev1 == NULL)
371		return 0;
372
373	/* Rev must be >= 0x10 */
374	pci_read_config_byte(dev1, 0x08, &r);
375	if (r < 0x10)
376		goto done_nomsg;
377	/* Read the chipset system configuration to check our mode */
378	pci_read_config_byte(dev1, 0x5F, &r);
379	ioport |= (r << 8);
380	outb(0x10, ioport);
381	/* Must be 66Mhz sync */
382	if ((inb(ioport + 2) & 1) == 0)
383		goto done;
384
385	/* Check the ATA arbitration/timing is suitable */
386	pci_read_config_byte(pdev, 0x42, &r);
387	if ((r & 0x36) != 0x36)
388		goto done;
389	pci_read_config_byte(dev1, 0x52, &r);
390	if (r & 0x80)	/* IDEDIR disabled */
391		ret = 1;
392done:
393	printk(KERN_WARNING "UDMA not supported in this configuration.\n");
394done_nomsg:		/* Wrong chip revision */
395	pci_dev_put(dev1);
396	return ret;
397}
398
399static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
400{
401	static const struct ata_port_info info_82c700 = {
402		.flags = ATA_FLAG_SLAVE_POSS,
403		.pio_mask = ATA_PIO4,
404		.mwdma_mask = ATA_MWDMA2,
405		.port_ops = &optidma_port_ops
406	};
407	static const struct ata_port_info info_82c700_udma = {
408		.flags = ATA_FLAG_SLAVE_POSS,
409		.pio_mask = ATA_PIO4,
410		.mwdma_mask = ATA_MWDMA2,
411		.udma_mask = ATA_UDMA2,
412		.port_ops = &optiplus_port_ops
413	};
414	const struct ata_port_info *ppi[] = { &info_82c700, NULL };
415	int rc;
416
417	ata_print_version_once(&dev->dev, DRV_VERSION);
418
419	rc = pcim_enable_device(dev);
420	if (rc)
421		return rc;
422
423	/* Fixed location chipset magic */
424	inw(0x1F1);
425	inw(0x1F1);
426	pci_clock = inb(0x1F5) & 1;		/* 0 = 33Mhz, 1 = 25Mhz */
427
428	if (optiplus_with_udma(dev))
429		ppi[0] = &info_82c700_udma;
430
431	return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0);
432}
433
434static const struct pci_device_id optidma[] = {
435	{ PCI_VDEVICE(OPTI, 0xD568), },		/* Opti 82C700 */
436
437	{ },
438};
439
440static struct pci_driver optidma_pci_driver = {
441	.name 		= DRV_NAME,
442	.id_table	= optidma,
443	.probe 		= optidma_init_one,
444	.remove		= ata_pci_remove_one,
445#ifdef CONFIG_PM_SLEEP
446	.suspend	= ata_pci_device_suspend,
447	.resume		= ata_pci_device_resume,
448#endif
449};
450
451module_pci_driver(optidma_pci_driver);
452
453MODULE_AUTHOR("Alan Cox");
454MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
455MODULE_LICENSE("GPL");
456MODULE_DEVICE_TABLE(pci, optidma);
457MODULE_VERSION(DRV_VERSION);
458