1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 **       DO NOT EDIT BELOW        **
11 ************************************/
12
13#ifndef ASIC_REG_TPC4_CMDQ_REGS_H_
14#define ASIC_REG_TPC4_CMDQ_REGS_H_
15
16/*
17 *****************************************
18 *   TPC4_CMDQ (Prototype: CMDQ)
19 *****************************************
20 */
21
22#define mmTPC4_CMDQ_GLBL_CFG0                                        0xF09000
23
24#define mmTPC4_CMDQ_GLBL_CFG1                                        0xF09004
25
26#define mmTPC4_CMDQ_GLBL_PROT                                        0xF09008
27
28#define mmTPC4_CMDQ_GLBL_ERR_CFG                                     0xF0900C
29
30#define mmTPC4_CMDQ_GLBL_ERR_ADDR_LO                                 0xF09010
31
32#define mmTPC4_CMDQ_GLBL_ERR_ADDR_HI                                 0xF09014
33
34#define mmTPC4_CMDQ_GLBL_ERR_WDATA                                   0xF09018
35
36#define mmTPC4_CMDQ_GLBL_SECURE_PROPS                                0xF0901C
37
38#define mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS                            0xF09020
39
40#define mmTPC4_CMDQ_GLBL_STS0                                        0xF09024
41
42#define mmTPC4_CMDQ_GLBL_STS1                                        0xF09028
43
44#define mmTPC4_CMDQ_CQ_CFG0                                          0xF090B0
45
46#define mmTPC4_CMDQ_CQ_CFG1                                          0xF090B4
47
48#define mmTPC4_CMDQ_CQ_ARUSER                                        0xF090B8
49
50#define mmTPC4_CMDQ_CQ_PTR_LO                                        0xF090C0
51
52#define mmTPC4_CMDQ_CQ_PTR_HI                                        0xF090C4
53
54#define mmTPC4_CMDQ_CQ_TSIZE                                         0xF090C8
55
56#define mmTPC4_CMDQ_CQ_CTL                                           0xF090CC
57
58#define mmTPC4_CMDQ_CQ_PTR_LO_STS                                    0xF090D4
59
60#define mmTPC4_CMDQ_CQ_PTR_HI_STS                                    0xF090D8
61
62#define mmTPC4_CMDQ_CQ_TSIZE_STS                                     0xF090DC
63
64#define mmTPC4_CMDQ_CQ_CTL_STS                                       0xF090E0
65
66#define mmTPC4_CMDQ_CQ_STS0                                          0xF090E4
67
68#define mmTPC4_CMDQ_CQ_STS1                                          0xF090E8
69
70#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN                                0xF090F0
71
72#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                         0xF090F4
73
74#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT                               0xF090F8
75
76#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT                              0xF090FC
77
78#define mmTPC4_CMDQ_CQ_IFIFO_CNT                                     0xF09108
79
80#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO                             0xF09120
81
82#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI                             0xF09124
83
84#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO                             0xF09128
85
86#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI                             0xF0912C
87
88#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO                             0xF09130
89
90#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI                             0xF09134
91
92#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO                             0xF09138
93
94#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI                             0xF0913C
95
96#define mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET                             0xF09140
97
98#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                       0xF09144
99
100#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                       0xF09148
101
102#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                       0xF0914C
103
104#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET                       0xF09150
105
106#define mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET                            0xF09154
107
108#define mmTPC4_CMDQ_CP_FENCE0_RDATA                                  0xF09158
109
110#define mmTPC4_CMDQ_CP_FENCE1_RDATA                                  0xF0915C
111
112#define mmTPC4_CMDQ_CP_FENCE2_RDATA                                  0xF09160
113
114#define mmTPC4_CMDQ_CP_FENCE3_RDATA                                  0xF09164
115
116#define mmTPC4_CMDQ_CP_FENCE0_CNT                                    0xF09168
117
118#define mmTPC4_CMDQ_CP_FENCE1_CNT                                    0xF0916C
119
120#define mmTPC4_CMDQ_CP_FENCE2_CNT                                    0xF09170
121
122#define mmTPC4_CMDQ_CP_FENCE3_CNT                                    0xF09174
123
124#define mmTPC4_CMDQ_CP_STS                                           0xF09178
125
126#define mmTPC4_CMDQ_CP_CURRENT_INST_LO                               0xF0917C
127
128#define mmTPC4_CMDQ_CP_CURRENT_INST_HI                               0xF09180
129
130#define mmTPC4_CMDQ_CP_BARRIER_CFG                                   0xF09184
131
132#define mmTPC4_CMDQ_CP_DBG_0                                         0xF09188
133
134#define mmTPC4_CMDQ_CQ_BUF_ADDR                                      0xF09308
135
136#define mmTPC4_CMDQ_CQ_BUF_RDATA                                     0xF0930C
137
138#endif /* ASIC_REG_TPC4_CMDQ_REGS_H_ */
139