1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ 14#define ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ 15 16/* 17 ***************************************** 18 * SRAM_Y0_X2_RTR (Prototype: IC_RTR) 19 ***************************************** 20 */ 21 22#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_E_ARB 0x209100 23 24#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_W_ARB 0x209104 25 26#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB 0x209110 27 28#define mmSRAM_Y0_X2_RTR_HBW_E_ARB_MAX 0x209120 29 30#define mmSRAM_Y0_X2_RTR_HBW_W_ARB_MAX 0x209124 31 32#define mmSRAM_Y0_X2_RTR_HBW_L_ARB_MAX 0x209130 33 34#define mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB 0x209140 35 36#define mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB 0x209144 37 38#define mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB 0x209148 39 40#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB 0x209160 41 42#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB 0x209164 43 44#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_L_ARB 0x209168 45 46#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_E_ARB 0x209200 47 48#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_W_ARB 0x209204 49 50#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_L_ARB 0x209210 51 52#define mmSRAM_Y0_X2_RTR_LBW_E_ARB_MAX 0x209220 53 54#define mmSRAM_Y0_X2_RTR_LBW_W_ARB_MAX 0x209224 55 56#define mmSRAM_Y0_X2_RTR_LBW_L_ARB_MAX 0x209230 57 58#define mmSRAM_Y0_X2_RTR_LBW_DATA_E_ARB 0x209240 59 60#define mmSRAM_Y0_X2_RTR_LBW_DATA_W_ARB 0x209244 61 62#define mmSRAM_Y0_X2_RTR_LBW_DATA_L_ARB 0x209248 63 64#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_E_ARB 0x209260 65 66#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_W_ARB 0x209264 67 68#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_L_ARB 0x209268 69 70#define mmSRAM_Y0_X2_RTR_DBG_E_ARB 0x209300 71 72#define mmSRAM_Y0_X2_RTR_DBG_W_ARB 0x209304 73 74#define mmSRAM_Y0_X2_RTR_DBG_L_ARB 0x209310 75 76#define mmSRAM_Y0_X2_RTR_DBG_E_ARB_MAX 0x209320 77 78#define mmSRAM_Y0_X2_RTR_DBG_W_ARB_MAX 0x209324 79 80#define mmSRAM_Y0_X2_RTR_DBG_L_ARB_MAX 0x209330 81 82#endif /* ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ */ 83