1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 **       DO NOT EDIT BELOW        **
11 ************************************/
12
13#ifndef ASIC_REG_CPU_PLL_REGS_H_
14#define ASIC_REG_CPU_PLL_REGS_H_
15
16/*
17 *****************************************
18 *   CPU_PLL (Prototype: PLL)
19 *****************************************
20 */
21
22#define mmCPU_PLL_NR                                                 0x4A2100
23
24#define mmCPU_PLL_NF                                                 0x4A2104
25
26#define mmCPU_PLL_OD                                                 0x4A2108
27
28#define mmCPU_PLL_NB                                                 0x4A210C
29
30#define mmCPU_PLL_CFG                                                0x4A2110
31
32#define mmCPU_PLL_LOSE_MASK                                          0x4A2120
33
34#define mmCPU_PLL_LOCK_INTR                                          0x4A2128
35
36#define mmCPU_PLL_LOCK_BYPASS                                        0x4A212C
37
38#define mmCPU_PLL_DATA_CHNG                                          0x4A2130
39
40#define mmCPU_PLL_RST                                                0x4A2134
41
42#define mmCPU_PLL_SLIP_WD_CNTR                                       0x4A2150
43
44#define mmCPU_PLL_DIV_FACTOR_0                                       0x4A2200
45
46#define mmCPU_PLL_DIV_FACTOR_1                                       0x4A2204
47
48#define mmCPU_PLL_DIV_FACTOR_2                                       0x4A2208
49
50#define mmCPU_PLL_DIV_FACTOR_3                                       0x4A220C
51
52#define mmCPU_PLL_DIV_FACTOR_CMD_0                                   0x4A2220
53
54#define mmCPU_PLL_DIV_FACTOR_CMD_1                                   0x4A2224
55
56#define mmCPU_PLL_DIV_FACTOR_CMD_2                                   0x4A2228
57
58#define mmCPU_PLL_DIV_FACTOR_CMD_3                                   0x4A222C
59
60#define mmCPU_PLL_DIV_SEL_0                                          0x4A2280
61
62#define mmCPU_PLL_DIV_SEL_1                                          0x4A2284
63
64#define mmCPU_PLL_DIV_SEL_2                                          0x4A2288
65
66#define mmCPU_PLL_DIV_SEL_3                                          0x4A228C
67
68#define mmCPU_PLL_DIV_EN_0                                           0x4A22A0
69
70#define mmCPU_PLL_DIV_EN_1                                           0x4A22A4
71
72#define mmCPU_PLL_DIV_EN_2                                           0x4A22A8
73
74#define mmCPU_PLL_DIV_EN_3                                           0x4A22AC
75
76#define mmCPU_PLL_DIV_FACTOR_BUSY_0                                  0x4A22C0
77
78#define mmCPU_PLL_DIV_FACTOR_BUSY_1                                  0x4A22C4
79
80#define mmCPU_PLL_DIV_FACTOR_BUSY_2                                  0x4A22C8
81
82#define mmCPU_PLL_DIV_FACTOR_BUSY_3                                  0x4A22CC
83
84#define mmCPU_PLL_CLK_GATER                                          0x4A2300
85
86#define mmCPU_PLL_CLK_RLX_0                                          0x4A2310
87
88#define mmCPU_PLL_CLK_RLX_1                                          0x4A2314
89
90#define mmCPU_PLL_CLK_RLX_2                                          0x4A2318
91
92#define mmCPU_PLL_CLK_RLX_3                                          0x4A231C
93
94#define mmCPU_PLL_REF_CNTR_PERIOD                                    0x4A2400
95
96#define mmCPU_PLL_REF_LOW_THRESHOLD                                  0x4A2410
97
98#define mmCPU_PLL_REF_HIGH_THRESHOLD                                 0x4A2420
99
100#define mmCPU_PLL_PLL_NOT_STABLE                                     0x4A2430
101
102#define mmCPU_PLL_FREQ_CALC_EN                                       0x4A2440
103
104#endif /* ASIC_REG_CPU_PLL_REGS_H_ */
105