1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2020 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 **       DO NOT EDIT BELOW        **
11 ************************************/
12
13#ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_
14#define ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_
15
16/*
17 *****************************************
18 *   DCORE0_EDMA0_CORE_CTX
19 *   (Prototype: DMA_CORE_CTX)
20 *****************************************
21 */
22
23#define mmDCORE0_EDMA0_CORE_CTX_RATE_LIM_TKN 0x41CB860
24
25#define mmDCORE0_EDMA0_CORE_CTX_PWRLP 0x41CB864
26
27#define mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS 0x41CB868
28
29#define mmDCORE0_EDMA0_CORE_CTX_IDX 0x41CB86C
30
31#define mmDCORE0_EDMA0_CORE_CTX_IDX_INC 0x41CB870
32
33#define mmDCORE0_EDMA0_CORE_CTX_CTRL 0x41CB874
34
35#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0 0x41CB878
36
37#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1 0x41CB87C
38
39#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1 0x41CB880
40
41#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2 0x41CB884
42
43#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2 0x41CB888
44
45#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3 0x41CB88C
46
47#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3 0x41CB890
48
49#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4 0x41CB894
50
51#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4 0x41CB898
52
53#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1 0x41CB89C
54
55#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1 0x41CB8A0
56
57#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2 0x41CB8A4
58
59#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2 0x41CB8A8
60
61#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3 0x41CB8AC
62
63#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3 0x41CB8B0
64
65#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4 0x41CB8B4
66
67#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4 0x41CB8B8
68
69#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x41CB8BC
70
71#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x41CB8C0
72
73#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA 0x41CB8C4
74
75#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO 0x41CB8C8
76
77#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI 0x41CB8CC
78
79#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO 0x41CB8D0
80
81#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI 0x41CB8D4
82
83#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO 0x41CB8D8
84
85#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI 0x41CB8DC
86
87#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO 0x41CB8E0
88
89#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI 0x41CB8E4
90
91#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0 0x41CB8E8
92
93#define mmDCORE0_EDMA0_CORE_CTX_COMMIT 0x41CB8EC
94
95#endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ */
96