1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_NIC3_QM1_REGS_H_ 14#define ASIC_REG_NIC3_QM1_REGS_H_ 15 16/* 17 ***************************************** 18 * NIC3_QM1 (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmNIC3_QM1_GLBL_CFG0 0xDA2000 23 24#define mmNIC3_QM1_GLBL_CFG1 0xDA2004 25 26#define mmNIC3_QM1_GLBL_PROT 0xDA2008 27 28#define mmNIC3_QM1_GLBL_ERR_CFG 0xDA200C 29 30#define mmNIC3_QM1_GLBL_SECURE_PROPS_0 0xDA2010 31 32#define mmNIC3_QM1_GLBL_SECURE_PROPS_1 0xDA2014 33 34#define mmNIC3_QM1_GLBL_SECURE_PROPS_2 0xDA2018 35 36#define mmNIC3_QM1_GLBL_SECURE_PROPS_3 0xDA201C 37 38#define mmNIC3_QM1_GLBL_SECURE_PROPS_4 0xDA2020 39 40#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_0 0xDA2024 41 42#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_1 0xDA2028 43 44#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_2 0xDA202C 45 46#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_3 0xDA2030 47 48#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_4 0xDA2034 49 50#define mmNIC3_QM1_GLBL_STS0 0xDA2038 51 52#define mmNIC3_QM1_GLBL_STS1_0 0xDA2040 53 54#define mmNIC3_QM1_GLBL_STS1_1 0xDA2044 55 56#define mmNIC3_QM1_GLBL_STS1_2 0xDA2048 57 58#define mmNIC3_QM1_GLBL_STS1_3 0xDA204C 59 60#define mmNIC3_QM1_GLBL_STS1_4 0xDA2050 61 62#define mmNIC3_QM1_GLBL_MSG_EN_0 0xDA2054 63 64#define mmNIC3_QM1_GLBL_MSG_EN_1 0xDA2058 65 66#define mmNIC3_QM1_GLBL_MSG_EN_2 0xDA205C 67 68#define mmNIC3_QM1_GLBL_MSG_EN_3 0xDA2060 69 70#define mmNIC3_QM1_GLBL_MSG_EN_4 0xDA2068 71 72#define mmNIC3_QM1_PQ_BASE_LO_0 0xDA2070 73 74#define mmNIC3_QM1_PQ_BASE_LO_1 0xDA2074 75 76#define mmNIC3_QM1_PQ_BASE_LO_2 0xDA2078 77 78#define mmNIC3_QM1_PQ_BASE_LO_3 0xDA207C 79 80#define mmNIC3_QM1_PQ_BASE_HI_0 0xDA2080 81 82#define mmNIC3_QM1_PQ_BASE_HI_1 0xDA2084 83 84#define mmNIC3_QM1_PQ_BASE_HI_2 0xDA2088 85 86#define mmNIC3_QM1_PQ_BASE_HI_3 0xDA208C 87 88#define mmNIC3_QM1_PQ_SIZE_0 0xDA2090 89 90#define mmNIC3_QM1_PQ_SIZE_1 0xDA2094 91 92#define mmNIC3_QM1_PQ_SIZE_2 0xDA2098 93 94#define mmNIC3_QM1_PQ_SIZE_3 0xDA209C 95 96#define mmNIC3_QM1_PQ_PI_0 0xDA20A0 97 98#define mmNIC3_QM1_PQ_PI_1 0xDA20A4 99 100#define mmNIC3_QM1_PQ_PI_2 0xDA20A8 101 102#define mmNIC3_QM1_PQ_PI_3 0xDA20AC 103 104#define mmNIC3_QM1_PQ_CI_0 0xDA20B0 105 106#define mmNIC3_QM1_PQ_CI_1 0xDA20B4 107 108#define mmNIC3_QM1_PQ_CI_2 0xDA20B8 109 110#define mmNIC3_QM1_PQ_CI_3 0xDA20BC 111 112#define mmNIC3_QM1_PQ_CFG0_0 0xDA20C0 113 114#define mmNIC3_QM1_PQ_CFG0_1 0xDA20C4 115 116#define mmNIC3_QM1_PQ_CFG0_2 0xDA20C8 117 118#define mmNIC3_QM1_PQ_CFG0_3 0xDA20CC 119 120#define mmNIC3_QM1_PQ_CFG1_0 0xDA20D0 121 122#define mmNIC3_QM1_PQ_CFG1_1 0xDA20D4 123 124#define mmNIC3_QM1_PQ_CFG1_2 0xDA20D8 125 126#define mmNIC3_QM1_PQ_CFG1_3 0xDA20DC 127 128#define mmNIC3_QM1_PQ_ARUSER_31_11_0 0xDA20E0 129 130#define mmNIC3_QM1_PQ_ARUSER_31_11_1 0xDA20E4 131 132#define mmNIC3_QM1_PQ_ARUSER_31_11_2 0xDA20E8 133 134#define mmNIC3_QM1_PQ_ARUSER_31_11_3 0xDA20EC 135 136#define mmNIC3_QM1_PQ_STS0_0 0xDA20F0 137 138#define mmNIC3_QM1_PQ_STS0_1 0xDA20F4 139 140#define mmNIC3_QM1_PQ_STS0_2 0xDA20F8 141 142#define mmNIC3_QM1_PQ_STS0_3 0xDA20FC 143 144#define mmNIC3_QM1_PQ_STS1_0 0xDA2100 145 146#define mmNIC3_QM1_PQ_STS1_1 0xDA2104 147 148#define mmNIC3_QM1_PQ_STS1_2 0xDA2108 149 150#define mmNIC3_QM1_PQ_STS1_3 0xDA210C 151 152#define mmNIC3_QM1_CQ_CFG0_0 0xDA2110 153 154#define mmNIC3_QM1_CQ_CFG0_1 0xDA2114 155 156#define mmNIC3_QM1_CQ_CFG0_2 0xDA2118 157 158#define mmNIC3_QM1_CQ_CFG0_3 0xDA211C 159 160#define mmNIC3_QM1_CQ_CFG0_4 0xDA2120 161 162#define mmNIC3_QM1_CQ_CFG1_0 0xDA2124 163 164#define mmNIC3_QM1_CQ_CFG1_1 0xDA2128 165 166#define mmNIC3_QM1_CQ_CFG1_2 0xDA212C 167 168#define mmNIC3_QM1_CQ_CFG1_3 0xDA2130 169 170#define mmNIC3_QM1_CQ_CFG1_4 0xDA2134 171 172#define mmNIC3_QM1_CQ_ARUSER_31_11_0 0xDA2138 173 174#define mmNIC3_QM1_CQ_ARUSER_31_11_1 0xDA213C 175 176#define mmNIC3_QM1_CQ_ARUSER_31_11_2 0xDA2140 177 178#define mmNIC3_QM1_CQ_ARUSER_31_11_3 0xDA2144 179 180#define mmNIC3_QM1_CQ_ARUSER_31_11_4 0xDA2148 181 182#define mmNIC3_QM1_CQ_STS0_0 0xDA214C 183 184#define mmNIC3_QM1_CQ_STS0_1 0xDA2150 185 186#define mmNIC3_QM1_CQ_STS0_2 0xDA2154 187 188#define mmNIC3_QM1_CQ_STS0_3 0xDA2158 189 190#define mmNIC3_QM1_CQ_STS0_4 0xDA215C 191 192#define mmNIC3_QM1_CQ_STS1_0 0xDA2160 193 194#define mmNIC3_QM1_CQ_STS1_1 0xDA2164 195 196#define mmNIC3_QM1_CQ_STS1_2 0xDA2168 197 198#define mmNIC3_QM1_CQ_STS1_3 0xDA216C 199 200#define mmNIC3_QM1_CQ_STS1_4 0xDA2170 201 202#define mmNIC3_QM1_CQ_PTR_LO_0 0xDA2174 203 204#define mmNIC3_QM1_CQ_PTR_HI_0 0xDA2178 205 206#define mmNIC3_QM1_CQ_TSIZE_0 0xDA217C 207 208#define mmNIC3_QM1_CQ_CTL_0 0xDA2180 209 210#define mmNIC3_QM1_CQ_PTR_LO_1 0xDA2184 211 212#define mmNIC3_QM1_CQ_PTR_HI_1 0xDA2188 213 214#define mmNIC3_QM1_CQ_TSIZE_1 0xDA218C 215 216#define mmNIC3_QM1_CQ_CTL_1 0xDA2190 217 218#define mmNIC3_QM1_CQ_PTR_LO_2 0xDA2194 219 220#define mmNIC3_QM1_CQ_PTR_HI_2 0xDA2198 221 222#define mmNIC3_QM1_CQ_TSIZE_2 0xDA219C 223 224#define mmNIC3_QM1_CQ_CTL_2 0xDA21A0 225 226#define mmNIC3_QM1_CQ_PTR_LO_3 0xDA21A4 227 228#define mmNIC3_QM1_CQ_PTR_HI_3 0xDA21A8 229 230#define mmNIC3_QM1_CQ_TSIZE_3 0xDA21AC 231 232#define mmNIC3_QM1_CQ_CTL_3 0xDA21B0 233 234#define mmNIC3_QM1_CQ_PTR_LO_4 0xDA21B4 235 236#define mmNIC3_QM1_CQ_PTR_HI_4 0xDA21B8 237 238#define mmNIC3_QM1_CQ_TSIZE_4 0xDA21BC 239 240#define mmNIC3_QM1_CQ_CTL_4 0xDA21C0 241 242#define mmNIC3_QM1_CQ_PTR_LO_STS_0 0xDA21C4 243 244#define mmNIC3_QM1_CQ_PTR_LO_STS_1 0xDA21C8 245 246#define mmNIC3_QM1_CQ_PTR_LO_STS_2 0xDA21CC 247 248#define mmNIC3_QM1_CQ_PTR_LO_STS_3 0xDA21D0 249 250#define mmNIC3_QM1_CQ_PTR_LO_STS_4 0xDA21D4 251 252#define mmNIC3_QM1_CQ_PTR_HI_STS_0 0xDA21D8 253 254#define mmNIC3_QM1_CQ_PTR_HI_STS_1 0xDA21DC 255 256#define mmNIC3_QM1_CQ_PTR_HI_STS_2 0xDA21E0 257 258#define mmNIC3_QM1_CQ_PTR_HI_STS_3 0xDA21E4 259 260#define mmNIC3_QM1_CQ_PTR_HI_STS_4 0xDA21E8 261 262#define mmNIC3_QM1_CQ_TSIZE_STS_0 0xDA21EC 263 264#define mmNIC3_QM1_CQ_TSIZE_STS_1 0xDA21F0 265 266#define mmNIC3_QM1_CQ_TSIZE_STS_2 0xDA21F4 267 268#define mmNIC3_QM1_CQ_TSIZE_STS_3 0xDA21F8 269 270#define mmNIC3_QM1_CQ_TSIZE_STS_4 0xDA21FC 271 272#define mmNIC3_QM1_CQ_CTL_STS_0 0xDA2200 273 274#define mmNIC3_QM1_CQ_CTL_STS_1 0xDA2204 275 276#define mmNIC3_QM1_CQ_CTL_STS_2 0xDA2208 277 278#define mmNIC3_QM1_CQ_CTL_STS_3 0xDA220C 279 280#define mmNIC3_QM1_CQ_CTL_STS_4 0xDA2210 281 282#define mmNIC3_QM1_CQ_IFIFO_CNT_0 0xDA2214 283 284#define mmNIC3_QM1_CQ_IFIFO_CNT_1 0xDA2218 285 286#define mmNIC3_QM1_CQ_IFIFO_CNT_2 0xDA221C 287 288#define mmNIC3_QM1_CQ_IFIFO_CNT_3 0xDA2220 289 290#define mmNIC3_QM1_CQ_IFIFO_CNT_4 0xDA2224 291 292#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_0 0xDA2228 293 294#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_1 0xDA222C 295 296#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_2 0xDA2230 297 298#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_3 0xDA2234 299 300#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_4 0xDA2238 301 302#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_0 0xDA223C 303 304#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_1 0xDA2240 305 306#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_2 0xDA2244 307 308#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_3 0xDA2248 309 310#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_4 0xDA224C 311 312#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_0 0xDA2250 313 314#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_1 0xDA2254 315 316#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_2 0xDA2258 317 318#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_3 0xDA225C 319 320#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_4 0xDA2260 321 322#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_0 0xDA2264 323 324#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_1 0xDA2268 325 326#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_2 0xDA226C 327 328#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_3 0xDA2270 329 330#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_4 0xDA2274 331 332#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_0 0xDA2278 333 334#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_1 0xDA227C 335 336#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 0xDA2280 337 338#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_3 0xDA2284 339 340#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_4 0xDA2288 341 342#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_0 0xDA228C 343 344#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_1 0xDA2290 345 346#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_2 0xDA2294 347 348#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_3 0xDA2298 349 350#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_4 0xDA229C 351 352#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_0 0xDA22A0 353 354#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_1 0xDA22A4 355 356#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_2 0xDA22A8 357 358#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_3 0xDA22AC 359 360#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_4 0xDA22B0 361 362#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_0 0xDA22B4 363 364#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_1 0xDA22B8 365 366#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_2 0xDA22BC 367 368#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_3 0xDA22C0 369 370#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_4 0xDA22C4 371 372#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_0 0xDA22C8 373 374#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_1 0xDA22CC 375 376#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_2 0xDA22D0 377 378#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_3 0xDA22D4 379 380#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_4 0xDA22D8 381 382#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDA22E0 383 384#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDA22E4 385 386#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDA22E8 387 388#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDA22EC 389 390#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDA22F0 391 392#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDA22F4 393 394#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDA22F8 395 396#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDA22FC 397 398#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDA2300 399 400#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDA2304 401 402#define mmNIC3_QM1_CP_FENCE0_RDATA_0 0xDA2308 403 404#define mmNIC3_QM1_CP_FENCE0_RDATA_1 0xDA230C 405 406#define mmNIC3_QM1_CP_FENCE0_RDATA_2 0xDA2310 407 408#define mmNIC3_QM1_CP_FENCE0_RDATA_3 0xDA2314 409 410#define mmNIC3_QM1_CP_FENCE0_RDATA_4 0xDA2318 411 412#define mmNIC3_QM1_CP_FENCE1_RDATA_0 0xDA231C 413 414#define mmNIC3_QM1_CP_FENCE1_RDATA_1 0xDA2320 415 416#define mmNIC3_QM1_CP_FENCE1_RDATA_2 0xDA2324 417 418#define mmNIC3_QM1_CP_FENCE1_RDATA_3 0xDA2328 419 420#define mmNIC3_QM1_CP_FENCE1_RDATA_4 0xDA232C 421 422#define mmNIC3_QM1_CP_FENCE2_RDATA_0 0xDA2330 423 424#define mmNIC3_QM1_CP_FENCE2_RDATA_1 0xDA2334 425 426#define mmNIC3_QM1_CP_FENCE2_RDATA_2 0xDA2338 427 428#define mmNIC3_QM1_CP_FENCE2_RDATA_3 0xDA233C 429 430#define mmNIC3_QM1_CP_FENCE2_RDATA_4 0xDA2340 431 432#define mmNIC3_QM1_CP_FENCE3_RDATA_0 0xDA2344 433 434#define mmNIC3_QM1_CP_FENCE3_RDATA_1 0xDA2348 435 436#define mmNIC3_QM1_CP_FENCE3_RDATA_2 0xDA234C 437 438#define mmNIC3_QM1_CP_FENCE3_RDATA_3 0xDA2350 439 440#define mmNIC3_QM1_CP_FENCE3_RDATA_4 0xDA2354 441 442#define mmNIC3_QM1_CP_FENCE0_CNT_0 0xDA2358 443 444#define mmNIC3_QM1_CP_FENCE0_CNT_1 0xDA235C 445 446#define mmNIC3_QM1_CP_FENCE0_CNT_2 0xDA2360 447 448#define mmNIC3_QM1_CP_FENCE0_CNT_3 0xDA2364 449 450#define mmNIC3_QM1_CP_FENCE0_CNT_4 0xDA2368 451 452#define mmNIC3_QM1_CP_FENCE1_CNT_0 0xDA236C 453 454#define mmNIC3_QM1_CP_FENCE1_CNT_1 0xDA2370 455 456#define mmNIC3_QM1_CP_FENCE1_CNT_2 0xDA2374 457 458#define mmNIC3_QM1_CP_FENCE1_CNT_3 0xDA2378 459 460#define mmNIC3_QM1_CP_FENCE1_CNT_4 0xDA237C 461 462#define mmNIC3_QM1_CP_FENCE2_CNT_0 0xDA2380 463 464#define mmNIC3_QM1_CP_FENCE2_CNT_1 0xDA2384 465 466#define mmNIC3_QM1_CP_FENCE2_CNT_2 0xDA2388 467 468#define mmNIC3_QM1_CP_FENCE2_CNT_3 0xDA238C 469 470#define mmNIC3_QM1_CP_FENCE2_CNT_4 0xDA2390 471 472#define mmNIC3_QM1_CP_FENCE3_CNT_0 0xDA2394 473 474#define mmNIC3_QM1_CP_FENCE3_CNT_1 0xDA2398 475 476#define mmNIC3_QM1_CP_FENCE3_CNT_2 0xDA239C 477 478#define mmNIC3_QM1_CP_FENCE3_CNT_3 0xDA23A0 479 480#define mmNIC3_QM1_CP_FENCE3_CNT_4 0xDA23A4 481 482#define mmNIC3_QM1_CP_STS_0 0xDA23A8 483 484#define mmNIC3_QM1_CP_STS_1 0xDA23AC 485 486#define mmNIC3_QM1_CP_STS_2 0xDA23B0 487 488#define mmNIC3_QM1_CP_STS_3 0xDA23B4 489 490#define mmNIC3_QM1_CP_STS_4 0xDA23B8 491 492#define mmNIC3_QM1_CP_CURRENT_INST_LO_0 0xDA23BC 493 494#define mmNIC3_QM1_CP_CURRENT_INST_LO_1 0xDA23C0 495 496#define mmNIC3_QM1_CP_CURRENT_INST_LO_2 0xDA23C4 497 498#define mmNIC3_QM1_CP_CURRENT_INST_LO_3 0xDA23C8 499 500#define mmNIC3_QM1_CP_CURRENT_INST_LO_4 0xDA23CC 501 502#define mmNIC3_QM1_CP_CURRENT_INST_HI_0 0xDA23D0 503 504#define mmNIC3_QM1_CP_CURRENT_INST_HI_1 0xDA23D4 505 506#define mmNIC3_QM1_CP_CURRENT_INST_HI_2 0xDA23D8 507 508#define mmNIC3_QM1_CP_CURRENT_INST_HI_3 0xDA23DC 509 510#define mmNIC3_QM1_CP_CURRENT_INST_HI_4 0xDA23E0 511 512#define mmNIC3_QM1_CP_BARRIER_CFG_0 0xDA23F4 513 514#define mmNIC3_QM1_CP_BARRIER_CFG_1 0xDA23F8 515 516#define mmNIC3_QM1_CP_BARRIER_CFG_2 0xDA23FC 517 518#define mmNIC3_QM1_CP_BARRIER_CFG_3 0xDA2400 519 520#define mmNIC3_QM1_CP_BARRIER_CFG_4 0xDA2404 521 522#define mmNIC3_QM1_CP_DBG_0_0 0xDA2408 523 524#define mmNIC3_QM1_CP_DBG_0_1 0xDA240C 525 526#define mmNIC3_QM1_CP_DBG_0_2 0xDA2410 527 528#define mmNIC3_QM1_CP_DBG_0_3 0xDA2414 529 530#define mmNIC3_QM1_CP_DBG_0_4 0xDA2418 531 532#define mmNIC3_QM1_CP_ARUSER_31_11_0 0xDA241C 533 534#define mmNIC3_QM1_CP_ARUSER_31_11_1 0xDA2420 535 536#define mmNIC3_QM1_CP_ARUSER_31_11_2 0xDA2424 537 538#define mmNIC3_QM1_CP_ARUSER_31_11_3 0xDA2428 539 540#define mmNIC3_QM1_CP_ARUSER_31_11_4 0xDA242C 541 542#define mmNIC3_QM1_CP_AWUSER_31_11_0 0xDA2430 543 544#define mmNIC3_QM1_CP_AWUSER_31_11_1 0xDA2434 545 546#define mmNIC3_QM1_CP_AWUSER_31_11_2 0xDA2438 547 548#define mmNIC3_QM1_CP_AWUSER_31_11_3 0xDA243C 549 550#define mmNIC3_QM1_CP_AWUSER_31_11_4 0xDA2440 551 552#define mmNIC3_QM1_ARB_CFG_0 0xDA2A00 553 554#define mmNIC3_QM1_ARB_CHOISE_Q_PUSH 0xDA2A04 555 556#define mmNIC3_QM1_ARB_WRR_WEIGHT_0 0xDA2A08 557 558#define mmNIC3_QM1_ARB_WRR_WEIGHT_1 0xDA2A0C 559 560#define mmNIC3_QM1_ARB_WRR_WEIGHT_2 0xDA2A10 561 562#define mmNIC3_QM1_ARB_WRR_WEIGHT_3 0xDA2A14 563 564#define mmNIC3_QM1_ARB_CFG_1 0xDA2A18 565 566#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_0 0xDA2A20 567 568#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_1 0xDA2A24 569 570#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_2 0xDA2A28 571 572#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_3 0xDA2A2C 573 574#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_4 0xDA2A30 575 576#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_5 0xDA2A34 577 578#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_6 0xDA2A38 579 580#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_7 0xDA2A3C 581 582#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_8 0xDA2A40 583 584#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_9 0xDA2A44 585 586#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_10 0xDA2A48 587 588#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_11 0xDA2A4C 589 590#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_12 0xDA2A50 591 592#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_13 0xDA2A54 593 594#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_14 0xDA2A58 595 596#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_15 0xDA2A5C 597 598#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_16 0xDA2A60 599 600#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_17 0xDA2A64 601 602#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_18 0xDA2A68 603 604#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_19 0xDA2A6C 605 606#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_20 0xDA2A70 607 608#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_21 0xDA2A74 609 610#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_22 0xDA2A78 611 612#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_23 0xDA2A7C 613 614#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 0xDA2A80 615 616#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_25 0xDA2A84 617 618#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_26 0xDA2A88 619 620#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_27 0xDA2A8C 621 622#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_28 0xDA2A90 623 624#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_29 0xDA2A94 625 626#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_30 0xDA2A98 627 628#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_31 0xDA2A9C 629 630#define mmNIC3_QM1_ARB_MST_CRED_INC 0xDA2AA0 631 632#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xDA2AA4 633 634#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xDA2AA8 635 636#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xDA2AAC 637 638#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xDA2AB0 639 640#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xDA2AB4 641 642#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xDA2AB8 643 644#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xDA2ABC 645 646#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xDA2AC0 647 648#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xDA2AC4 649 650#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xDA2AC8 651 652#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xDA2ACC 653 654#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xDA2AD0 655 656#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xDA2AD4 657 658#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xDA2AD8 659 660#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xDA2ADC 661 662#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xDA2AE0 663 664#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xDA2AE4 665 666#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xDA2AE8 667 668#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xDA2AEC 669 670#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xDA2AF0 671 672#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xDA2AF4 673 674#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xDA2AF8 675 676#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xDA2AFC 677 678#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xDA2B00 679 680#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xDA2B04 681 682#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xDA2B08 683 684#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xDA2B0C 685 686#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xDA2B10 687 688#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xDA2B14 689 690#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xDA2B18 691 692#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xDA2B1C 693 694#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xDA2B20 695 696#define mmNIC3_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xDA2B28 697 698#define mmNIC3_QM1_ARB_MST_SLAVE_EN 0xDA2B2C 699 700#define mmNIC3_QM1_ARB_MST_QUIET_PER 0xDA2B34 701 702#define mmNIC3_QM1_ARB_SLV_CHOISE_WDT 0xDA2B38 703 704#define mmNIC3_QM1_ARB_SLV_ID 0xDA2B3C 705 706#define mmNIC3_QM1_ARB_MSG_MAX_INFLIGHT 0xDA2B44 707 708#define mmNIC3_QM1_ARB_MSG_AWUSER_31_11 0xDA2B48 709 710#define mmNIC3_QM1_ARB_MSG_AWUSER_SEC_PROP 0xDA2B4C 711 712#define mmNIC3_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xDA2B50 713 714#define mmNIC3_QM1_ARB_BASE_LO 0xDA2B54 715 716#define mmNIC3_QM1_ARB_BASE_HI 0xDA2B58 717 718#define mmNIC3_QM1_ARB_STATE_STS 0xDA2B80 719 720#define mmNIC3_QM1_ARB_CHOISE_FULLNESS_STS 0xDA2B84 721 722#define mmNIC3_QM1_ARB_MSG_STS 0xDA2B88 723 724#define mmNIC3_QM1_ARB_SLV_CHOISE_Q_HEAD 0xDA2B8C 725 726#define mmNIC3_QM1_ARB_ERR_CAUSE 0xDA2B9C 727 728#define mmNIC3_QM1_ARB_ERR_MSG_EN 0xDA2BA0 729 730#define mmNIC3_QM1_ARB_ERR_STS_DRP 0xDA2BA8 731 732#define mmNIC3_QM1_ARB_MST_CRED_STS_0 0xDA2BB0 733 734#define mmNIC3_QM1_ARB_MST_CRED_STS_1 0xDA2BB4 735 736#define mmNIC3_QM1_ARB_MST_CRED_STS_2 0xDA2BB8 737 738#define mmNIC3_QM1_ARB_MST_CRED_STS_3 0xDA2BBC 739 740#define mmNIC3_QM1_ARB_MST_CRED_STS_4 0xDA2BC0 741 742#define mmNIC3_QM1_ARB_MST_CRED_STS_5 0xDA2BC4 743 744#define mmNIC3_QM1_ARB_MST_CRED_STS_6 0xDA2BC8 745 746#define mmNIC3_QM1_ARB_MST_CRED_STS_7 0xDA2BCC 747 748#define mmNIC3_QM1_ARB_MST_CRED_STS_8 0xDA2BD0 749 750#define mmNIC3_QM1_ARB_MST_CRED_STS_9 0xDA2BD4 751 752#define mmNIC3_QM1_ARB_MST_CRED_STS_10 0xDA2BD8 753 754#define mmNIC3_QM1_ARB_MST_CRED_STS_11 0xDA2BDC 755 756#define mmNIC3_QM1_ARB_MST_CRED_STS_12 0xDA2BE0 757 758#define mmNIC3_QM1_ARB_MST_CRED_STS_13 0xDA2BE4 759 760#define mmNIC3_QM1_ARB_MST_CRED_STS_14 0xDA2BE8 761 762#define mmNIC3_QM1_ARB_MST_CRED_STS_15 0xDA2BEC 763 764#define mmNIC3_QM1_ARB_MST_CRED_STS_16 0xDA2BF0 765 766#define mmNIC3_QM1_ARB_MST_CRED_STS_17 0xDA2BF4 767 768#define mmNIC3_QM1_ARB_MST_CRED_STS_18 0xDA2BF8 769 770#define mmNIC3_QM1_ARB_MST_CRED_STS_19 0xDA2BFC 771 772#define mmNIC3_QM1_ARB_MST_CRED_STS_20 0xDA2C00 773 774#define mmNIC3_QM1_ARB_MST_CRED_STS_21 0xDA2C04 775 776#define mmNIC3_QM1_ARB_MST_CRED_STS_22 0xDA2C08 777 778#define mmNIC3_QM1_ARB_MST_CRED_STS_23 0xDA2C0C 779 780#define mmNIC3_QM1_ARB_MST_CRED_STS_24 0xDA2C10 781 782#define mmNIC3_QM1_ARB_MST_CRED_STS_25 0xDA2C14 783 784#define mmNIC3_QM1_ARB_MST_CRED_STS_26 0xDA2C18 785 786#define mmNIC3_QM1_ARB_MST_CRED_STS_27 0xDA2C1C 787 788#define mmNIC3_QM1_ARB_MST_CRED_STS_28 0xDA2C20 789 790#define mmNIC3_QM1_ARB_MST_CRED_STS_29 0xDA2C24 791 792#define mmNIC3_QM1_ARB_MST_CRED_STS_30 0xDA2C28 793 794#define mmNIC3_QM1_ARB_MST_CRED_STS_31 0xDA2C2C 795 796#define mmNIC3_QM1_CGM_CFG 0xDA2C70 797 798#define mmNIC3_QM1_CGM_STS 0xDA2C74 799 800#define mmNIC3_QM1_CGM_CFG1 0xDA2C78 801 802#define mmNIC3_QM1_LOCAL_RANGE_BASE 0xDA2C80 803 804#define mmNIC3_QM1_LOCAL_RANGE_SIZE 0xDA2C84 805 806#define mmNIC3_QM1_CSMR_STRICT_PRIO_CFG 0xDA2C90 807 808#define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_1 0xDA2C94 809 810#define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_0 0xDA2C98 811 812#define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_1 0xDA2C9C 813 814#define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_0 0xDA2CA0 815 816#define mmNIC3_QM1_GLBL_AXCACHE 0xDA2CA4 817 818#define mmNIC3_QM1_IND_GW_APB_CFG 0xDA2CB0 819 820#define mmNIC3_QM1_IND_GW_APB_WDATA 0xDA2CB4 821 822#define mmNIC3_QM1_IND_GW_APB_RDATA 0xDA2CB8 823 824#define mmNIC3_QM1_IND_GW_APB_STATUS 0xDA2CBC 825 826#define mmNIC3_QM1_GLBL_ERR_ADDR_LO 0xDA2CD0 827 828#define mmNIC3_QM1_GLBL_ERR_ADDR_HI 0xDA2CD4 829 830#define mmNIC3_QM1_GLBL_ERR_WDATA 0xDA2CD8 831 832#define mmNIC3_QM1_GLBL_MEM_INIT_BUSY 0xDA2D00 833 834#endif /* ASIC_REG_NIC3_QM1_REGS_H_ */ 835