1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_NIC1_QM1_REGS_H_ 14#define ASIC_REG_NIC1_QM1_REGS_H_ 15 16/* 17 ***************************************** 18 * NIC1_QM1 (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmNIC1_QM1_GLBL_CFG0 0xD22000 23 24#define mmNIC1_QM1_GLBL_CFG1 0xD22004 25 26#define mmNIC1_QM1_GLBL_PROT 0xD22008 27 28#define mmNIC1_QM1_GLBL_ERR_CFG 0xD2200C 29 30#define mmNIC1_QM1_GLBL_SECURE_PROPS_0 0xD22010 31 32#define mmNIC1_QM1_GLBL_SECURE_PROPS_1 0xD22014 33 34#define mmNIC1_QM1_GLBL_SECURE_PROPS_2 0xD22018 35 36#define mmNIC1_QM1_GLBL_SECURE_PROPS_3 0xD2201C 37 38#define mmNIC1_QM1_GLBL_SECURE_PROPS_4 0xD22020 39 40#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_0 0xD22024 41 42#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_1 0xD22028 43 44#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_2 0xD2202C 45 46#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_3 0xD22030 47 48#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_4 0xD22034 49 50#define mmNIC1_QM1_GLBL_STS0 0xD22038 51 52#define mmNIC1_QM1_GLBL_STS1_0 0xD22040 53 54#define mmNIC1_QM1_GLBL_STS1_1 0xD22044 55 56#define mmNIC1_QM1_GLBL_STS1_2 0xD22048 57 58#define mmNIC1_QM1_GLBL_STS1_3 0xD2204C 59 60#define mmNIC1_QM1_GLBL_STS1_4 0xD22050 61 62#define mmNIC1_QM1_GLBL_MSG_EN_0 0xD22054 63 64#define mmNIC1_QM1_GLBL_MSG_EN_1 0xD22058 65 66#define mmNIC1_QM1_GLBL_MSG_EN_2 0xD2205C 67 68#define mmNIC1_QM1_GLBL_MSG_EN_3 0xD22060 69 70#define mmNIC1_QM1_GLBL_MSG_EN_4 0xD22068 71 72#define mmNIC1_QM1_PQ_BASE_LO_0 0xD22070 73 74#define mmNIC1_QM1_PQ_BASE_LO_1 0xD22074 75 76#define mmNIC1_QM1_PQ_BASE_LO_2 0xD22078 77 78#define mmNIC1_QM1_PQ_BASE_LO_3 0xD2207C 79 80#define mmNIC1_QM1_PQ_BASE_HI_0 0xD22080 81 82#define mmNIC1_QM1_PQ_BASE_HI_1 0xD22084 83 84#define mmNIC1_QM1_PQ_BASE_HI_2 0xD22088 85 86#define mmNIC1_QM1_PQ_BASE_HI_3 0xD2208C 87 88#define mmNIC1_QM1_PQ_SIZE_0 0xD22090 89 90#define mmNIC1_QM1_PQ_SIZE_1 0xD22094 91 92#define mmNIC1_QM1_PQ_SIZE_2 0xD22098 93 94#define mmNIC1_QM1_PQ_SIZE_3 0xD2209C 95 96#define mmNIC1_QM1_PQ_PI_0 0xD220A0 97 98#define mmNIC1_QM1_PQ_PI_1 0xD220A4 99 100#define mmNIC1_QM1_PQ_PI_2 0xD220A8 101 102#define mmNIC1_QM1_PQ_PI_3 0xD220AC 103 104#define mmNIC1_QM1_PQ_CI_0 0xD220B0 105 106#define mmNIC1_QM1_PQ_CI_1 0xD220B4 107 108#define mmNIC1_QM1_PQ_CI_2 0xD220B8 109 110#define mmNIC1_QM1_PQ_CI_3 0xD220BC 111 112#define mmNIC1_QM1_PQ_CFG0_0 0xD220C0 113 114#define mmNIC1_QM1_PQ_CFG0_1 0xD220C4 115 116#define mmNIC1_QM1_PQ_CFG0_2 0xD220C8 117 118#define mmNIC1_QM1_PQ_CFG0_3 0xD220CC 119 120#define mmNIC1_QM1_PQ_CFG1_0 0xD220D0 121 122#define mmNIC1_QM1_PQ_CFG1_1 0xD220D4 123 124#define mmNIC1_QM1_PQ_CFG1_2 0xD220D8 125 126#define mmNIC1_QM1_PQ_CFG1_3 0xD220DC 127 128#define mmNIC1_QM1_PQ_ARUSER_31_11_0 0xD220E0 129 130#define mmNIC1_QM1_PQ_ARUSER_31_11_1 0xD220E4 131 132#define mmNIC1_QM1_PQ_ARUSER_31_11_2 0xD220E8 133 134#define mmNIC1_QM1_PQ_ARUSER_31_11_3 0xD220EC 135 136#define mmNIC1_QM1_PQ_STS0_0 0xD220F0 137 138#define mmNIC1_QM1_PQ_STS0_1 0xD220F4 139 140#define mmNIC1_QM1_PQ_STS0_2 0xD220F8 141 142#define mmNIC1_QM1_PQ_STS0_3 0xD220FC 143 144#define mmNIC1_QM1_PQ_STS1_0 0xD22100 145 146#define mmNIC1_QM1_PQ_STS1_1 0xD22104 147 148#define mmNIC1_QM1_PQ_STS1_2 0xD22108 149 150#define mmNIC1_QM1_PQ_STS1_3 0xD2210C 151 152#define mmNIC1_QM1_CQ_CFG0_0 0xD22110 153 154#define mmNIC1_QM1_CQ_CFG0_1 0xD22114 155 156#define mmNIC1_QM1_CQ_CFG0_2 0xD22118 157 158#define mmNIC1_QM1_CQ_CFG0_3 0xD2211C 159 160#define mmNIC1_QM1_CQ_CFG0_4 0xD22120 161 162#define mmNIC1_QM1_CQ_CFG1_0 0xD22124 163 164#define mmNIC1_QM1_CQ_CFG1_1 0xD22128 165 166#define mmNIC1_QM1_CQ_CFG1_2 0xD2212C 167 168#define mmNIC1_QM1_CQ_CFG1_3 0xD22130 169 170#define mmNIC1_QM1_CQ_CFG1_4 0xD22134 171 172#define mmNIC1_QM1_CQ_ARUSER_31_11_0 0xD22138 173 174#define mmNIC1_QM1_CQ_ARUSER_31_11_1 0xD2213C 175 176#define mmNIC1_QM1_CQ_ARUSER_31_11_2 0xD22140 177 178#define mmNIC1_QM1_CQ_ARUSER_31_11_3 0xD22144 179 180#define mmNIC1_QM1_CQ_ARUSER_31_11_4 0xD22148 181 182#define mmNIC1_QM1_CQ_STS0_0 0xD2214C 183 184#define mmNIC1_QM1_CQ_STS0_1 0xD22150 185 186#define mmNIC1_QM1_CQ_STS0_2 0xD22154 187 188#define mmNIC1_QM1_CQ_STS0_3 0xD22158 189 190#define mmNIC1_QM1_CQ_STS0_4 0xD2215C 191 192#define mmNIC1_QM1_CQ_STS1_0 0xD22160 193 194#define mmNIC1_QM1_CQ_STS1_1 0xD22164 195 196#define mmNIC1_QM1_CQ_STS1_2 0xD22168 197 198#define mmNIC1_QM1_CQ_STS1_3 0xD2216C 199 200#define mmNIC1_QM1_CQ_STS1_4 0xD22170 201 202#define mmNIC1_QM1_CQ_PTR_LO_0 0xD22174 203 204#define mmNIC1_QM1_CQ_PTR_HI_0 0xD22178 205 206#define mmNIC1_QM1_CQ_TSIZE_0 0xD2217C 207 208#define mmNIC1_QM1_CQ_CTL_0 0xD22180 209 210#define mmNIC1_QM1_CQ_PTR_LO_1 0xD22184 211 212#define mmNIC1_QM1_CQ_PTR_HI_1 0xD22188 213 214#define mmNIC1_QM1_CQ_TSIZE_1 0xD2218C 215 216#define mmNIC1_QM1_CQ_CTL_1 0xD22190 217 218#define mmNIC1_QM1_CQ_PTR_LO_2 0xD22194 219 220#define mmNIC1_QM1_CQ_PTR_HI_2 0xD22198 221 222#define mmNIC1_QM1_CQ_TSIZE_2 0xD2219C 223 224#define mmNIC1_QM1_CQ_CTL_2 0xD221A0 225 226#define mmNIC1_QM1_CQ_PTR_LO_3 0xD221A4 227 228#define mmNIC1_QM1_CQ_PTR_HI_3 0xD221A8 229 230#define mmNIC1_QM1_CQ_TSIZE_3 0xD221AC 231 232#define mmNIC1_QM1_CQ_CTL_3 0xD221B0 233 234#define mmNIC1_QM1_CQ_PTR_LO_4 0xD221B4 235 236#define mmNIC1_QM1_CQ_PTR_HI_4 0xD221B8 237 238#define mmNIC1_QM1_CQ_TSIZE_4 0xD221BC 239 240#define mmNIC1_QM1_CQ_CTL_4 0xD221C0 241 242#define mmNIC1_QM1_CQ_PTR_LO_STS_0 0xD221C4 243 244#define mmNIC1_QM1_CQ_PTR_LO_STS_1 0xD221C8 245 246#define mmNIC1_QM1_CQ_PTR_LO_STS_2 0xD221CC 247 248#define mmNIC1_QM1_CQ_PTR_LO_STS_3 0xD221D0 249 250#define mmNIC1_QM1_CQ_PTR_LO_STS_4 0xD221D4 251 252#define mmNIC1_QM1_CQ_PTR_HI_STS_0 0xD221D8 253 254#define mmNIC1_QM1_CQ_PTR_HI_STS_1 0xD221DC 255 256#define mmNIC1_QM1_CQ_PTR_HI_STS_2 0xD221E0 257 258#define mmNIC1_QM1_CQ_PTR_HI_STS_3 0xD221E4 259 260#define mmNIC1_QM1_CQ_PTR_HI_STS_4 0xD221E8 261 262#define mmNIC1_QM1_CQ_TSIZE_STS_0 0xD221EC 263 264#define mmNIC1_QM1_CQ_TSIZE_STS_1 0xD221F0 265 266#define mmNIC1_QM1_CQ_TSIZE_STS_2 0xD221F4 267 268#define mmNIC1_QM1_CQ_TSIZE_STS_3 0xD221F8 269 270#define mmNIC1_QM1_CQ_TSIZE_STS_4 0xD221FC 271 272#define mmNIC1_QM1_CQ_CTL_STS_0 0xD22200 273 274#define mmNIC1_QM1_CQ_CTL_STS_1 0xD22204 275 276#define mmNIC1_QM1_CQ_CTL_STS_2 0xD22208 277 278#define mmNIC1_QM1_CQ_CTL_STS_3 0xD2220C 279 280#define mmNIC1_QM1_CQ_CTL_STS_4 0xD22210 281 282#define mmNIC1_QM1_CQ_IFIFO_CNT_0 0xD22214 283 284#define mmNIC1_QM1_CQ_IFIFO_CNT_1 0xD22218 285 286#define mmNIC1_QM1_CQ_IFIFO_CNT_2 0xD2221C 287 288#define mmNIC1_QM1_CQ_IFIFO_CNT_3 0xD22220 289 290#define mmNIC1_QM1_CQ_IFIFO_CNT_4 0xD22224 291 292#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_0 0xD22228 293 294#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_1 0xD2222C 295 296#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_2 0xD22230 297 298#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_3 0xD22234 299 300#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_4 0xD22238 301 302#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_0 0xD2223C 303 304#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_1 0xD22240 305 306#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_2 0xD22244 307 308#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_3 0xD22248 309 310#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_4 0xD2224C 311 312#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_0 0xD22250 313 314#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_1 0xD22254 315 316#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_2 0xD22258 317 318#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_3 0xD2225C 319 320#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_4 0xD22260 321 322#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_0 0xD22264 323 324#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_1 0xD22268 325 326#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_2 0xD2226C 327 328#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_3 0xD22270 329 330#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_4 0xD22274 331 332#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_0 0xD22278 333 334#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_1 0xD2227C 335 336#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 0xD22280 337 338#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_3 0xD22284 339 340#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_4 0xD22288 341 342#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_0 0xD2228C 343 344#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_1 0xD22290 345 346#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_2 0xD22294 347 348#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_3 0xD22298 349 350#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_4 0xD2229C 351 352#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_0 0xD222A0 353 354#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_1 0xD222A4 355 356#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_2 0xD222A8 357 358#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_3 0xD222AC 359 360#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_4 0xD222B0 361 362#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_0 0xD222B4 363 364#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_1 0xD222B8 365 366#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_2 0xD222BC 367 368#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_3 0xD222C0 369 370#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_4 0xD222C4 371 372#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_0 0xD222C8 373 374#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_1 0xD222CC 375 376#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_2 0xD222D0 377 378#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_3 0xD222D4 379 380#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_4 0xD222D8 381 382#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD222E0 383 384#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD222E4 385 386#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD222E8 387 388#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD222EC 389 390#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD222F0 391 392#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD222F4 393 394#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD222F8 395 396#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD222FC 397 398#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD22300 399 400#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD22304 401 402#define mmNIC1_QM1_CP_FENCE0_RDATA_0 0xD22308 403 404#define mmNIC1_QM1_CP_FENCE0_RDATA_1 0xD2230C 405 406#define mmNIC1_QM1_CP_FENCE0_RDATA_2 0xD22310 407 408#define mmNIC1_QM1_CP_FENCE0_RDATA_3 0xD22314 409 410#define mmNIC1_QM1_CP_FENCE0_RDATA_4 0xD22318 411 412#define mmNIC1_QM1_CP_FENCE1_RDATA_0 0xD2231C 413 414#define mmNIC1_QM1_CP_FENCE1_RDATA_1 0xD22320 415 416#define mmNIC1_QM1_CP_FENCE1_RDATA_2 0xD22324 417 418#define mmNIC1_QM1_CP_FENCE1_RDATA_3 0xD22328 419 420#define mmNIC1_QM1_CP_FENCE1_RDATA_4 0xD2232C 421 422#define mmNIC1_QM1_CP_FENCE2_RDATA_0 0xD22330 423 424#define mmNIC1_QM1_CP_FENCE2_RDATA_1 0xD22334 425 426#define mmNIC1_QM1_CP_FENCE2_RDATA_2 0xD22338 427 428#define mmNIC1_QM1_CP_FENCE2_RDATA_3 0xD2233C 429 430#define mmNIC1_QM1_CP_FENCE2_RDATA_4 0xD22340 431 432#define mmNIC1_QM1_CP_FENCE3_RDATA_0 0xD22344 433 434#define mmNIC1_QM1_CP_FENCE3_RDATA_1 0xD22348 435 436#define mmNIC1_QM1_CP_FENCE3_RDATA_2 0xD2234C 437 438#define mmNIC1_QM1_CP_FENCE3_RDATA_3 0xD22350 439 440#define mmNIC1_QM1_CP_FENCE3_RDATA_4 0xD22354 441 442#define mmNIC1_QM1_CP_FENCE0_CNT_0 0xD22358 443 444#define mmNIC1_QM1_CP_FENCE0_CNT_1 0xD2235C 445 446#define mmNIC1_QM1_CP_FENCE0_CNT_2 0xD22360 447 448#define mmNIC1_QM1_CP_FENCE0_CNT_3 0xD22364 449 450#define mmNIC1_QM1_CP_FENCE0_CNT_4 0xD22368 451 452#define mmNIC1_QM1_CP_FENCE1_CNT_0 0xD2236C 453 454#define mmNIC1_QM1_CP_FENCE1_CNT_1 0xD22370 455 456#define mmNIC1_QM1_CP_FENCE1_CNT_2 0xD22374 457 458#define mmNIC1_QM1_CP_FENCE1_CNT_3 0xD22378 459 460#define mmNIC1_QM1_CP_FENCE1_CNT_4 0xD2237C 461 462#define mmNIC1_QM1_CP_FENCE2_CNT_0 0xD22380 463 464#define mmNIC1_QM1_CP_FENCE2_CNT_1 0xD22384 465 466#define mmNIC1_QM1_CP_FENCE2_CNT_2 0xD22388 467 468#define mmNIC1_QM1_CP_FENCE2_CNT_3 0xD2238C 469 470#define mmNIC1_QM1_CP_FENCE2_CNT_4 0xD22390 471 472#define mmNIC1_QM1_CP_FENCE3_CNT_0 0xD22394 473 474#define mmNIC1_QM1_CP_FENCE3_CNT_1 0xD22398 475 476#define mmNIC1_QM1_CP_FENCE3_CNT_2 0xD2239C 477 478#define mmNIC1_QM1_CP_FENCE3_CNT_3 0xD223A0 479 480#define mmNIC1_QM1_CP_FENCE3_CNT_4 0xD223A4 481 482#define mmNIC1_QM1_CP_STS_0 0xD223A8 483 484#define mmNIC1_QM1_CP_STS_1 0xD223AC 485 486#define mmNIC1_QM1_CP_STS_2 0xD223B0 487 488#define mmNIC1_QM1_CP_STS_3 0xD223B4 489 490#define mmNIC1_QM1_CP_STS_4 0xD223B8 491 492#define mmNIC1_QM1_CP_CURRENT_INST_LO_0 0xD223BC 493 494#define mmNIC1_QM1_CP_CURRENT_INST_LO_1 0xD223C0 495 496#define mmNIC1_QM1_CP_CURRENT_INST_LO_2 0xD223C4 497 498#define mmNIC1_QM1_CP_CURRENT_INST_LO_3 0xD223C8 499 500#define mmNIC1_QM1_CP_CURRENT_INST_LO_4 0xD223CC 501 502#define mmNIC1_QM1_CP_CURRENT_INST_HI_0 0xD223D0 503 504#define mmNIC1_QM1_CP_CURRENT_INST_HI_1 0xD223D4 505 506#define mmNIC1_QM1_CP_CURRENT_INST_HI_2 0xD223D8 507 508#define mmNIC1_QM1_CP_CURRENT_INST_HI_3 0xD223DC 509 510#define mmNIC1_QM1_CP_CURRENT_INST_HI_4 0xD223E0 511 512#define mmNIC1_QM1_CP_BARRIER_CFG_0 0xD223F4 513 514#define mmNIC1_QM1_CP_BARRIER_CFG_1 0xD223F8 515 516#define mmNIC1_QM1_CP_BARRIER_CFG_2 0xD223FC 517 518#define mmNIC1_QM1_CP_BARRIER_CFG_3 0xD22400 519 520#define mmNIC1_QM1_CP_BARRIER_CFG_4 0xD22404 521 522#define mmNIC1_QM1_CP_DBG_0_0 0xD22408 523 524#define mmNIC1_QM1_CP_DBG_0_1 0xD2240C 525 526#define mmNIC1_QM1_CP_DBG_0_2 0xD22410 527 528#define mmNIC1_QM1_CP_DBG_0_3 0xD22414 529 530#define mmNIC1_QM1_CP_DBG_0_4 0xD22418 531 532#define mmNIC1_QM1_CP_ARUSER_31_11_0 0xD2241C 533 534#define mmNIC1_QM1_CP_ARUSER_31_11_1 0xD22420 535 536#define mmNIC1_QM1_CP_ARUSER_31_11_2 0xD22424 537 538#define mmNIC1_QM1_CP_ARUSER_31_11_3 0xD22428 539 540#define mmNIC1_QM1_CP_ARUSER_31_11_4 0xD2242C 541 542#define mmNIC1_QM1_CP_AWUSER_31_11_0 0xD22430 543 544#define mmNIC1_QM1_CP_AWUSER_31_11_1 0xD22434 545 546#define mmNIC1_QM1_CP_AWUSER_31_11_2 0xD22438 547 548#define mmNIC1_QM1_CP_AWUSER_31_11_3 0xD2243C 549 550#define mmNIC1_QM1_CP_AWUSER_31_11_4 0xD22440 551 552#define mmNIC1_QM1_ARB_CFG_0 0xD22A00 553 554#define mmNIC1_QM1_ARB_CHOISE_Q_PUSH 0xD22A04 555 556#define mmNIC1_QM1_ARB_WRR_WEIGHT_0 0xD22A08 557 558#define mmNIC1_QM1_ARB_WRR_WEIGHT_1 0xD22A0C 559 560#define mmNIC1_QM1_ARB_WRR_WEIGHT_2 0xD22A10 561 562#define mmNIC1_QM1_ARB_WRR_WEIGHT_3 0xD22A14 563 564#define mmNIC1_QM1_ARB_CFG_1 0xD22A18 565 566#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_0 0xD22A20 567 568#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_1 0xD22A24 569 570#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_2 0xD22A28 571 572#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_3 0xD22A2C 573 574#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_4 0xD22A30 575 576#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_5 0xD22A34 577 578#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_6 0xD22A38 579 580#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_7 0xD22A3C 581 582#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_8 0xD22A40 583 584#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_9 0xD22A44 585 586#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_10 0xD22A48 587 588#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_11 0xD22A4C 589 590#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_12 0xD22A50 591 592#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_13 0xD22A54 593 594#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_14 0xD22A58 595 596#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_15 0xD22A5C 597 598#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_16 0xD22A60 599 600#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_17 0xD22A64 601 602#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_18 0xD22A68 603 604#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_19 0xD22A6C 605 606#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_20 0xD22A70 607 608#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_21 0xD22A74 609 610#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_22 0xD22A78 611 612#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_23 0xD22A7C 613 614#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 0xD22A80 615 616#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_25 0xD22A84 617 618#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_26 0xD22A88 619 620#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_27 0xD22A8C 621 622#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_28 0xD22A90 623 624#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_29 0xD22A94 625 626#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_30 0xD22A98 627 628#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_31 0xD22A9C 629 630#define mmNIC1_QM1_ARB_MST_CRED_INC 0xD22AA0 631 632#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xD22AA4 633 634#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xD22AA8 635 636#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xD22AAC 637 638#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xD22AB0 639 640#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xD22AB4 641 642#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xD22AB8 643 644#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xD22ABC 645 646#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xD22AC0 647 648#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xD22AC4 649 650#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xD22AC8 651 652#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xD22ACC 653 654#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xD22AD0 655 656#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xD22AD4 657 658#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xD22AD8 659 660#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xD22ADC 661 662#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xD22AE0 663 664#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xD22AE4 665 666#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xD22AE8 667 668#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xD22AEC 669 670#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xD22AF0 671 672#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xD22AF4 673 674#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xD22AF8 675 676#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xD22AFC 677 678#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xD22B00 679 680#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xD22B04 681 682#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xD22B08 683 684#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xD22B0C 685 686#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xD22B10 687 688#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xD22B14 689 690#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xD22B18 691 692#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xD22B1C 693 694#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xD22B20 695 696#define mmNIC1_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xD22B28 697 698#define mmNIC1_QM1_ARB_MST_SLAVE_EN 0xD22B2C 699 700#define mmNIC1_QM1_ARB_MST_QUIET_PER 0xD22B34 701 702#define mmNIC1_QM1_ARB_SLV_CHOISE_WDT 0xD22B38 703 704#define mmNIC1_QM1_ARB_SLV_ID 0xD22B3C 705 706#define mmNIC1_QM1_ARB_MSG_MAX_INFLIGHT 0xD22B44 707 708#define mmNIC1_QM1_ARB_MSG_AWUSER_31_11 0xD22B48 709 710#define mmNIC1_QM1_ARB_MSG_AWUSER_SEC_PROP 0xD22B4C 711 712#define mmNIC1_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xD22B50 713 714#define mmNIC1_QM1_ARB_BASE_LO 0xD22B54 715 716#define mmNIC1_QM1_ARB_BASE_HI 0xD22B58 717 718#define mmNIC1_QM1_ARB_STATE_STS 0xD22B80 719 720#define mmNIC1_QM1_ARB_CHOISE_FULLNESS_STS 0xD22B84 721 722#define mmNIC1_QM1_ARB_MSG_STS 0xD22B88 723 724#define mmNIC1_QM1_ARB_SLV_CHOISE_Q_HEAD 0xD22B8C 725 726#define mmNIC1_QM1_ARB_ERR_CAUSE 0xD22B9C 727 728#define mmNIC1_QM1_ARB_ERR_MSG_EN 0xD22BA0 729 730#define mmNIC1_QM1_ARB_ERR_STS_DRP 0xD22BA8 731 732#define mmNIC1_QM1_ARB_MST_CRED_STS_0 0xD22BB0 733 734#define mmNIC1_QM1_ARB_MST_CRED_STS_1 0xD22BB4 735 736#define mmNIC1_QM1_ARB_MST_CRED_STS_2 0xD22BB8 737 738#define mmNIC1_QM1_ARB_MST_CRED_STS_3 0xD22BBC 739 740#define mmNIC1_QM1_ARB_MST_CRED_STS_4 0xD22BC0 741 742#define mmNIC1_QM1_ARB_MST_CRED_STS_5 0xD22BC4 743 744#define mmNIC1_QM1_ARB_MST_CRED_STS_6 0xD22BC8 745 746#define mmNIC1_QM1_ARB_MST_CRED_STS_7 0xD22BCC 747 748#define mmNIC1_QM1_ARB_MST_CRED_STS_8 0xD22BD0 749 750#define mmNIC1_QM1_ARB_MST_CRED_STS_9 0xD22BD4 751 752#define mmNIC1_QM1_ARB_MST_CRED_STS_10 0xD22BD8 753 754#define mmNIC1_QM1_ARB_MST_CRED_STS_11 0xD22BDC 755 756#define mmNIC1_QM1_ARB_MST_CRED_STS_12 0xD22BE0 757 758#define mmNIC1_QM1_ARB_MST_CRED_STS_13 0xD22BE4 759 760#define mmNIC1_QM1_ARB_MST_CRED_STS_14 0xD22BE8 761 762#define mmNIC1_QM1_ARB_MST_CRED_STS_15 0xD22BEC 763 764#define mmNIC1_QM1_ARB_MST_CRED_STS_16 0xD22BF0 765 766#define mmNIC1_QM1_ARB_MST_CRED_STS_17 0xD22BF4 767 768#define mmNIC1_QM1_ARB_MST_CRED_STS_18 0xD22BF8 769 770#define mmNIC1_QM1_ARB_MST_CRED_STS_19 0xD22BFC 771 772#define mmNIC1_QM1_ARB_MST_CRED_STS_20 0xD22C00 773 774#define mmNIC1_QM1_ARB_MST_CRED_STS_21 0xD22C04 775 776#define mmNIC1_QM1_ARB_MST_CRED_STS_22 0xD22C08 777 778#define mmNIC1_QM1_ARB_MST_CRED_STS_23 0xD22C0C 779 780#define mmNIC1_QM1_ARB_MST_CRED_STS_24 0xD22C10 781 782#define mmNIC1_QM1_ARB_MST_CRED_STS_25 0xD22C14 783 784#define mmNIC1_QM1_ARB_MST_CRED_STS_26 0xD22C18 785 786#define mmNIC1_QM1_ARB_MST_CRED_STS_27 0xD22C1C 787 788#define mmNIC1_QM1_ARB_MST_CRED_STS_28 0xD22C20 789 790#define mmNIC1_QM1_ARB_MST_CRED_STS_29 0xD22C24 791 792#define mmNIC1_QM1_ARB_MST_CRED_STS_30 0xD22C28 793 794#define mmNIC1_QM1_ARB_MST_CRED_STS_31 0xD22C2C 795 796#define mmNIC1_QM1_CGM_CFG 0xD22C70 797 798#define mmNIC1_QM1_CGM_STS 0xD22C74 799 800#define mmNIC1_QM1_CGM_CFG1 0xD22C78 801 802#define mmNIC1_QM1_LOCAL_RANGE_BASE 0xD22C80 803 804#define mmNIC1_QM1_LOCAL_RANGE_SIZE 0xD22C84 805 806#define mmNIC1_QM1_CSMR_STRICT_PRIO_CFG 0xD22C90 807 808#define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_1 0xD22C94 809 810#define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_0 0xD22C98 811 812#define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_1 0xD22C9C 813 814#define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_0 0xD22CA0 815 816#define mmNIC1_QM1_GLBL_AXCACHE 0xD22CA4 817 818#define mmNIC1_QM1_IND_GW_APB_CFG 0xD22CB0 819 820#define mmNIC1_QM1_IND_GW_APB_WDATA 0xD22CB4 821 822#define mmNIC1_QM1_IND_GW_APB_RDATA 0xD22CB8 823 824#define mmNIC1_QM1_IND_GW_APB_STATUS 0xD22CBC 825 826#define mmNIC1_QM1_GLBL_ERR_ADDR_LO 0xD22CD0 827 828#define mmNIC1_QM1_GLBL_ERR_ADDR_HI 0xD22CD4 829 830#define mmNIC1_QM1_GLBL_ERR_WDATA 0xD22CD8 831 832#define mmNIC1_QM1_GLBL_MEM_INIT_BUSY 0xD22D00 833 834#endif /* ASIC_REG_NIC1_QM1_REGS_H_ */ 835