1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_DMA7_QM_REGS_H_ 14#define ASIC_REG_DMA7_QM_REGS_H_ 15 16/* 17 ***************************************** 18 * DMA7_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmDMA7_QM_GLBL_CFG0 0x5E8000 23 24#define mmDMA7_QM_GLBL_CFG1 0x5E8004 25 26#define mmDMA7_QM_GLBL_PROT 0x5E8008 27 28#define mmDMA7_QM_GLBL_ERR_CFG 0x5E800C 29 30#define mmDMA7_QM_GLBL_SECURE_PROPS_0 0x5E8010 31 32#define mmDMA7_QM_GLBL_SECURE_PROPS_1 0x5E8014 33 34#define mmDMA7_QM_GLBL_SECURE_PROPS_2 0x5E8018 35 36#define mmDMA7_QM_GLBL_SECURE_PROPS_3 0x5E801C 37 38#define mmDMA7_QM_GLBL_SECURE_PROPS_4 0x5E8020 39 40#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 0x5E8024 41 42#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 0x5E8028 43 44#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 0x5E802C 45 46#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 0x5E8030 47 48#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 0x5E8034 49 50#define mmDMA7_QM_GLBL_STS0 0x5E8038 51 52#define mmDMA7_QM_GLBL_STS1_0 0x5E8040 53 54#define mmDMA7_QM_GLBL_STS1_1 0x5E8044 55 56#define mmDMA7_QM_GLBL_STS1_2 0x5E8048 57 58#define mmDMA7_QM_GLBL_STS1_3 0x5E804C 59 60#define mmDMA7_QM_GLBL_STS1_4 0x5E8050 61 62#define mmDMA7_QM_GLBL_MSG_EN_0 0x5E8054 63 64#define mmDMA7_QM_GLBL_MSG_EN_1 0x5E8058 65 66#define mmDMA7_QM_GLBL_MSG_EN_2 0x5E805C 67 68#define mmDMA7_QM_GLBL_MSG_EN_3 0x5E8060 69 70#define mmDMA7_QM_GLBL_MSG_EN_4 0x5E8068 71 72#define mmDMA7_QM_PQ_BASE_LO_0 0x5E8070 73 74#define mmDMA7_QM_PQ_BASE_LO_1 0x5E8074 75 76#define mmDMA7_QM_PQ_BASE_LO_2 0x5E8078 77 78#define mmDMA7_QM_PQ_BASE_LO_3 0x5E807C 79 80#define mmDMA7_QM_PQ_BASE_HI_0 0x5E8080 81 82#define mmDMA7_QM_PQ_BASE_HI_1 0x5E8084 83 84#define mmDMA7_QM_PQ_BASE_HI_2 0x5E8088 85 86#define mmDMA7_QM_PQ_BASE_HI_3 0x5E808C 87 88#define mmDMA7_QM_PQ_SIZE_0 0x5E8090 89 90#define mmDMA7_QM_PQ_SIZE_1 0x5E8094 91 92#define mmDMA7_QM_PQ_SIZE_2 0x5E8098 93 94#define mmDMA7_QM_PQ_SIZE_3 0x5E809C 95 96#define mmDMA7_QM_PQ_PI_0 0x5E80A0 97 98#define mmDMA7_QM_PQ_PI_1 0x5E80A4 99 100#define mmDMA7_QM_PQ_PI_2 0x5E80A8 101 102#define mmDMA7_QM_PQ_PI_3 0x5E80AC 103 104#define mmDMA7_QM_PQ_CI_0 0x5E80B0 105 106#define mmDMA7_QM_PQ_CI_1 0x5E80B4 107 108#define mmDMA7_QM_PQ_CI_2 0x5E80B8 109 110#define mmDMA7_QM_PQ_CI_3 0x5E80BC 111 112#define mmDMA7_QM_PQ_CFG0_0 0x5E80C0 113 114#define mmDMA7_QM_PQ_CFG0_1 0x5E80C4 115 116#define mmDMA7_QM_PQ_CFG0_2 0x5E80C8 117 118#define mmDMA7_QM_PQ_CFG0_3 0x5E80CC 119 120#define mmDMA7_QM_PQ_CFG1_0 0x5E80D0 121 122#define mmDMA7_QM_PQ_CFG1_1 0x5E80D4 123 124#define mmDMA7_QM_PQ_CFG1_2 0x5E80D8 125 126#define mmDMA7_QM_PQ_CFG1_3 0x5E80DC 127 128#define mmDMA7_QM_PQ_ARUSER_31_11_0 0x5E80E0 129 130#define mmDMA7_QM_PQ_ARUSER_31_11_1 0x5E80E4 131 132#define mmDMA7_QM_PQ_ARUSER_31_11_2 0x5E80E8 133 134#define mmDMA7_QM_PQ_ARUSER_31_11_3 0x5E80EC 135 136#define mmDMA7_QM_PQ_STS0_0 0x5E80F0 137 138#define mmDMA7_QM_PQ_STS0_1 0x5E80F4 139 140#define mmDMA7_QM_PQ_STS0_2 0x5E80F8 141 142#define mmDMA7_QM_PQ_STS0_3 0x5E80FC 143 144#define mmDMA7_QM_PQ_STS1_0 0x5E8100 145 146#define mmDMA7_QM_PQ_STS1_1 0x5E8104 147 148#define mmDMA7_QM_PQ_STS1_2 0x5E8108 149 150#define mmDMA7_QM_PQ_STS1_3 0x5E810C 151 152#define mmDMA7_QM_CQ_CFG0_0 0x5E8110 153 154#define mmDMA7_QM_CQ_CFG0_1 0x5E8114 155 156#define mmDMA7_QM_CQ_CFG0_2 0x5E8118 157 158#define mmDMA7_QM_CQ_CFG0_3 0x5E811C 159 160#define mmDMA7_QM_CQ_CFG0_4 0x5E8120 161 162#define mmDMA7_QM_CQ_CFG1_0 0x5E8124 163 164#define mmDMA7_QM_CQ_CFG1_1 0x5E8128 165 166#define mmDMA7_QM_CQ_CFG1_2 0x5E812C 167 168#define mmDMA7_QM_CQ_CFG1_3 0x5E8130 169 170#define mmDMA7_QM_CQ_CFG1_4 0x5E8134 171 172#define mmDMA7_QM_CQ_ARUSER_31_11_0 0x5E8138 173 174#define mmDMA7_QM_CQ_ARUSER_31_11_1 0x5E813C 175 176#define mmDMA7_QM_CQ_ARUSER_31_11_2 0x5E8140 177 178#define mmDMA7_QM_CQ_ARUSER_31_11_3 0x5E8144 179 180#define mmDMA7_QM_CQ_ARUSER_31_11_4 0x5E8148 181 182#define mmDMA7_QM_CQ_STS0_0 0x5E814C 183 184#define mmDMA7_QM_CQ_STS0_1 0x5E8150 185 186#define mmDMA7_QM_CQ_STS0_2 0x5E8154 187 188#define mmDMA7_QM_CQ_STS0_3 0x5E8158 189 190#define mmDMA7_QM_CQ_STS0_4 0x5E815C 191 192#define mmDMA7_QM_CQ_STS1_0 0x5E8160 193 194#define mmDMA7_QM_CQ_STS1_1 0x5E8164 195 196#define mmDMA7_QM_CQ_STS1_2 0x5E8168 197 198#define mmDMA7_QM_CQ_STS1_3 0x5E816C 199 200#define mmDMA7_QM_CQ_STS1_4 0x5E8170 201 202#define mmDMA7_QM_CQ_PTR_LO_0 0x5E8174 203 204#define mmDMA7_QM_CQ_PTR_HI_0 0x5E8178 205 206#define mmDMA7_QM_CQ_TSIZE_0 0x5E817C 207 208#define mmDMA7_QM_CQ_CTL_0 0x5E8180 209 210#define mmDMA7_QM_CQ_PTR_LO_1 0x5E8184 211 212#define mmDMA7_QM_CQ_PTR_HI_1 0x5E8188 213 214#define mmDMA7_QM_CQ_TSIZE_1 0x5E818C 215 216#define mmDMA7_QM_CQ_CTL_1 0x5E8190 217 218#define mmDMA7_QM_CQ_PTR_LO_2 0x5E8194 219 220#define mmDMA7_QM_CQ_PTR_HI_2 0x5E8198 221 222#define mmDMA7_QM_CQ_TSIZE_2 0x5E819C 223 224#define mmDMA7_QM_CQ_CTL_2 0x5E81A0 225 226#define mmDMA7_QM_CQ_PTR_LO_3 0x5E81A4 227 228#define mmDMA7_QM_CQ_PTR_HI_3 0x5E81A8 229 230#define mmDMA7_QM_CQ_TSIZE_3 0x5E81AC 231 232#define mmDMA7_QM_CQ_CTL_3 0x5E81B0 233 234#define mmDMA7_QM_CQ_PTR_LO_4 0x5E81B4 235 236#define mmDMA7_QM_CQ_PTR_HI_4 0x5E81B8 237 238#define mmDMA7_QM_CQ_TSIZE_4 0x5E81BC 239 240#define mmDMA7_QM_CQ_CTL_4 0x5E81C0 241 242#define mmDMA7_QM_CQ_PTR_LO_STS_0 0x5E81C4 243 244#define mmDMA7_QM_CQ_PTR_LO_STS_1 0x5E81C8 245 246#define mmDMA7_QM_CQ_PTR_LO_STS_2 0x5E81CC 247 248#define mmDMA7_QM_CQ_PTR_LO_STS_3 0x5E81D0 249 250#define mmDMA7_QM_CQ_PTR_LO_STS_4 0x5E81D4 251 252#define mmDMA7_QM_CQ_PTR_HI_STS_0 0x5E81D8 253 254#define mmDMA7_QM_CQ_PTR_HI_STS_1 0x5E81DC 255 256#define mmDMA7_QM_CQ_PTR_HI_STS_2 0x5E81E0 257 258#define mmDMA7_QM_CQ_PTR_HI_STS_3 0x5E81E4 259 260#define mmDMA7_QM_CQ_PTR_HI_STS_4 0x5E81E8 261 262#define mmDMA7_QM_CQ_TSIZE_STS_0 0x5E81EC 263 264#define mmDMA7_QM_CQ_TSIZE_STS_1 0x5E81F0 265 266#define mmDMA7_QM_CQ_TSIZE_STS_2 0x5E81F4 267 268#define mmDMA7_QM_CQ_TSIZE_STS_3 0x5E81F8 269 270#define mmDMA7_QM_CQ_TSIZE_STS_4 0x5E81FC 271 272#define mmDMA7_QM_CQ_CTL_STS_0 0x5E8200 273 274#define mmDMA7_QM_CQ_CTL_STS_1 0x5E8204 275 276#define mmDMA7_QM_CQ_CTL_STS_2 0x5E8208 277 278#define mmDMA7_QM_CQ_CTL_STS_3 0x5E820C 279 280#define mmDMA7_QM_CQ_CTL_STS_4 0x5E8210 281 282#define mmDMA7_QM_CQ_IFIFO_CNT_0 0x5E8214 283 284#define mmDMA7_QM_CQ_IFIFO_CNT_1 0x5E8218 285 286#define mmDMA7_QM_CQ_IFIFO_CNT_2 0x5E821C 287 288#define mmDMA7_QM_CQ_IFIFO_CNT_3 0x5E8220 289 290#define mmDMA7_QM_CQ_IFIFO_CNT_4 0x5E8224 291 292#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 0x5E8228 293 294#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 0x5E822C 295 296#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 0x5E8230 297 298#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 0x5E8234 299 300#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 0x5E8238 301 302#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 0x5E823C 303 304#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 0x5E8240 305 306#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 0x5E8244 307 308#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 0x5E8248 309 310#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 0x5E824C 311 312#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 0x5E8250 313 314#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 0x5E8254 315 316#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 0x5E8258 317 318#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 0x5E825C 319 320#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 0x5E8260 321 322#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 0x5E8264 323 324#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 0x5E8268 325 326#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 0x5E826C 327 328#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 0x5E8270 329 330#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 0x5E8274 331 332#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 0x5E8278 333 334#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 0x5E827C 335 336#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 0x5E8280 337 338#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 0x5E8284 339 340#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 0x5E8288 341 342#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 0x5E828C 343 344#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 0x5E8290 345 346#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 0x5E8294 347 348#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 0x5E8298 349 350#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 0x5E829C 351 352#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 0x5E82A0 353 354#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 0x5E82A4 355 356#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 0x5E82A8 357 358#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 0x5E82AC 359 360#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 0x5E82B0 361 362#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 0x5E82B4 363 364#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 0x5E82B8 365 366#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 0x5E82BC 367 368#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 0x5E82C0 369 370#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 0x5E82C4 371 372#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 0x5E82C8 373 374#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 0x5E82CC 375 376#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 0x5E82D0 377 378#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 0x5E82D4 379 380#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 0x5E82D8 381 382#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5E82E0 383 384#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5E82E4 385 386#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5E82E8 387 388#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5E82EC 389 390#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5E82F0 391 392#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5E82F4 393 394#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5E82F8 395 396#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5E82FC 397 398#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5E8300 399 400#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5E8304 401 402#define mmDMA7_QM_CP_FENCE0_RDATA_0 0x5E8308 403 404#define mmDMA7_QM_CP_FENCE0_RDATA_1 0x5E830C 405 406#define mmDMA7_QM_CP_FENCE0_RDATA_2 0x5E8310 407 408#define mmDMA7_QM_CP_FENCE0_RDATA_3 0x5E8314 409 410#define mmDMA7_QM_CP_FENCE0_RDATA_4 0x5E8318 411 412#define mmDMA7_QM_CP_FENCE1_RDATA_0 0x5E831C 413 414#define mmDMA7_QM_CP_FENCE1_RDATA_1 0x5E8320 415 416#define mmDMA7_QM_CP_FENCE1_RDATA_2 0x5E8324 417 418#define mmDMA7_QM_CP_FENCE1_RDATA_3 0x5E8328 419 420#define mmDMA7_QM_CP_FENCE1_RDATA_4 0x5E832C 421 422#define mmDMA7_QM_CP_FENCE2_RDATA_0 0x5E8330 423 424#define mmDMA7_QM_CP_FENCE2_RDATA_1 0x5E8334 425 426#define mmDMA7_QM_CP_FENCE2_RDATA_2 0x5E8338 427 428#define mmDMA7_QM_CP_FENCE2_RDATA_3 0x5E833C 429 430#define mmDMA7_QM_CP_FENCE2_RDATA_4 0x5E8340 431 432#define mmDMA7_QM_CP_FENCE3_RDATA_0 0x5E8344 433 434#define mmDMA7_QM_CP_FENCE3_RDATA_1 0x5E8348 435 436#define mmDMA7_QM_CP_FENCE3_RDATA_2 0x5E834C 437 438#define mmDMA7_QM_CP_FENCE3_RDATA_3 0x5E8350 439 440#define mmDMA7_QM_CP_FENCE3_RDATA_4 0x5E8354 441 442#define mmDMA7_QM_CP_FENCE0_CNT_0 0x5E8358 443 444#define mmDMA7_QM_CP_FENCE0_CNT_1 0x5E835C 445 446#define mmDMA7_QM_CP_FENCE0_CNT_2 0x5E8360 447 448#define mmDMA7_QM_CP_FENCE0_CNT_3 0x5E8364 449 450#define mmDMA7_QM_CP_FENCE0_CNT_4 0x5E8368 451 452#define mmDMA7_QM_CP_FENCE1_CNT_0 0x5E836C 453 454#define mmDMA7_QM_CP_FENCE1_CNT_1 0x5E8370 455 456#define mmDMA7_QM_CP_FENCE1_CNT_2 0x5E8374 457 458#define mmDMA7_QM_CP_FENCE1_CNT_3 0x5E8378 459 460#define mmDMA7_QM_CP_FENCE1_CNT_4 0x5E837C 461 462#define mmDMA7_QM_CP_FENCE2_CNT_0 0x5E8380 463 464#define mmDMA7_QM_CP_FENCE2_CNT_1 0x5E8384 465 466#define mmDMA7_QM_CP_FENCE2_CNT_2 0x5E8388 467 468#define mmDMA7_QM_CP_FENCE2_CNT_3 0x5E838C 469 470#define mmDMA7_QM_CP_FENCE2_CNT_4 0x5E8390 471 472#define mmDMA7_QM_CP_FENCE3_CNT_0 0x5E8394 473 474#define mmDMA7_QM_CP_FENCE3_CNT_1 0x5E8398 475 476#define mmDMA7_QM_CP_FENCE3_CNT_2 0x5E839C 477 478#define mmDMA7_QM_CP_FENCE3_CNT_3 0x5E83A0 479 480#define mmDMA7_QM_CP_FENCE3_CNT_4 0x5E83A4 481 482#define mmDMA7_QM_CP_STS_0 0x5E83A8 483 484#define mmDMA7_QM_CP_STS_1 0x5E83AC 485 486#define mmDMA7_QM_CP_STS_2 0x5E83B0 487 488#define mmDMA7_QM_CP_STS_3 0x5E83B4 489 490#define mmDMA7_QM_CP_STS_4 0x5E83B8 491 492#define mmDMA7_QM_CP_CURRENT_INST_LO_0 0x5E83BC 493 494#define mmDMA7_QM_CP_CURRENT_INST_LO_1 0x5E83C0 495 496#define mmDMA7_QM_CP_CURRENT_INST_LO_2 0x5E83C4 497 498#define mmDMA7_QM_CP_CURRENT_INST_LO_3 0x5E83C8 499 500#define mmDMA7_QM_CP_CURRENT_INST_LO_4 0x5E83CC 501 502#define mmDMA7_QM_CP_CURRENT_INST_HI_0 0x5E83D0 503 504#define mmDMA7_QM_CP_CURRENT_INST_HI_1 0x5E83D4 505 506#define mmDMA7_QM_CP_CURRENT_INST_HI_2 0x5E83D8 507 508#define mmDMA7_QM_CP_CURRENT_INST_HI_3 0x5E83DC 509 510#define mmDMA7_QM_CP_CURRENT_INST_HI_4 0x5E83E0 511 512#define mmDMA7_QM_CP_BARRIER_CFG_0 0x5E83F4 513 514#define mmDMA7_QM_CP_BARRIER_CFG_1 0x5E83F8 515 516#define mmDMA7_QM_CP_BARRIER_CFG_2 0x5E83FC 517 518#define mmDMA7_QM_CP_BARRIER_CFG_3 0x5E8400 519 520#define mmDMA7_QM_CP_BARRIER_CFG_4 0x5E8404 521 522#define mmDMA7_QM_CP_DBG_0_0 0x5E8408 523 524#define mmDMA7_QM_CP_DBG_0_1 0x5E840C 525 526#define mmDMA7_QM_CP_DBG_0_2 0x5E8410 527 528#define mmDMA7_QM_CP_DBG_0_3 0x5E8414 529 530#define mmDMA7_QM_CP_DBG_0_4 0x5E8418 531 532#define mmDMA7_QM_CP_ARUSER_31_11_0 0x5E841C 533 534#define mmDMA7_QM_CP_ARUSER_31_11_1 0x5E8420 535 536#define mmDMA7_QM_CP_ARUSER_31_11_2 0x5E8424 537 538#define mmDMA7_QM_CP_ARUSER_31_11_3 0x5E8428 539 540#define mmDMA7_QM_CP_ARUSER_31_11_4 0x5E842C 541 542#define mmDMA7_QM_CP_AWUSER_31_11_0 0x5E8430 543 544#define mmDMA7_QM_CP_AWUSER_31_11_1 0x5E8434 545 546#define mmDMA7_QM_CP_AWUSER_31_11_2 0x5E8438 547 548#define mmDMA7_QM_CP_AWUSER_31_11_3 0x5E843C 549 550#define mmDMA7_QM_CP_AWUSER_31_11_4 0x5E8440 551 552#define mmDMA7_QM_ARB_CFG_0 0x5E8A00 553 554#define mmDMA7_QM_ARB_CHOISE_Q_PUSH 0x5E8A04 555 556#define mmDMA7_QM_ARB_WRR_WEIGHT_0 0x5E8A08 557 558#define mmDMA7_QM_ARB_WRR_WEIGHT_1 0x5E8A0C 559 560#define mmDMA7_QM_ARB_WRR_WEIGHT_2 0x5E8A10 561 562#define mmDMA7_QM_ARB_WRR_WEIGHT_3 0x5E8A14 563 564#define mmDMA7_QM_ARB_CFG_1 0x5E8A18 565 566#define mmDMA7_QM_ARB_MST_AVAIL_CRED_0 0x5E8A20 567 568#define mmDMA7_QM_ARB_MST_AVAIL_CRED_1 0x5E8A24 569 570#define mmDMA7_QM_ARB_MST_AVAIL_CRED_2 0x5E8A28 571 572#define mmDMA7_QM_ARB_MST_AVAIL_CRED_3 0x5E8A2C 573 574#define mmDMA7_QM_ARB_MST_AVAIL_CRED_4 0x5E8A30 575 576#define mmDMA7_QM_ARB_MST_AVAIL_CRED_5 0x5E8A34 577 578#define mmDMA7_QM_ARB_MST_AVAIL_CRED_6 0x5E8A38 579 580#define mmDMA7_QM_ARB_MST_AVAIL_CRED_7 0x5E8A3C 581 582#define mmDMA7_QM_ARB_MST_AVAIL_CRED_8 0x5E8A40 583 584#define mmDMA7_QM_ARB_MST_AVAIL_CRED_9 0x5E8A44 585 586#define mmDMA7_QM_ARB_MST_AVAIL_CRED_10 0x5E8A48 587 588#define mmDMA7_QM_ARB_MST_AVAIL_CRED_11 0x5E8A4C 589 590#define mmDMA7_QM_ARB_MST_AVAIL_CRED_12 0x5E8A50 591 592#define mmDMA7_QM_ARB_MST_AVAIL_CRED_13 0x5E8A54 593 594#define mmDMA7_QM_ARB_MST_AVAIL_CRED_14 0x5E8A58 595 596#define mmDMA7_QM_ARB_MST_AVAIL_CRED_15 0x5E8A5C 597 598#define mmDMA7_QM_ARB_MST_AVAIL_CRED_16 0x5E8A60 599 600#define mmDMA7_QM_ARB_MST_AVAIL_CRED_17 0x5E8A64 601 602#define mmDMA7_QM_ARB_MST_AVAIL_CRED_18 0x5E8A68 603 604#define mmDMA7_QM_ARB_MST_AVAIL_CRED_19 0x5E8A6C 605 606#define mmDMA7_QM_ARB_MST_AVAIL_CRED_20 0x5E8A70 607 608#define mmDMA7_QM_ARB_MST_AVAIL_CRED_21 0x5E8A74 609 610#define mmDMA7_QM_ARB_MST_AVAIL_CRED_22 0x5E8A78 611 612#define mmDMA7_QM_ARB_MST_AVAIL_CRED_23 0x5E8A7C 613 614#define mmDMA7_QM_ARB_MST_AVAIL_CRED_24 0x5E8A80 615 616#define mmDMA7_QM_ARB_MST_AVAIL_CRED_25 0x5E8A84 617 618#define mmDMA7_QM_ARB_MST_AVAIL_CRED_26 0x5E8A88 619 620#define mmDMA7_QM_ARB_MST_AVAIL_CRED_27 0x5E8A8C 621 622#define mmDMA7_QM_ARB_MST_AVAIL_CRED_28 0x5E8A90 623 624#define mmDMA7_QM_ARB_MST_AVAIL_CRED_29 0x5E8A94 625 626#define mmDMA7_QM_ARB_MST_AVAIL_CRED_30 0x5E8A98 627 628#define mmDMA7_QM_ARB_MST_AVAIL_CRED_31 0x5E8A9C 629 630#define mmDMA7_QM_ARB_MST_CRED_INC 0x5E8AA0 631 632#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5E8AA4 633 634#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5E8AA8 635 636#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5E8AAC 637 638#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5E8AB0 639 640#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5E8AB4 641 642#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5E8AB8 643 644#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5E8ABC 645 646#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5E8AC0 647 648#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5E8AC4 649 650#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5E8AC8 651 652#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5E8ACC 653 654#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5E8AD0 655 656#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5E8AD4 657 658#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5E8AD8 659 660#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5E8ADC 661 662#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5E8AE0 663 664#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5E8AE4 665 666#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5E8AE8 667 668#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5E8AEC 669 670#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5E8AF0 671 672#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5E8AF4 673 674#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5E8AF8 675 676#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5E8AFC 677 678#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5E8B00 679 680#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5E8B04 681 682#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5E8B08 683 684#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5E8B0C 685 686#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5E8B10 687 688#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5E8B14 689 690#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5E8B18 691 692#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5E8B1C 693 694#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5E8B20 695 696#define mmDMA7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5E8B28 697 698#define mmDMA7_QM_ARB_MST_SLAVE_EN 0x5E8B2C 699 700#define mmDMA7_QM_ARB_MST_QUIET_PER 0x5E8B34 701 702#define mmDMA7_QM_ARB_SLV_CHOISE_WDT 0x5E8B38 703 704#define mmDMA7_QM_ARB_SLV_ID 0x5E8B3C 705 706#define mmDMA7_QM_ARB_MSG_MAX_INFLIGHT 0x5E8B44 707 708#define mmDMA7_QM_ARB_MSG_AWUSER_31_11 0x5E8B48 709 710#define mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP 0x5E8B4C 711 712#define mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5E8B50 713 714#define mmDMA7_QM_ARB_BASE_LO 0x5E8B54 715 716#define mmDMA7_QM_ARB_BASE_HI 0x5E8B58 717 718#define mmDMA7_QM_ARB_STATE_STS 0x5E8B80 719 720#define mmDMA7_QM_ARB_CHOISE_FULLNESS_STS 0x5E8B84 721 722#define mmDMA7_QM_ARB_MSG_STS 0x5E8B88 723 724#define mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD 0x5E8B8C 725 726#define mmDMA7_QM_ARB_ERR_CAUSE 0x5E8B9C 727 728#define mmDMA7_QM_ARB_ERR_MSG_EN 0x5E8BA0 729 730#define mmDMA7_QM_ARB_ERR_STS_DRP 0x5E8BA8 731 732#define mmDMA7_QM_ARB_MST_CRED_STS_0 0x5E8BB0 733 734#define mmDMA7_QM_ARB_MST_CRED_STS_1 0x5E8BB4 735 736#define mmDMA7_QM_ARB_MST_CRED_STS_2 0x5E8BB8 737 738#define mmDMA7_QM_ARB_MST_CRED_STS_3 0x5E8BBC 739 740#define mmDMA7_QM_ARB_MST_CRED_STS_4 0x5E8BC0 741 742#define mmDMA7_QM_ARB_MST_CRED_STS_5 0x5E8BC4 743 744#define mmDMA7_QM_ARB_MST_CRED_STS_6 0x5E8BC8 745 746#define mmDMA7_QM_ARB_MST_CRED_STS_7 0x5E8BCC 747 748#define mmDMA7_QM_ARB_MST_CRED_STS_8 0x5E8BD0 749 750#define mmDMA7_QM_ARB_MST_CRED_STS_9 0x5E8BD4 751 752#define mmDMA7_QM_ARB_MST_CRED_STS_10 0x5E8BD8 753 754#define mmDMA7_QM_ARB_MST_CRED_STS_11 0x5E8BDC 755 756#define mmDMA7_QM_ARB_MST_CRED_STS_12 0x5E8BE0 757 758#define mmDMA7_QM_ARB_MST_CRED_STS_13 0x5E8BE4 759 760#define mmDMA7_QM_ARB_MST_CRED_STS_14 0x5E8BE8 761 762#define mmDMA7_QM_ARB_MST_CRED_STS_15 0x5E8BEC 763 764#define mmDMA7_QM_ARB_MST_CRED_STS_16 0x5E8BF0 765 766#define mmDMA7_QM_ARB_MST_CRED_STS_17 0x5E8BF4 767 768#define mmDMA7_QM_ARB_MST_CRED_STS_18 0x5E8BF8 769 770#define mmDMA7_QM_ARB_MST_CRED_STS_19 0x5E8BFC 771 772#define mmDMA7_QM_ARB_MST_CRED_STS_20 0x5E8C00 773 774#define mmDMA7_QM_ARB_MST_CRED_STS_21 0x5E8C04 775 776#define mmDMA7_QM_ARB_MST_CRED_STS_22 0x5E8C08 777 778#define mmDMA7_QM_ARB_MST_CRED_STS_23 0x5E8C0C 779 780#define mmDMA7_QM_ARB_MST_CRED_STS_24 0x5E8C10 781 782#define mmDMA7_QM_ARB_MST_CRED_STS_25 0x5E8C14 783 784#define mmDMA7_QM_ARB_MST_CRED_STS_26 0x5E8C18 785 786#define mmDMA7_QM_ARB_MST_CRED_STS_27 0x5E8C1C 787 788#define mmDMA7_QM_ARB_MST_CRED_STS_28 0x5E8C20 789 790#define mmDMA7_QM_ARB_MST_CRED_STS_29 0x5E8C24 791 792#define mmDMA7_QM_ARB_MST_CRED_STS_30 0x5E8C28 793 794#define mmDMA7_QM_ARB_MST_CRED_STS_31 0x5E8C2C 795 796#define mmDMA7_QM_CGM_CFG 0x5E8C70 797 798#define mmDMA7_QM_CGM_STS 0x5E8C74 799 800#define mmDMA7_QM_CGM_CFG1 0x5E8C78 801 802#define mmDMA7_QM_LOCAL_RANGE_BASE 0x5E8C80 803 804#define mmDMA7_QM_LOCAL_RANGE_SIZE 0x5E8C84 805 806#define mmDMA7_QM_CSMR_STRICT_PRIO_CFG 0x5E8C90 807 808#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 0x5E8C94 809 810#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 0x5E8C98 811 812#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 0x5E8C9C 813 814#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 0x5E8CA0 815 816#define mmDMA7_QM_GLBL_AXCACHE 0x5E8CA4 817 818#define mmDMA7_QM_IND_GW_APB_CFG 0x5E8CB0 819 820#define mmDMA7_QM_IND_GW_APB_WDATA 0x5E8CB4 821 822#define mmDMA7_QM_IND_GW_APB_RDATA 0x5E8CB8 823 824#define mmDMA7_QM_IND_GW_APB_STATUS 0x5E8CBC 825 826#define mmDMA7_QM_GLBL_ERR_ADDR_LO 0x5E8CD0 827 828#define mmDMA7_QM_GLBL_ERR_ADDR_HI 0x5E8CD4 829 830#define mmDMA7_QM_GLBL_ERR_WDATA 0x5E8CD8 831 832#define mmDMA7_QM_GLBL_MEM_INIT_BUSY 0x5E8D00 833 834#endif /* ASIC_REG_DMA7_QM_REGS_H_ */ 835