1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 **       DO NOT EDIT BELOW        **
11 ************************************/
12
13#ifndef ASIC_REG_DMA6_CORE_REGS_H_
14#define ASIC_REG_DMA6_CORE_REGS_H_
15
16/*
17 *****************************************
18 *   DMA6_CORE (Prototype: DMA_CORE)
19 *****************************************
20 */
21
22#define mmDMA6_CORE_CFG_0                                            0x5C0000
23
24#define mmDMA6_CORE_CFG_1                                            0x5C0004
25
26#define mmDMA6_CORE_LBW_MAX_OUTSTAND                                 0x5C0008
27
28#define mmDMA6_CORE_SRC_BASE_LO                                      0x5C0014
29
30#define mmDMA6_CORE_SRC_BASE_HI                                      0x5C0018
31
32#define mmDMA6_CORE_DST_BASE_LO                                      0x5C001C
33
34#define mmDMA6_CORE_DST_BASE_HI                                      0x5C0020
35
36#define mmDMA6_CORE_SRC_TSIZE_1                                      0x5C002C
37
38#define mmDMA6_CORE_SRC_STRIDE_1                                     0x5C0030
39
40#define mmDMA6_CORE_SRC_TSIZE_2                                      0x5C0034
41
42#define mmDMA6_CORE_SRC_STRIDE_2                                     0x5C0038
43
44#define mmDMA6_CORE_SRC_TSIZE_3                                      0x5C003C
45
46#define mmDMA6_CORE_SRC_STRIDE_3                                     0x5C0040
47
48#define mmDMA6_CORE_SRC_TSIZE_4                                      0x5C0044
49
50#define mmDMA6_CORE_SRC_STRIDE_4                                     0x5C0048
51
52#define mmDMA6_CORE_SRC_TSIZE_0                                      0x5C004C
53
54#define mmDMA6_CORE_DST_TSIZE_1                                      0x5C0054
55
56#define mmDMA6_CORE_DST_STRIDE_1                                     0x5C0058
57
58#define mmDMA6_CORE_DST_TSIZE_2                                      0x5C005C
59
60#define mmDMA6_CORE_DST_STRIDE_2                                     0x5C0060
61
62#define mmDMA6_CORE_DST_TSIZE_3                                      0x5C0064
63
64#define mmDMA6_CORE_DST_STRIDE_3                                     0x5C0068
65
66#define mmDMA6_CORE_DST_TSIZE_4                                      0x5C006C
67
68#define mmDMA6_CORE_DST_STRIDE_4                                     0x5C0070
69
70#define mmDMA6_CORE_DST_TSIZE_0                                      0x5C0074
71
72#define mmDMA6_CORE_COMMIT                                           0x5C0078
73
74#define mmDMA6_CORE_WR_COMP_WDATA                                    0x5C007C
75
76#define mmDMA6_CORE_WR_COMP_ADDR_LO                                  0x5C0080
77
78#define mmDMA6_CORE_WR_COMP_ADDR_HI                                  0x5C0084
79
80#define mmDMA6_CORE_WR_COMP_AWUSER_31_11                             0x5C0088
81
82#define mmDMA6_CORE_TE_NUMROWS                                       0x5C0094
83
84#define mmDMA6_CORE_PROT                                             0x5C00B8
85
86#define mmDMA6_CORE_SECURE_PROPS                                     0x5C00F0
87
88#define mmDMA6_CORE_NON_SECURE_PROPS                                 0x5C00F4
89
90#define mmDMA6_CORE_RD_MAX_OUTSTAND                                  0x5C0100
91
92#define mmDMA6_CORE_RD_MAX_SIZE                                      0x5C0104
93
94#define mmDMA6_CORE_RD_ARCACHE                                       0x5C0108
95
96#define mmDMA6_CORE_RD_ARUSER_31_11                                  0x5C0110
97
98#define mmDMA6_CORE_RD_INFLIGHTS                                     0x5C0114
99
100#define mmDMA6_CORE_WR_MAX_OUTSTAND                                  0x5C0120
101
102#define mmDMA6_CORE_WR_MAX_AWID                                      0x5C0124
103
104#define mmDMA6_CORE_WR_AWCACHE                                       0x5C0128
105
106#define mmDMA6_CORE_WR_AWUSER_31_11                                  0x5C0130
107
108#define mmDMA6_CORE_WR_INFLIGHTS                                     0x5C0134
109
110#define mmDMA6_CORE_RD_RATE_LIM_CFG_0                                0x5C0150
111
112#define mmDMA6_CORE_RD_RATE_LIM_CFG_1                                0x5C0154
113
114#define mmDMA6_CORE_WR_RATE_LIM_CFG_0                                0x5C0158
115
116#define mmDMA6_CORE_WR_RATE_LIM_CFG_1                                0x5C015C
117
118#define mmDMA6_CORE_ERR_CFG                                          0x5C0160
119
120#define mmDMA6_CORE_ERR_CAUSE                                        0x5C0164
121
122#define mmDMA6_CORE_ERRMSG_ADDR_LO                                   0x5C0170
123
124#define mmDMA6_CORE_ERRMSG_ADDR_HI                                   0x5C0174
125
126#define mmDMA6_CORE_ERRMSG_WDATA                                     0x5C0178
127
128#define mmDMA6_CORE_STS0                                             0x5C0190
129
130#define mmDMA6_CORE_STS1                                             0x5C0194
131
132#define mmDMA6_CORE_RD_DBGMEM_ADD                                    0x5C0200
133
134#define mmDMA6_CORE_RD_DBGMEM_DATA_WR                                0x5C0204
135
136#define mmDMA6_CORE_RD_DBGMEM_DATA_RD                                0x5C0208
137
138#define mmDMA6_CORE_RD_DBGMEM_CTRL                                   0x5C020C
139
140#define mmDMA6_CORE_RD_DBGMEM_RC                                     0x5C0210
141
142#define mmDMA6_CORE_DBG_HBW_AXI_AR_CNT                               0x5C0220
143
144#define mmDMA6_CORE_DBG_HBW_AXI_AW_CNT                               0x5C0224
145
146#define mmDMA6_CORE_DBG_LBW_AXI_AW_CNT                               0x5C0228
147
148#define mmDMA6_CORE_DBG_DESC_CNT                                     0x5C022C
149
150#define mmDMA6_CORE_DBG_STS                                          0x5C0230
151
152#define mmDMA6_CORE_DBG_RD_DESC_ID                                   0x5C0234
153
154#define mmDMA6_CORE_DBG_WR_DESC_ID                                   0x5C0238
155
156#endif /* ASIC_REG_DMA6_CORE_REGS_H_ */
157