1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_DMA4_CORE_REGS_H_ 14#define ASIC_REG_DMA4_CORE_REGS_H_ 15 16/* 17 ***************************************** 18 * DMA4_CORE (Prototype: DMA_CORE) 19 ***************************************** 20 */ 21 22#define mmDMA4_CORE_CFG_0 0x580000 23 24#define mmDMA4_CORE_CFG_1 0x580004 25 26#define mmDMA4_CORE_LBW_MAX_OUTSTAND 0x580008 27 28#define mmDMA4_CORE_SRC_BASE_LO 0x580014 29 30#define mmDMA4_CORE_SRC_BASE_HI 0x580018 31 32#define mmDMA4_CORE_DST_BASE_LO 0x58001C 33 34#define mmDMA4_CORE_DST_BASE_HI 0x580020 35 36#define mmDMA4_CORE_SRC_TSIZE_1 0x58002C 37 38#define mmDMA4_CORE_SRC_STRIDE_1 0x580030 39 40#define mmDMA4_CORE_SRC_TSIZE_2 0x580034 41 42#define mmDMA4_CORE_SRC_STRIDE_2 0x580038 43 44#define mmDMA4_CORE_SRC_TSIZE_3 0x58003C 45 46#define mmDMA4_CORE_SRC_STRIDE_3 0x580040 47 48#define mmDMA4_CORE_SRC_TSIZE_4 0x580044 49 50#define mmDMA4_CORE_SRC_STRIDE_4 0x580048 51 52#define mmDMA4_CORE_SRC_TSIZE_0 0x58004C 53 54#define mmDMA4_CORE_DST_TSIZE_1 0x580054 55 56#define mmDMA4_CORE_DST_STRIDE_1 0x580058 57 58#define mmDMA4_CORE_DST_TSIZE_2 0x58005C 59 60#define mmDMA4_CORE_DST_STRIDE_2 0x580060 61 62#define mmDMA4_CORE_DST_TSIZE_3 0x580064 63 64#define mmDMA4_CORE_DST_STRIDE_3 0x580068 65 66#define mmDMA4_CORE_DST_TSIZE_4 0x58006C 67 68#define mmDMA4_CORE_DST_STRIDE_4 0x580070 69 70#define mmDMA4_CORE_DST_TSIZE_0 0x580074 71 72#define mmDMA4_CORE_COMMIT 0x580078 73 74#define mmDMA4_CORE_WR_COMP_WDATA 0x58007C 75 76#define mmDMA4_CORE_WR_COMP_ADDR_LO 0x580080 77 78#define mmDMA4_CORE_WR_COMP_ADDR_HI 0x580084 79 80#define mmDMA4_CORE_WR_COMP_AWUSER_31_11 0x580088 81 82#define mmDMA4_CORE_TE_NUMROWS 0x580094 83 84#define mmDMA4_CORE_PROT 0x5800B8 85 86#define mmDMA4_CORE_SECURE_PROPS 0x5800F0 87 88#define mmDMA4_CORE_NON_SECURE_PROPS 0x5800F4 89 90#define mmDMA4_CORE_RD_MAX_OUTSTAND 0x580100 91 92#define mmDMA4_CORE_RD_MAX_SIZE 0x580104 93 94#define mmDMA4_CORE_RD_ARCACHE 0x580108 95 96#define mmDMA4_CORE_RD_ARUSER_31_11 0x580110 97 98#define mmDMA4_CORE_RD_INFLIGHTS 0x580114 99 100#define mmDMA4_CORE_WR_MAX_OUTSTAND 0x580120 101 102#define mmDMA4_CORE_WR_MAX_AWID 0x580124 103 104#define mmDMA4_CORE_WR_AWCACHE 0x580128 105 106#define mmDMA4_CORE_WR_AWUSER_31_11 0x580130 107 108#define mmDMA4_CORE_WR_INFLIGHTS 0x580134 109 110#define mmDMA4_CORE_RD_RATE_LIM_CFG_0 0x580150 111 112#define mmDMA4_CORE_RD_RATE_LIM_CFG_1 0x580154 113 114#define mmDMA4_CORE_WR_RATE_LIM_CFG_0 0x580158 115 116#define mmDMA4_CORE_WR_RATE_LIM_CFG_1 0x58015C 117 118#define mmDMA4_CORE_ERR_CFG 0x580160 119 120#define mmDMA4_CORE_ERR_CAUSE 0x580164 121 122#define mmDMA4_CORE_ERRMSG_ADDR_LO 0x580170 123 124#define mmDMA4_CORE_ERRMSG_ADDR_HI 0x580174 125 126#define mmDMA4_CORE_ERRMSG_WDATA 0x580178 127 128#define mmDMA4_CORE_STS0 0x580190 129 130#define mmDMA4_CORE_STS1 0x580194 131 132#define mmDMA4_CORE_RD_DBGMEM_ADD 0x580200 133 134#define mmDMA4_CORE_RD_DBGMEM_DATA_WR 0x580204 135 136#define mmDMA4_CORE_RD_DBGMEM_DATA_RD 0x580208 137 138#define mmDMA4_CORE_RD_DBGMEM_CTRL 0x58020C 139 140#define mmDMA4_CORE_RD_DBGMEM_RC 0x580210 141 142#define mmDMA4_CORE_DBG_HBW_AXI_AR_CNT 0x580220 143 144#define mmDMA4_CORE_DBG_HBW_AXI_AW_CNT 0x580224 145 146#define mmDMA4_CORE_DBG_LBW_AXI_AW_CNT 0x580228 147 148#define mmDMA4_CORE_DBG_DESC_CNT 0x58022C 149 150#define mmDMA4_CORE_DBG_STS 0x580230 151 152#define mmDMA4_CORE_DBG_RD_DESC_ID 0x580234 153 154#define mmDMA4_CORE_DBG_WR_DESC_ID 0x580238 155 156#endif /* ASIC_REG_DMA4_CORE_REGS_H_ */ 157