133965Sjdp/* SPDX-License-Identifier: GPL-2.0 2218822Sdim * 3218822Sdim * Copyright 2016-2018 HabanaLabs, Ltd. 433965Sjdp * All Rights Reserved. 589857Sobrien * 633965Sjdp */ 789857Sobrien 889857Sobrien/************************************ 989857Sobrien ** This is an auto-generated file ** 1089857Sobrien ** DO NOT EDIT BELOW ** 1133965Sjdp ************************************/ 1289857Sobrien 1389857Sobrien#ifndef ASIC_REG_DMA0_CORE_MASKS_H_ 1489857Sobrien#define ASIC_REG_DMA0_CORE_MASKS_H_ 1589857Sobrien 1633965Sjdp/* 1789857Sobrien ***************************************** 1889857Sobrien * DMA0_CORE (Prototype: DMA_CORE) 19218822Sdim ***************************************** 2033965Sjdp */ 2133965Sjdp 2233965Sjdp/* DMA0_CORE_CFG_0 */ 2333965Sjdp#define DMA0_CORE_CFG_0_EN_SHIFT 0 2433965Sjdp#define DMA0_CORE_CFG_0_EN_MASK 0x1 2533965Sjdp 2633965Sjdp/* DMA0_CORE_CFG_1 */ 2733965Sjdp#define DMA0_CORE_CFG_1_HALT_SHIFT 0 2833965Sjdp#define DMA0_CORE_CFG_1_HALT_MASK 0x1 2989857Sobrien#define DMA0_CORE_CFG_1_FLUSH_SHIFT 1 3033965Sjdp#define DMA0_CORE_CFG_1_FLUSH_MASK 0x2 31218822Sdim#define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT 2 3233965Sjdp#define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK 0x4 3333965Sjdp 3491041Sobrien/* DMA0_CORE_LBW_MAX_OUTSTAND */ 35218822Sdim#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT 0 3633965Sjdp#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK 0x1F 3733965Sjdp 3833965Sjdp/* DMA0_CORE_SRC_BASE_LO */ 3933965Sjdp#define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT 0 4033965Sjdp#define DMA0_CORE_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF 4133965Sjdp 4233965Sjdp/* DMA0_CORE_SRC_BASE_HI */ 4333965Sjdp#define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT 0 4433965Sjdp#define DMA0_CORE_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF 4533965Sjdp 4689857Sobrien/* DMA0_CORE_DST_BASE_LO */ 4789857Sobrien#define DMA0_CORE_DST_BASE_LO_VAL_SHIFT 0 4889857Sobrien#define DMA0_CORE_DST_BASE_LO_VAL_MASK 0xFFFFFFFF 49218822Sdim 50218822Sdim/* DMA0_CORE_DST_BASE_HI */ 51218822Sdim#define DMA0_CORE_DST_BASE_HI_VAL_SHIFT 0 5233965Sjdp#define DMA0_CORE_DST_BASE_HI_VAL_MASK 0xFFFFFF 5333965Sjdp#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT 24 5489857Sobrien#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK 0xFF000000 5533965Sjdp 5689857Sobrien/* DMA0_CORE_SRC_TSIZE_1 */ 5789857Sobrien#define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT 0 5889857Sobrien#define DMA0_CORE_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF 5989857Sobrien 6033965Sjdp/* DMA0_CORE_SRC_STRIDE_1 */ 6133965Sjdp#define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT 0 6233965Sjdp#define DMA0_CORE_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF 6338889Sjdp 6433965Sjdp/* DMA0_CORE_SRC_TSIZE_2 */ 6589857Sobrien#define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT 0 6633965Sjdp#define DMA0_CORE_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF 67130561Sobrien 68130561Sobrien/* DMA0_CORE_SRC_STRIDE_2 */ 69130561Sobrien#define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT 0 70130561Sobrien#define DMA0_CORE_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF 71130561Sobrien 72130561Sobrien/* DMA0_CORE_SRC_TSIZE_3 */ 73130561Sobrien#define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT 0 74130561Sobrien#define DMA0_CORE_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF 75130561Sobrien 76130561Sobrien/* DMA0_CORE_SRC_STRIDE_3 */ 77130561Sobrien#define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT 0 78130561Sobrien#define DMA0_CORE_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF 7933965Sjdp 8033965Sjdp/* DMA0_CORE_SRC_TSIZE_4 */ 81130561Sobrien#define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT 0 8233965Sjdp#define DMA0_CORE_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF 8389857Sobrien 8489857Sobrien/* DMA0_CORE_SRC_STRIDE_4 */ 85104834Sobrien#define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT 0 8689857Sobrien#define DMA0_CORE_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF 8789857Sobrien 88130561Sobrien/* DMA0_CORE_SRC_TSIZE_0 */ 8989857Sobrien#define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT 0 9089857Sobrien#define DMA0_CORE_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF 91218822Sdim 9289857Sobrien/* DMA0_CORE_DST_TSIZE_1 */ 9389857Sobrien#define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT 0 9489857Sobrien#define DMA0_CORE_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF 9533965Sjdp 9689857Sobrien/* DMA0_CORE_DST_STRIDE_1 */ 9733965Sjdp#define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT 0 9889857Sobrien#define DMA0_CORE_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF 9933965Sjdp 10089857Sobrien/* DMA0_CORE_DST_TSIZE_2 */ 10133965Sjdp#define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT 0 102218822Sdim#define DMA0_CORE_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF 10360484Sobrien 10433965Sjdp/* DMA0_CORE_DST_STRIDE_2 */ 10533965Sjdp#define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT 0 10633965Sjdp#define DMA0_CORE_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF 107218822Sdim 10833965Sjdp/* DMA0_CORE_DST_TSIZE_3 */ 10933965Sjdp#define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT 0 11033965Sjdp#define DMA0_CORE_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF 11133965Sjdp 11289857Sobrien/* DMA0_CORE_DST_STRIDE_3 */ 11333965Sjdp#define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT 0 11433965Sjdp#define DMA0_CORE_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF 11533965Sjdp 11633965Sjdp/* DMA0_CORE_DST_TSIZE_4 */ 11733965Sjdp#define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT 0 118130561Sobrien#define DMA0_CORE_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF 11989857Sobrien 12033965Sjdp/* DMA0_CORE_DST_STRIDE_4 */ 121130561Sobrien#define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT 0 12233965Sjdp#define DMA0_CORE_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF 12333965Sjdp 12433965Sjdp/* DMA0_CORE_DST_TSIZE_0 */ 12533965Sjdp#define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT 0 12660484Sobrien#define DMA0_CORE_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF 12760484Sobrien 12860484Sobrien/* DMA0_CORE_COMMIT */ 12989857Sobrien#define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT 0 13089857Sobrien#define DMA0_CORE_COMMIT_WR_COMP_EN_MASK 0x1 13189857Sobrien#define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT 1 13260484Sobrien#define DMA0_CORE_COMMIT_TRANSPOSE_MASK 0x2 13360484Sobrien#define DMA0_CORE_COMMIT_DTYPE_SHIFT 2 13460484Sobrien#define DMA0_CORE_COMMIT_DTYPE_MASK 0x4 13533965Sjdp#define DMA0_CORE_COMMIT_LIN_SHIFT 3 13633965Sjdp#define DMA0_CORE_COMMIT_LIN_MASK 0x8 13733965Sjdp#define DMA0_CORE_COMMIT_MEM_SET_SHIFT 4 138218822Sdim#define DMA0_CORE_COMMIT_MEM_SET_MASK 0x10 139218822Sdim#define DMA0_CORE_COMMIT_COMPRESS_SHIFT 5 14033965Sjdp#define DMA0_CORE_COMMIT_COMPRESS_MASK 0x20 14133965Sjdp#define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT 6 14233965Sjdp#define DMA0_CORE_COMMIT_DECOMPRESS_MASK 0x40 14389857Sobrien#define DMA0_CORE_COMMIT_CTX_ID_SHIFT 16 14433965Sjdp#define DMA0_CORE_COMMIT_CTX_ID_MASK 0xFF0000 14533965Sjdp 14633965Sjdp/* DMA0_CORE_WR_COMP_WDATA */ 14733965Sjdp#define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT 0 14833965Sjdp#define DMA0_CORE_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF 14933965Sjdp 15033965Sjdp/* DMA0_CORE_WR_COMP_ADDR_LO */ 15133965Sjdp#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT 0 15233965Sjdp#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF 15333965Sjdp 15433965Sjdp/* DMA0_CORE_WR_COMP_ADDR_HI */ 15533965Sjdp#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT 0 15633965Sjdp#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF 15733965Sjdp 15833965Sjdp/* DMA0_CORE_WR_COMP_AWUSER_31_11 */ 15960484Sobrien#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT 0 16033965Sjdp#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK 0x1FFFFF 16133965Sjdp 16233965Sjdp/* DMA0_CORE_TE_NUMROWS */ 16333965Sjdp#define DMA0_CORE_TE_NUMROWS_VAL_SHIFT 0 16433965Sjdp#define DMA0_CORE_TE_NUMROWS_VAL_MASK 0xFFFFFFFF 16533965Sjdp 16633965Sjdp/* DMA0_CORE_PROT */ 16733965Sjdp#define DMA0_CORE_PROT_VAL_SHIFT 0 16833965Sjdp#define DMA0_CORE_PROT_VAL_MASK 0x1 16933965Sjdp#define DMA0_CORE_PROT_ERR_VAL_SHIFT 1 17033965Sjdp#define DMA0_CORE_PROT_ERR_VAL_MASK 0x2 17133965Sjdp 17233965Sjdp/* DMA0_CORE_SECURE_PROPS */ 17333965Sjdp#define DMA0_CORE_SECURE_PROPS_ASID_SHIFT 0 17433965Sjdp#define DMA0_CORE_SECURE_PROPS_ASID_MASK 0x3FF 17533965Sjdp#define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT 10 17633965Sjdp#define DMA0_CORE_SECURE_PROPS_MMBP_MASK 0x400 17733965Sjdp 17833965Sjdp/* DMA0_CORE_NON_SECURE_PROPS */ 17933965Sjdp#define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT 0 18033965Sjdp#define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK 0x3FF 18133965Sjdp#define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT 10 18233965Sjdp#define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK 0x400 18333965Sjdp 18433965Sjdp/* DMA0_CORE_RD_MAX_OUTSTAND */ 18533965Sjdp#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT 0 18660484Sobrien#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK 0xFFF 18733965Sjdp 18833965Sjdp/* DMA0_CORE_RD_MAX_SIZE */ 18933965Sjdp#define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT 0 19033965Sjdp#define DMA0_CORE_RD_MAX_SIZE_DATA_MASK 0x7FF 19133965Sjdp#define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT 16 19233965Sjdp#define DMA0_CORE_RD_MAX_SIZE_MD_MASK 0x7FF0000 19333965Sjdp 19433965Sjdp/* DMA0_CORE_RD_ARCACHE */ 19533965Sjdp#define DMA0_CORE_RD_ARCACHE_VAL_SHIFT 0 19633965Sjdp#define DMA0_CORE_RD_ARCACHE_VAL_MASK 0xF 19789857Sobrien 19833965Sjdp/* DMA0_CORE_RD_ARUSER_31_11 */ 19933965Sjdp#define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT 0 20033965Sjdp#define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK 0x1FFFFF 20133965Sjdp 20233965Sjdp/* DMA0_CORE_RD_INFLIGHTS */ 20333965Sjdp#define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT 0 20433965Sjdp#define DMA0_CORE_RD_INFLIGHTS_VAL_MASK 0xFFFFFFFF 20533965Sjdp 20633965Sjdp/* DMA0_CORE_WR_MAX_OUTSTAND */ 20733965Sjdp#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT 0 20833965Sjdp#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK 0xFFF 20933965Sjdp 21089857Sobrien/* DMA0_CORE_WR_MAX_AWID */ 21189857Sobrien#define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT 0 21289857Sobrien#define DMA0_CORE_WR_MAX_AWID_VAL_MASK 0xFFFF 21377298Sobrien 21477298Sobrien/* DMA0_CORE_WR_AWCACHE */ 21577298Sobrien#define DMA0_CORE_WR_AWCACHE_VAL_SHIFT 0 21677298Sobrien#define DMA0_CORE_WR_AWCACHE_VAL_MASK 0xF 21777298Sobrien 21877298Sobrien/* DMA0_CORE_WR_AWUSER_31_11 */ 21977298Sobrien#define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT 0 22077298Sobrien#define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK 0x1FFFFF 22177298Sobrien 22277298Sobrien/* DMA0_CORE_WR_INFLIGHTS */ 22333965Sjdp#define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT 0 22433965Sjdp#define DMA0_CORE_WR_INFLIGHTS_VAL_MASK 0xFFFF 22589857Sobrien 22689857Sobrien/* DMA0_CORE_RD_RATE_LIM_CFG_0 */ 22733965Sjdp#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 22833965Sjdp#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 22933965Sjdp#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 23033965Sjdp#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 23133965Sjdp 23233965Sjdp/* DMA0_CORE_RD_RATE_LIM_CFG_1 */ 23333965Sjdp#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 23433965Sjdp#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF 23533965Sjdp#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT 31 23633965Sjdp#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 23733965Sjdp 23833965Sjdp/* DMA0_CORE_WR_RATE_LIM_CFG_0 */ 23933965Sjdp#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 24033965Sjdp#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 24133965Sjdp#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 24289857Sobrien#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 24389857Sobrien 24489857Sobrien/* DMA0_CORE_WR_RATE_LIM_CFG_1 */ 24589857Sobrien#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 24689857Sobrien#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF 24789857Sobrien#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT 31 24889857Sobrien#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 24989857Sobrien 25089857Sobrien/* DMA0_CORE_ERR_CFG */ 25189857Sobrien#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 25289857Sobrien#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 25389857Sobrien#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 25489857Sobrien#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 25589857Sobrien 25633965Sjdp/* DMA0_CORE_ERR_CAUSE */ 25733965Sjdp#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 25833965Sjdp#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 25933965Sjdp#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 26033965Sjdp#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 26133965Sjdp#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 2 262130561Sobrien#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x4 26333965Sjdp#define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 26433965Sjdp#define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 26533965Sjdp 26633965Sjdp/* DMA0_CORE_ERRMSG_ADDR_LO */ 26733965Sjdp#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 26833965Sjdp#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF 26933965Sjdp 27033965Sjdp/* DMA0_CORE_ERRMSG_ADDR_HI */ 27133965Sjdp#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 27233965Sjdp#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF 27333965Sjdp 27433965Sjdp/* DMA0_CORE_ERRMSG_WDATA */ 27533965Sjdp#define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 27633965Sjdp#define DMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF 27733965Sjdp 27833965Sjdp/* DMA0_CORE_STS0 */ 27933965Sjdp#define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 28033965Sjdp#define DMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF 28133965Sjdp#define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 28233965Sjdp#define DMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 28333965Sjdp#define DMA0_CORE_STS0_BUSY_SHIFT 31 28433965Sjdp#define DMA0_CORE_STS0_BUSY_MASK 0x80000000 28533965Sjdp 28633965Sjdp/* DMA0_CORE_STS1 */ 28733965Sjdp#define DMA0_CORE_STS1_IS_HALT_SHIFT 0 28889857Sobrien#define DMA0_CORE_STS1_IS_HALT_MASK 0x1 28933965Sjdp 29033965Sjdp/* DMA0_CORE_RD_DBGMEM_ADD */ 29133965Sjdp#define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT 0 29233965Sjdp#define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK 0xFFFFFFFF 29333965Sjdp 29433965Sjdp/* DMA0_CORE_RD_DBGMEM_DATA_WR */ 29533965Sjdp#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT 0 29633965Sjdp#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK 0xFFFFFFFF 29733965Sjdp 29833965Sjdp/* DMA0_CORE_RD_DBGMEM_DATA_RD */ 29933965Sjdp#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT 0 30033965Sjdp#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK 0xFFFFFFFF 30133965Sjdp 30233965Sjdp/* DMA0_CORE_RD_DBGMEM_CTRL */ 30333965Sjdp#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT 0 30433965Sjdp#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK 0x1 30533965Sjdp 30633965Sjdp/* DMA0_CORE_RD_DBGMEM_RC */ 30733965Sjdp#define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT 0 30833965Sjdp#define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK 0x1 30933965Sjdp 31033965Sjdp/* DMA0_CORE_DBG_HBW_AXI_AR_CNT */ 31133965Sjdp 31233965Sjdp/* DMA0_CORE_DBG_HBW_AXI_AW_CNT */ 313130561Sobrien 31433965Sjdp/* DMA0_CORE_DBG_LBW_AXI_AW_CNT */ 31533965Sjdp 31699461Sobrien/* DMA0_CORE_DBG_DESC_CNT */ 31733965Sjdp#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT 0 31833965Sjdp#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK 0xFFFFFFFF 31933965Sjdp 32033965Sjdp/* DMA0_CORE_DBG_STS */ 32133965Sjdp#define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 32233965Sjdp#define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 32333965Sjdp#define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 32433965Sjdp#define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 32533965Sjdp#define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 32633965Sjdp#define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 32733965Sjdp#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 32833965Sjdp#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 32933965Sjdp#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 33033965Sjdp#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 33133965Sjdp#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 33233965Sjdp#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 33333965Sjdp#define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 33499461Sobrien#define DMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 33599461Sobrien#define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 33699461Sobrien#define DMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 33799461Sobrien#define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 33833965Sjdp#define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 33999461Sobrien#define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 34099461Sobrien#define DMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 34199461Sobrien#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT 20 34233965Sjdp#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK 0x7FF00000 34333965Sjdp 34433965Sjdp/* DMA0_CORE_DBG_RD_DESC_ID */ 345130561Sobrien 34633965Sjdp/* DMA0_CORE_DBG_WR_DESC_ID */ 347130561Sobrien 34889857Sobrien#endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */ 349130561Sobrien