1/* 2 * This header file contains assembly-language definitions (assembly 3 * macros, etc.) for this specific Xtensa processor's TIE extensions 4 * and options. It is customized to this Xtensa processor configuration. 5 * 6 * This file is subject to the terms and conditions of version 2.1 of the GNU 7 * Lesser General Public License as published by the Free Software Foundation. 8 * 9 * Copyright (C) 1999-2009 Tensilica Inc. 10 */ 11 12#ifndef _XTENSA_CORE_TIE_ASM_H 13#define _XTENSA_CORE_TIE_ASM_H 14 15/* Selection parameter values for save-area save/restore macros: */ 16/* Option vs. TIE: */ 17#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 18#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 19/* Whether used automatically by compiler: */ 20#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 21#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 22/* ABI handling across function calls: */ 23#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 24#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 25#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 26/* Misc */ 27#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 28 29 30 31/* Macro to save all non-coprocessor (extra) custom TIE and optional state 32 * (not including zero-overhead loop registers). 33 * Save area ptr (clobbered): ptr (8 byte aligned) 34 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 35 */ 36 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 37 xchal_sa_start \continue, \ofs 38 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 39 xchal_sa_align \ptr, 0, 1024-4, 4, 4 40 rsr \at1, BR // boolean option 41 s32i \at1, \ptr, .Lxchal_ofs_ + 0 42 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 43 .endif 44 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 45 xchal_sa_align \ptr, 0, 1024-4, 4, 4 46 rsr \at1, SCOMPARE1 // conditional store option 47 s32i \at1, \ptr, .Lxchal_ofs_ + 0 48 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 49 .endif 50 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 51 xchal_sa_align \ptr, 0, 1024-4, 4, 4 52 rur \at1, THREADPTR // threadptr option 53 s32i \at1, \ptr, .Lxchal_ofs_ + 0 54 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 55 .endif 56 .endm // xchal_ncp_store 57 58/* Macro to save all non-coprocessor (extra) custom TIE and optional state 59 * (not including zero-overhead loop registers). 60 * Save area ptr (clobbered): ptr (8 byte aligned) 61 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 62 */ 63 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 64 xchal_sa_start \continue, \ofs 65 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 66 xchal_sa_align \ptr, 0, 1024-4, 4, 4 67 l32i \at1, \ptr, .Lxchal_ofs_ + 0 68 wsr \at1, BR // boolean option 69 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 70 .endif 71 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 72 xchal_sa_align \ptr, 0, 1024-4, 4, 4 73 l32i \at1, \ptr, .Lxchal_ofs_ + 0 74 wsr \at1, SCOMPARE1 // conditional store option 75 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 76 .endif 77 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 78 xchal_sa_align \ptr, 0, 1024-4, 4, 4 79 l32i \at1, \ptr, .Lxchal_ofs_ + 0 80 wur \at1, THREADPTR // threadptr option 81 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 82 .endif 83 .endm // xchal_ncp_load 84 85 86 87#define XCHAL_NCP_NUM_ATMPS 1 88 89 90 91/* Macro to save the state of TIE coprocessor AudioEngineLX. 92 * Save area ptr (clobbered): ptr (8 byte aligned) 93 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP1_NUM_ATMPS needed) 94 */ 95#define xchal_cp_AudioEngineLX_store xchal_cp1_store 96/* #define xchal_cp_AudioEngineLX_store_a2 xchal_cp1_store a2 a3 a4 a5 a6 */ 97 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 98 xchal_sa_start \continue, \ofs 99 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 100 xchal_sa_align \ptr, 0, 0, 1, 8 101 rur240 \at1 // AE_OVF_SAR 102 s32i \at1, \ptr, 0 103 rur241 \at1 // AE_BITHEAD 104 s32i \at1, \ptr, 4 105 rur242 \at1 // AE_TS_FTS_BU_BP 106 s32i \at1, \ptr, 8 107 rur243 \at1 // AE_SD_NO 108 s32i \at1, \ptr, 12 109 AE_SP24X2S.I aep0, \ptr, 16 110 AE_SP24X2S.I aep1, \ptr, 24 111 AE_SP24X2S.I aep2, \ptr, 32 112 AE_SP24X2S.I aep3, \ptr, 40 113 AE_SP24X2S.I aep4, \ptr, 48 114 AE_SP24X2S.I aep5, \ptr, 56 115 addi \ptr, \ptr, 64 116 AE_SP24X2S.I aep6, \ptr, 0 117 AE_SP24X2S.I aep7, \ptr, 8 118 AE_SQ56S.I aeq0, \ptr, 16 119 AE_SQ56S.I aeq1, \ptr, 24 120 AE_SQ56S.I aeq2, \ptr, 32 121 AE_SQ56S.I aeq3, \ptr, 40 122 .set .Lxchal_pofs_, .Lxchal_pofs_ + 64 123 .set .Lxchal_ofs_, .Lxchal_ofs_ + 112 124 .endif 125 .endm // xchal_cp1_store 126 127/* Macro to restore the state of TIE coprocessor AudioEngineLX. 128 * Save area ptr (clobbered): ptr (8 byte aligned) 129 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP1_NUM_ATMPS needed) 130 */ 131#define xchal_cp_AudioEngineLX_load xchal_cp1_load 132/* #define xchal_cp_AudioEngineLX_load_a2 xchal_cp1_load a2 a3 a4 a5 a6 */ 133 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 134 xchal_sa_start \continue, \ofs 135 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 136 xchal_sa_align \ptr, 0, 0, 1, 8 137 l32i \at1, \ptr, 0 138 wur240 \at1 // AE_OVF_SAR 139 l32i \at1, \ptr, 4 140 wur241 \at1 // AE_BITHEAD 141 l32i \at1, \ptr, 8 142 wur242 \at1 // AE_TS_FTS_BU_BP 143 l32i \at1, \ptr, 12 144 wur243 \at1 // AE_SD_NO 145 addi \ptr, \ptr, 80 146 AE_LQ56.I aeq0, \ptr, 0 147 AE_LQ56.I aeq1, \ptr, 8 148 AE_LQ56.I aeq2, \ptr, 16 149 AE_LQ56.I aeq3, \ptr, 24 150 AE_LP24X2.I aep0, \ptr, -64 151 AE_LP24X2.I aep1, \ptr, -56 152 AE_LP24X2.I aep2, \ptr, -48 153 AE_LP24X2.I aep3, \ptr, -40 154 AE_LP24X2.I aep4, \ptr, -32 155 AE_LP24X2.I aep5, \ptr, -24 156 AE_LP24X2.I aep6, \ptr, -16 157 AE_LP24X2.I aep7, \ptr, -8 158 .set .Lxchal_pofs_, .Lxchal_pofs_ + 80 159 .set .Lxchal_ofs_, .Lxchal_ofs_ + 112 160 .endif 161 .endm // xchal_cp1_load 162 163#define XCHAL_CP1_NUM_ATMPS 1 164#define XCHAL_SA_NUM_ATMPS 1 165 166 /* Empty macros for unconfigured coprocessors: */ 167 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 168 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 169 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 170 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 171 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 172 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 173 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 174 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 175 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 176 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 177 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 178 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 179 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 180 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 181 182#endif /*_XTENSA_CORE_TIE_ASM_H*/ 183