1/*
2 * Xtensa MX interrupt distributor
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2008 - 2013 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_MXREGS_H
12#define _XTENSA_MXREGS_H
13
14/*
15 * RER/WER at, as	Read/write external register
16 *	at: value
17 *	as: address
18 *
19 * Address	Value
20 * 00nn		0...0p..p	Interrupt Routing, route IRQ n to processor p
21 * 01pp		0...0d..d	16 bits (d) 'ored' as single IPI to processor p
22 * 0180		0...0m..m	Clear enable specified by mask (m)
23 * 0184		0...0m..m	Set enable specified by mask (m)
24 * 0190		0...0x..x	8-bit IPI partition register
25 *				VVVVVVVVPPPPUUUUUUUUUUUUUUUUU
26 *				V (10-bit) Release/Version
27 *				P ( 4-bit) Number of cores - 1
28 *				U (18-bit) ID
29 * 01a0		i.......i	32-bit ConfigID
30 * 0200		0...0m..m	RunStall core 'n'
31 * 0220		c		Cache coherency enabled
32 */
33
34#define MIROUT(irq)	(0x000 + (irq))
35#define MIPICAUSE(cpu)	(0x100 + (cpu))
36#define MIPISET(cause)	(0x140 + (cause))
37#define MIENG		0x180
38#define MIENGSET	0x184
39#define MIASG		0x188	/* Read Global Assert Register */
40#define MIASGSET	0x18c	/* Set Global Addert Regiter */
41#define MIPIPART	0x190
42#define SYSCFGID	0x1a0
43#define MPSCORE		0x200
44#define CCON		0x220
45
46#endif /* _XTENSA_MXREGS_H */
47