1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Core of Xen paravirt_ops implementation. 4 * 5 * This file contains the xen_paravirt_ops structure itself, and the 6 * implementations for: 7 * - privileged instructions 8 * - interrupt flags 9 * - segment operations 10 * - booting and setup 11 * 12 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 13 */ 14 15#include <linux/cpu.h> 16#include <linux/kernel.h> 17#include <linux/init.h> 18#include <linux/smp.h> 19#include <linux/preempt.h> 20#include <linux/hardirq.h> 21#include <linux/percpu.h> 22#include <linux/delay.h> 23#include <linux/start_kernel.h> 24#include <linux/sched.h> 25#include <linux/kprobes.h> 26#include <linux/kstrtox.h> 27#include <linux/memblock.h> 28#include <linux/export.h> 29#include <linux/mm.h> 30#include <linux/page-flags.h> 31#include <linux/pci.h> 32#include <linux/gfp.h> 33#include <linux/edd.h> 34#include <linux/reboot.h> 35#include <linux/virtio_anchor.h> 36#include <linux/stackprotector.h> 37 38#include <xen/xen.h> 39#include <xen/events.h> 40#include <xen/interface/xen.h> 41#include <xen/interface/version.h> 42#include <xen/interface/physdev.h> 43#include <xen/interface/vcpu.h> 44#include <xen/interface/memory.h> 45#include <xen/interface/nmi.h> 46#include <xen/interface/xen-mca.h> 47#include <xen/features.h> 48#include <xen/page.h> 49#include <xen/hvc-console.h> 50#include <xen/acpi.h> 51 52#include <asm/paravirt.h> 53#include <asm/apic.h> 54#include <asm/page.h> 55#include <asm/xen/pci.h> 56#include <asm/xen/hypercall.h> 57#include <asm/xen/hypervisor.h> 58#include <asm/xen/cpuid.h> 59#include <asm/fixmap.h> 60#include <asm/processor.h> 61#include <asm/proto.h> 62#include <asm/msr-index.h> 63#include <asm/traps.h> 64#include <asm/setup.h> 65#include <asm/desc.h> 66#include <asm/pgalloc.h> 67#include <asm/tlbflush.h> 68#include <asm/reboot.h> 69#include <asm/hypervisor.h> 70#include <asm/mach_traps.h> 71#include <asm/mtrr.h> 72#include <asm/mwait.h> 73#include <asm/pci_x86.h> 74#include <asm/cpu.h> 75#ifdef CONFIG_X86_IOPL_IOPERM 76#include <asm/io_bitmap.h> 77#endif 78 79#ifdef CONFIG_ACPI 80#include <linux/acpi.h> 81#include <asm/acpi.h> 82#include <acpi/proc_cap_intel.h> 83#include <acpi/processor.h> 84#include <xen/interface/platform.h> 85#endif 86 87#include "xen-ops.h" 88#include "mmu.h" 89#include "smp.h" 90#include "multicalls.h" 91#include "pmu.h" 92 93#include "../kernel/cpu/cpu.h" /* get_cpu_cap() */ 94 95void *xen_initial_gdt; 96 97static int xen_cpu_up_prepare_pv(unsigned int cpu); 98static int xen_cpu_dead_pv(unsigned int cpu); 99 100struct tls_descs { 101 struct desc_struct desc[3]; 102}; 103 104DEFINE_PER_CPU(enum xen_lazy_mode, xen_lazy_mode) = XEN_LAZY_NONE; 105DEFINE_PER_CPU(unsigned int, xen_lazy_nesting); 106 107enum xen_lazy_mode xen_get_lazy_mode(void) 108{ 109 if (in_interrupt()) 110 return XEN_LAZY_NONE; 111 112 return this_cpu_read(xen_lazy_mode); 113} 114 115/* 116 * Updating the 3 TLS descriptors in the GDT on every task switch is 117 * surprisingly expensive so we avoid updating them if they haven't 118 * changed. Since Xen writes different descriptors than the one 119 * passed in the update_descriptor hypercall we keep shadow copies to 120 * compare against. 121 */ 122static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); 123 124static __read_mostly bool xen_msr_safe = IS_ENABLED(CONFIG_XEN_PV_MSR_SAFE); 125 126static int __init parse_xen_msr_safe(char *str) 127{ 128 if (str) 129 return kstrtobool(str, &xen_msr_safe); 130 return -EINVAL; 131} 132early_param("xen_msr_safe", parse_xen_msr_safe); 133 134/* Get MTRR settings from Xen and put them into mtrr_state. */ 135static void __init xen_set_mtrr_data(void) 136{ 137#ifdef CONFIG_MTRR 138 struct xen_platform_op op = { 139 .cmd = XENPF_read_memtype, 140 .interface_version = XENPF_INTERFACE_VERSION, 141 }; 142 unsigned int reg; 143 unsigned long mask; 144 uint32_t eax, width; 145 static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata; 146 147 /* Get physical address width (only 64-bit cpus supported). */ 148 width = 36; 149 eax = cpuid_eax(0x80000000); 150 if ((eax >> 16) == 0x8000 && eax >= 0x80000008) { 151 eax = cpuid_eax(0x80000008); 152 width = eax & 0xff; 153 } 154 155 for (reg = 0; reg < MTRR_MAX_VAR_RANGES; reg++) { 156 op.u.read_memtype.reg = reg; 157 if (HYPERVISOR_platform_op(&op)) 158 break; 159 160 /* 161 * Only called in dom0, which has all RAM PFNs mapped at 162 * RAM MFNs, and all PCI space etc. is identity mapped. 163 * This means we can treat MFN == PFN regarding MTRR settings. 164 */ 165 var[reg].base_lo = op.u.read_memtype.type; 166 var[reg].base_lo |= op.u.read_memtype.mfn << PAGE_SHIFT; 167 var[reg].base_hi = op.u.read_memtype.mfn >> (32 - PAGE_SHIFT); 168 mask = ~((op.u.read_memtype.nr_mfns << PAGE_SHIFT) - 1); 169 mask &= (1UL << width) - 1; 170 if (mask) 171 mask |= MTRR_PHYSMASK_V; 172 var[reg].mask_lo = mask; 173 var[reg].mask_hi = mask >> 32; 174 } 175 176 /* Only overwrite MTRR state if any MTRR could be got from Xen. */ 177 if (reg) 178 mtrr_overwrite_state(var, reg, MTRR_TYPE_UNCACHABLE); 179#endif 180} 181 182static void __init xen_pv_init_platform(void) 183{ 184 /* PV guests can't operate virtio devices without grants. */ 185 if (IS_ENABLED(CONFIG_XEN_VIRTIO)) 186 virtio_set_mem_acc_cb(xen_virtio_restricted_mem_acc); 187 188 populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP)); 189 190 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info); 191 HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); 192 193 /* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */ 194 xen_vcpu_info_reset(0); 195 196 /* pvclock is in shared info area */ 197 xen_init_time_ops(); 198 199 if (xen_initial_domain()) 200 xen_set_mtrr_data(); 201 else 202 mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK); 203 204 /* Adjust nr_cpu_ids before "enumeration" happens */ 205 xen_smp_count_cpus(); 206} 207 208static void __init xen_pv_guest_late_init(void) 209{ 210#ifndef CONFIG_SMP 211 /* Setup shared vcpu info for non-smp configurations */ 212 xen_setup_vcpu_info_placement(); 213#endif 214} 215 216static __read_mostly unsigned int cpuid_leaf5_ecx_val; 217static __read_mostly unsigned int cpuid_leaf5_edx_val; 218 219static void xen_cpuid(unsigned int *ax, unsigned int *bx, 220 unsigned int *cx, unsigned int *dx) 221{ 222 unsigned maskebx = ~0; 223 224 /* 225 * Mask out inconvenient features, to try and disable as many 226 * unsupported kernel subsystems as possible. 227 */ 228 switch (*ax) { 229 case CPUID_MWAIT_LEAF: 230 /* Synthesize the values.. */ 231 *ax = 0; 232 *bx = 0; 233 *cx = cpuid_leaf5_ecx_val; 234 *dx = cpuid_leaf5_edx_val; 235 return; 236 237 case 0xb: 238 /* Suppress extended topology stuff */ 239 maskebx = 0; 240 break; 241 } 242 243 asm(XEN_EMULATE_PREFIX "cpuid" 244 : "=a" (*ax), 245 "=b" (*bx), 246 "=c" (*cx), 247 "=d" (*dx) 248 : "0" (*ax), "2" (*cx)); 249 250 *bx &= maskebx; 251} 252 253static bool __init xen_check_mwait(void) 254{ 255#ifdef CONFIG_ACPI 256 struct xen_platform_op op = { 257 .cmd = XENPF_set_processor_pminfo, 258 .u.set_pminfo.id = -1, 259 .u.set_pminfo.type = XEN_PM_PDC, 260 }; 261 uint32_t buf[3]; 262 unsigned int ax, bx, cx, dx; 263 unsigned int mwait_mask; 264 265 /* We need to determine whether it is OK to expose the MWAIT 266 * capability to the kernel to harvest deeper than C3 states from ACPI 267 * _CST using the processor_harvest_xen.c module. For this to work, we 268 * need to gather the MWAIT_LEAF values (which the cstate.c code 269 * checks against). The hypervisor won't expose the MWAIT flag because 270 * it would break backwards compatibility; so we will find out directly 271 * from the hardware and hypercall. 272 */ 273 if (!xen_initial_domain()) 274 return false; 275 276 /* 277 * When running under platform earlier than Xen4.2, do not expose 278 * mwait, to avoid the risk of loading native acpi pad driver 279 */ 280 if (!xen_running_on_version_or_later(4, 2)) 281 return false; 282 283 ax = 1; 284 cx = 0; 285 286 native_cpuid(&ax, &bx, &cx, &dx); 287 288 mwait_mask = (1 << (X86_FEATURE_EST % 32)) | 289 (1 << (X86_FEATURE_MWAIT % 32)); 290 291 if ((cx & mwait_mask) != mwait_mask) 292 return false; 293 294 /* We need to emulate the MWAIT_LEAF and for that we need both 295 * ecx and edx. The hypercall provides only partial information. 296 */ 297 298 ax = CPUID_MWAIT_LEAF; 299 bx = 0; 300 cx = 0; 301 dx = 0; 302 303 native_cpuid(&ax, &bx, &cx, &dx); 304 305 /* Ask the Hypervisor whether to clear ACPI_PROC_CAP_C_C2C3_FFH. If so, 306 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. 307 */ 308 buf[0] = ACPI_PDC_REVISION_ID; 309 buf[1] = 1; 310 buf[2] = (ACPI_PROC_CAP_C_CAPABILITY_SMP | ACPI_PROC_CAP_EST_CAPABILITY_SWSMP); 311 312 set_xen_guest_handle(op.u.set_pminfo.pdc, buf); 313 314 if ((HYPERVISOR_platform_op(&op) == 0) && 315 (buf[2] & (ACPI_PROC_CAP_C_C1_FFH | ACPI_PROC_CAP_C_C2C3_FFH))) { 316 cpuid_leaf5_ecx_val = cx; 317 cpuid_leaf5_edx_val = dx; 318 } 319 return true; 320#else 321 return false; 322#endif 323} 324 325static bool __init xen_check_xsave(void) 326{ 327 unsigned int cx, xsave_mask; 328 329 cx = cpuid_ecx(1); 330 331 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) | 332 (1 << (X86_FEATURE_OSXSAVE % 32)); 333 334 /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ 335 return (cx & xsave_mask) == xsave_mask; 336} 337 338static void __init xen_init_capabilities(void) 339{ 340 setup_force_cpu_cap(X86_FEATURE_XENPV); 341 setup_clear_cpu_cap(X86_FEATURE_DCA); 342 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF); 343 setup_clear_cpu_cap(X86_FEATURE_MTRR); 344 setup_clear_cpu_cap(X86_FEATURE_ACC); 345 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 346 setup_clear_cpu_cap(X86_FEATURE_SME); 347 setup_clear_cpu_cap(X86_FEATURE_LKGS); 348 349 /* 350 * Xen PV would need some work to support PCID: CR3 handling as well 351 * as xen_flush_tlb_others() would need updating. 352 */ 353 setup_clear_cpu_cap(X86_FEATURE_PCID); 354 355 if (!xen_initial_domain()) 356 setup_clear_cpu_cap(X86_FEATURE_ACPI); 357 358 if (xen_check_mwait()) 359 setup_force_cpu_cap(X86_FEATURE_MWAIT); 360 else 361 setup_clear_cpu_cap(X86_FEATURE_MWAIT); 362 363 if (!xen_check_xsave()) { 364 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 365 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE); 366 } 367} 368 369static noinstr void xen_set_debugreg(int reg, unsigned long val) 370{ 371 HYPERVISOR_set_debugreg(reg, val); 372} 373 374static noinstr unsigned long xen_get_debugreg(int reg) 375{ 376 return HYPERVISOR_get_debugreg(reg); 377} 378 379static void xen_start_context_switch(struct task_struct *prev) 380{ 381 BUG_ON(preemptible()); 382 383 if (this_cpu_read(xen_lazy_mode) == XEN_LAZY_MMU) { 384 arch_leave_lazy_mmu_mode(); 385 set_ti_thread_flag(task_thread_info(prev), TIF_LAZY_MMU_UPDATES); 386 } 387 enter_lazy(XEN_LAZY_CPU); 388} 389 390static void xen_end_context_switch(struct task_struct *next) 391{ 392 BUG_ON(preemptible()); 393 394 xen_mc_flush(); 395 leave_lazy(XEN_LAZY_CPU); 396 if (test_and_clear_ti_thread_flag(task_thread_info(next), TIF_LAZY_MMU_UPDATES)) 397 arch_enter_lazy_mmu_mode(); 398} 399 400static unsigned long xen_store_tr(void) 401{ 402 return 0; 403} 404 405/* 406 * Set the page permissions for a particular virtual address. If the 407 * address is a vmalloc mapping (or other non-linear mapping), then 408 * find the linear mapping of the page and also set its protections to 409 * match. 410 */ 411static void set_aliased_prot(void *v, pgprot_t prot) 412{ 413 int level; 414 pte_t *ptep; 415 pte_t pte; 416 unsigned long pfn; 417 unsigned char dummy; 418 void *va; 419 420 ptep = lookup_address((unsigned long)v, &level); 421 BUG_ON(ptep == NULL); 422 423 pfn = pte_pfn(*ptep); 424 pte = pfn_pte(pfn, prot); 425 426 /* 427 * Careful: update_va_mapping() will fail if the virtual address 428 * we're poking isn't populated in the page tables. We don't 429 * need to worry about the direct map (that's always in the page 430 * tables), but we need to be careful about vmap space. In 431 * particular, the top level page table can lazily propagate 432 * entries between processes, so if we've switched mms since we 433 * vmapped the target in the first place, we might not have the 434 * top-level page table entry populated. 435 * 436 * We disable preemption because we want the same mm active when 437 * we probe the target and when we issue the hypercall. We'll 438 * have the same nominal mm, but if we're a kernel thread, lazy 439 * mm dropping could change our pgd. 440 * 441 * Out of an abundance of caution, this uses __get_user() to fault 442 * in the target address just in case there's some obscure case 443 * in which the target address isn't readable. 444 */ 445 446 preempt_disable(); 447 448 copy_from_kernel_nofault(&dummy, v, 1); 449 450 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) 451 BUG(); 452 453 va = __va(PFN_PHYS(pfn)); 454 455 if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 456 BUG(); 457 458 preempt_enable(); 459} 460 461static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) 462{ 463 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 464 int i; 465 466 /* 467 * We need to mark the all aliases of the LDT pages RO. We 468 * don't need to call vm_flush_aliases(), though, since that's 469 * only responsible for flushing aliases out the TLBs, not the 470 * page tables, and Xen will flush the TLB for us if needed. 471 * 472 * To avoid confusing future readers: none of this is necessary 473 * to load the LDT. The hypervisor only checks this when the 474 * LDT is faulted in due to subsequent descriptor access. 475 */ 476 477 for (i = 0; i < entries; i += entries_per_page) 478 set_aliased_prot(ldt + i, PAGE_KERNEL_RO); 479} 480 481static void xen_free_ldt(struct desc_struct *ldt, unsigned entries) 482{ 483 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 484 int i; 485 486 for (i = 0; i < entries; i += entries_per_page) 487 set_aliased_prot(ldt + i, PAGE_KERNEL); 488} 489 490static void xen_set_ldt(const void *addr, unsigned entries) 491{ 492 struct mmuext_op *op; 493 struct multicall_space mcs = xen_mc_entry(sizeof(*op)); 494 495 trace_xen_cpu_set_ldt(addr, entries); 496 497 op = mcs.args; 498 op->cmd = MMUEXT_SET_LDT; 499 op->arg1.linear_addr = (unsigned long)addr; 500 op->arg2.nr_ents = entries; 501 502 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF); 503 504 xen_mc_issue(XEN_LAZY_CPU); 505} 506 507static void xen_load_gdt(const struct desc_ptr *dtr) 508{ 509 unsigned long va = dtr->address; 510 unsigned int size = dtr->size + 1; 511 unsigned long pfn, mfn; 512 int level; 513 pte_t *ptep; 514 void *virt; 515 516 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 517 BUG_ON(size > PAGE_SIZE); 518 BUG_ON(va & ~PAGE_MASK); 519 520 /* 521 * The GDT is per-cpu and is in the percpu data area. 522 * That can be virtually mapped, so we need to do a 523 * page-walk to get the underlying MFN for the 524 * hypercall. The page can also be in the kernel's 525 * linear range, so we need to RO that mapping too. 526 */ 527 ptep = lookup_address(va, &level); 528 BUG_ON(ptep == NULL); 529 530 pfn = pte_pfn(*ptep); 531 mfn = pfn_to_mfn(pfn); 532 virt = __va(PFN_PHYS(pfn)); 533 534 make_lowmem_page_readonly((void *)va); 535 make_lowmem_page_readonly(virt); 536 537 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 538 BUG(); 539} 540 541/* 542 * load_gdt for early boot, when the gdt is only mapped once 543 */ 544static void __init xen_load_gdt_boot(const struct desc_ptr *dtr) 545{ 546 unsigned long va = dtr->address; 547 unsigned int size = dtr->size + 1; 548 unsigned long pfn, mfn; 549 pte_t pte; 550 551 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 552 BUG_ON(size > PAGE_SIZE); 553 BUG_ON(va & ~PAGE_MASK); 554 555 pfn = virt_to_pfn((void *)va); 556 mfn = pfn_to_mfn(pfn); 557 558 pte = pfn_pte(pfn, PAGE_KERNEL_RO); 559 560 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 561 BUG(); 562 563 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 564 BUG(); 565} 566 567static inline bool desc_equal(const struct desc_struct *d1, 568 const struct desc_struct *d2) 569{ 570 return !memcmp(d1, d2, sizeof(*d1)); 571} 572 573static void load_TLS_descriptor(struct thread_struct *t, 574 unsigned int cpu, unsigned int i) 575{ 576 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i]; 577 struct desc_struct *gdt; 578 xmaddr_t maddr; 579 struct multicall_space mc; 580 581 if (desc_equal(shadow, &t->tls_array[i])) 582 return; 583 584 *shadow = t->tls_array[i]; 585 586 gdt = get_cpu_gdt_rw(cpu); 587 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); 588 mc = __xen_mc_entry(0); 589 590 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); 591} 592 593static void xen_load_tls(struct thread_struct *t, unsigned int cpu) 594{ 595 /* 596 * In lazy mode we need to zero %fs, otherwise we may get an 597 * exception between the new %fs descriptor being loaded and 598 * %fs being effectively cleared at __switch_to(). 599 */ 600 if (xen_get_lazy_mode() == XEN_LAZY_CPU) 601 loadsegment(fs, 0); 602 603 xen_mc_batch(); 604 605 load_TLS_descriptor(t, cpu, 0); 606 load_TLS_descriptor(t, cpu, 1); 607 load_TLS_descriptor(t, cpu, 2); 608 609 xen_mc_issue(XEN_LAZY_CPU); 610} 611 612static void xen_load_gs_index(unsigned int idx) 613{ 614 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx)) 615 BUG(); 616} 617 618static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum, 619 const void *ptr) 620{ 621 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]); 622 u64 entry = *(u64 *)ptr; 623 624 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry); 625 626 preempt_disable(); 627 628 xen_mc_flush(); 629 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry)) 630 BUG(); 631 632 preempt_enable(); 633} 634 635void noist_exc_debug(struct pt_regs *regs); 636 637DEFINE_IDTENTRY_RAW(xenpv_exc_nmi) 638{ 639 /* On Xen PV, NMI doesn't use IST. The C part is the same as native. */ 640 exc_nmi(regs); 641} 642 643DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault) 644{ 645 /* On Xen PV, DF doesn't use IST. The C part is the same as native. */ 646 exc_double_fault(regs, error_code); 647} 648 649DEFINE_IDTENTRY_RAW(xenpv_exc_debug) 650{ 651 /* 652 * There's no IST on Xen PV, but we still need to dispatch 653 * to the correct handler. 654 */ 655 if (user_mode(regs)) 656 noist_exc_debug(regs); 657 else 658 exc_debug(regs); 659} 660 661DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap) 662{ 663 /* This should never happen and there is no way to handle it. */ 664 instrumentation_begin(); 665 pr_err("Unknown trap in Xen PV mode."); 666 BUG(); 667 instrumentation_end(); 668} 669 670#ifdef CONFIG_X86_MCE 671DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check) 672{ 673 /* 674 * There's no IST on Xen PV, but we still need to dispatch 675 * to the correct handler. 676 */ 677 if (user_mode(regs)) 678 noist_exc_machine_check(regs); 679 else 680 exc_machine_check(regs); 681} 682#endif 683 684struct trap_array_entry { 685 void (*orig)(void); 686 void (*xen)(void); 687 bool ist_okay; 688}; 689 690#define TRAP_ENTRY(func, ist_ok) { \ 691 .orig = asm_##func, \ 692 .xen = xen_asm_##func, \ 693 .ist_okay = ist_ok } 694 695#define TRAP_ENTRY_REDIR(func, ist_ok) { \ 696 .orig = asm_##func, \ 697 .xen = xen_asm_xenpv_##func, \ 698 .ist_okay = ist_ok } 699 700static struct trap_array_entry trap_array[] = { 701 TRAP_ENTRY_REDIR(exc_debug, true ), 702 TRAP_ENTRY_REDIR(exc_double_fault, true ), 703#ifdef CONFIG_X86_MCE 704 TRAP_ENTRY_REDIR(exc_machine_check, true ), 705#endif 706 TRAP_ENTRY_REDIR(exc_nmi, true ), 707 TRAP_ENTRY(exc_int3, false ), 708 TRAP_ENTRY(exc_overflow, false ), 709#ifdef CONFIG_IA32_EMULATION 710 TRAP_ENTRY(int80_emulation, false ), 711#endif 712 TRAP_ENTRY(exc_page_fault, false ), 713 TRAP_ENTRY(exc_divide_error, false ), 714 TRAP_ENTRY(exc_bounds, false ), 715 TRAP_ENTRY(exc_invalid_op, false ), 716 TRAP_ENTRY(exc_device_not_available, false ), 717 TRAP_ENTRY(exc_coproc_segment_overrun, false ), 718 TRAP_ENTRY(exc_invalid_tss, false ), 719 TRAP_ENTRY(exc_segment_not_present, false ), 720 TRAP_ENTRY(exc_stack_segment, false ), 721 TRAP_ENTRY(exc_general_protection, false ), 722 TRAP_ENTRY(exc_spurious_interrupt_bug, false ), 723 TRAP_ENTRY(exc_coprocessor_error, false ), 724 TRAP_ENTRY(exc_alignment_check, false ), 725 TRAP_ENTRY(exc_simd_coprocessor_error, false ), 726#ifdef CONFIG_X86_CET 727 TRAP_ENTRY(exc_control_protection, false ), 728#endif 729}; 730 731static bool __ref get_trap_addr(void **addr, unsigned int ist) 732{ 733 unsigned int nr; 734 bool ist_okay = false; 735 bool found = false; 736 737 /* 738 * Replace trap handler addresses by Xen specific ones. 739 * Check for known traps using IST and whitelist them. 740 * The debugger ones are the only ones we care about. 741 * Xen will handle faults like double_fault, so we should never see 742 * them. Warn if there's an unexpected IST-using fault handler. 743 */ 744 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) { 745 struct trap_array_entry *entry = trap_array + nr; 746 747 if (*addr == entry->orig) { 748 *addr = entry->xen; 749 ist_okay = entry->ist_okay; 750 found = true; 751 break; 752 } 753 } 754 755 if (nr == ARRAY_SIZE(trap_array) && 756 *addr >= (void *)early_idt_handler_array[0] && 757 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { 758 nr = (*addr - (void *)early_idt_handler_array[0]) / 759 EARLY_IDT_HANDLER_SIZE; 760 *addr = (void *)xen_early_idt_handler_array[nr]; 761 found = true; 762 } 763 764 if (!found) 765 *addr = (void *)xen_asm_exc_xen_unknown_trap; 766 767 if (WARN_ON(found && ist != 0 && !ist_okay)) 768 return false; 769 770 return true; 771} 772 773static int cvt_gate_to_trap(int vector, const gate_desc *val, 774 struct trap_info *info) 775{ 776 unsigned long addr; 777 778 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT) 779 return 0; 780 781 info->vector = vector; 782 783 addr = gate_offset(val); 784 if (!get_trap_addr((void **)&addr, val->bits.ist)) 785 return 0; 786 info->address = addr; 787 788 info->cs = gate_segment(val); 789 info->flags = val->bits.dpl; 790 /* interrupt gates clear IF */ 791 if (val->bits.type == GATE_INTERRUPT) 792 info->flags |= 1 << 2; 793 794 return 1; 795} 796 797/* Locations of each CPU's IDT */ 798static DEFINE_PER_CPU(struct desc_ptr, idt_desc); 799 800/* Set an IDT entry. If the entry is part of the current IDT, then 801 also update Xen. */ 802static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) 803{ 804 unsigned long p = (unsigned long)&dt[entrynum]; 805 unsigned long start, end; 806 807 trace_xen_cpu_write_idt_entry(dt, entrynum, g); 808 809 preempt_disable(); 810 811 start = __this_cpu_read(idt_desc.address); 812 end = start + __this_cpu_read(idt_desc.size) + 1; 813 814 xen_mc_flush(); 815 816 native_write_idt_entry(dt, entrynum, g); 817 818 if (p >= start && (p + 8) <= end) { 819 struct trap_info info[2]; 820 821 info[1].address = 0; 822 823 if (cvt_gate_to_trap(entrynum, g, &info[0])) 824 if (HYPERVISOR_set_trap_table(info)) 825 BUG(); 826 } 827 828 preempt_enable(); 829} 830 831static unsigned xen_convert_trap_info(const struct desc_ptr *desc, 832 struct trap_info *traps, bool full) 833{ 834 unsigned in, out, count; 835 836 count = (desc->size+1) / sizeof(gate_desc); 837 BUG_ON(count > 256); 838 839 for (in = out = 0; in < count; in++) { 840 gate_desc *entry = (gate_desc *)(desc->address) + in; 841 842 if (cvt_gate_to_trap(in, entry, &traps[out]) || full) 843 out++; 844 } 845 846 return out; 847} 848 849void xen_copy_trap_info(struct trap_info *traps) 850{ 851 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc); 852 853 xen_convert_trap_info(desc, traps, true); 854} 855 856/* Load a new IDT into Xen. In principle this can be per-CPU, so we 857 hold a spinlock to protect the static traps[] array (static because 858 it avoids allocation, and saves stack space). */ 859static void xen_load_idt(const struct desc_ptr *desc) 860{ 861 static DEFINE_SPINLOCK(lock); 862 static struct trap_info traps[257]; 863 static const struct trap_info zero = { }; 864 unsigned out; 865 866 trace_xen_cpu_load_idt(desc); 867 868 spin_lock(&lock); 869 870 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); 871 872 out = xen_convert_trap_info(desc, traps, false); 873 traps[out] = zero; 874 875 xen_mc_flush(); 876 if (HYPERVISOR_set_trap_table(traps)) 877 BUG(); 878 879 spin_unlock(&lock); 880} 881 882/* Write a GDT descriptor entry. Ignore LDT descriptors, since 883 they're handled differently. */ 884static void xen_write_gdt_entry(struct desc_struct *dt, int entry, 885 const void *desc, int type) 886{ 887 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 888 889 preempt_disable(); 890 891 switch (type) { 892 case DESC_LDT: 893 case DESC_TSS: 894 /* ignore */ 895 break; 896 897 default: { 898 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]); 899 900 xen_mc_flush(); 901 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 902 BUG(); 903 } 904 905 } 906 907 preempt_enable(); 908} 909 910/* 911 * Version of write_gdt_entry for use at early boot-time needed to 912 * update an entry as simply as possible. 913 */ 914static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry, 915 const void *desc, int type) 916{ 917 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 918 919 switch (type) { 920 case DESC_LDT: 921 case DESC_TSS: 922 /* ignore */ 923 break; 924 925 default: { 926 xmaddr_t maddr = virt_to_machine(&dt[entry]); 927 928 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 929 dt[entry] = *(struct desc_struct *)desc; 930 } 931 932 } 933} 934 935static void xen_load_sp0(unsigned long sp0) 936{ 937 struct multicall_space mcs; 938 939 mcs = xen_mc_entry(0); 940 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0); 941 xen_mc_issue(XEN_LAZY_CPU); 942 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 943} 944 945#ifdef CONFIG_X86_IOPL_IOPERM 946static void xen_invalidate_io_bitmap(void) 947{ 948 struct physdev_set_iobitmap iobitmap = { 949 .bitmap = NULL, 950 .nr_ports = 0, 951 }; 952 953 native_tss_invalidate_io_bitmap(); 954 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 955} 956 957static void xen_update_io_bitmap(void) 958{ 959 struct physdev_set_iobitmap iobitmap; 960 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 961 962 native_tss_update_io_bitmap(); 963 964 iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) + 965 tss->x86_tss.io_bitmap_base; 966 if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID) 967 iobitmap.nr_ports = 0; 968 else 969 iobitmap.nr_ports = IO_BITMAP_BITS; 970 971 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 972} 973#endif 974 975static void xen_io_delay(void) 976{ 977} 978 979static DEFINE_PER_CPU(unsigned long, xen_cr0_value); 980 981static unsigned long xen_read_cr0(void) 982{ 983 unsigned long cr0 = this_cpu_read(xen_cr0_value); 984 985 if (unlikely(cr0 == 0)) { 986 cr0 = native_read_cr0(); 987 this_cpu_write(xen_cr0_value, cr0); 988 } 989 990 return cr0; 991} 992 993static void xen_write_cr0(unsigned long cr0) 994{ 995 struct multicall_space mcs; 996 997 this_cpu_write(xen_cr0_value, cr0); 998 999 /* Only pay attention to cr0.TS; everything else is 1000 ignored. */ 1001 mcs = xen_mc_entry(0); 1002 1003 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0); 1004 1005 xen_mc_issue(XEN_LAZY_CPU); 1006} 1007 1008static void xen_write_cr4(unsigned long cr4) 1009{ 1010 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE); 1011 1012 native_write_cr4(cr4); 1013} 1014 1015static u64 xen_do_read_msr(unsigned int msr, int *err) 1016{ 1017 u64 val = 0; /* Avoid uninitialized value for safe variant. */ 1018 1019 if (pmu_msr_read(msr, &val, err)) 1020 return val; 1021 1022 if (err) 1023 val = native_read_msr_safe(msr, err); 1024 else 1025 val = native_read_msr(msr); 1026 1027 switch (msr) { 1028 case MSR_IA32_APICBASE: 1029 val &= ~X2APIC_ENABLE; 1030 break; 1031 } 1032 return val; 1033} 1034 1035static void set_seg(unsigned int which, unsigned int low, unsigned int high, 1036 int *err) 1037{ 1038 u64 base = ((u64)high << 32) | low; 1039 1040 if (HYPERVISOR_set_segment_base(which, base) == 0) 1041 return; 1042 1043 if (err) 1044 *err = -EIO; 1045 else 1046 WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base); 1047} 1048 1049/* 1050 * Support write_msr_safe() and write_msr() semantics. 1051 * With err == NULL write_msr() semantics are selected. 1052 * Supplying an err pointer requires err to be pre-initialized with 0. 1053 */ 1054static void xen_do_write_msr(unsigned int msr, unsigned int low, 1055 unsigned int high, int *err) 1056{ 1057 switch (msr) { 1058 case MSR_FS_BASE: 1059 set_seg(SEGBASE_FS, low, high, err); 1060 break; 1061 1062 case MSR_KERNEL_GS_BASE: 1063 set_seg(SEGBASE_GS_USER, low, high, err); 1064 break; 1065 1066 case MSR_GS_BASE: 1067 set_seg(SEGBASE_GS_KERNEL, low, high, err); 1068 break; 1069 1070 case MSR_STAR: 1071 case MSR_CSTAR: 1072 case MSR_LSTAR: 1073 case MSR_SYSCALL_MASK: 1074 case MSR_IA32_SYSENTER_CS: 1075 case MSR_IA32_SYSENTER_ESP: 1076 case MSR_IA32_SYSENTER_EIP: 1077 /* Fast syscall setup is all done in hypercalls, so 1078 these are all ignored. Stub them out here to stop 1079 Xen console noise. */ 1080 break; 1081 1082 default: 1083 if (!pmu_msr_write(msr, low, high, err)) { 1084 if (err) 1085 *err = native_write_msr_safe(msr, low, high); 1086 else 1087 native_write_msr(msr, low, high); 1088 } 1089 } 1090} 1091 1092static u64 xen_read_msr_safe(unsigned int msr, int *err) 1093{ 1094 return xen_do_read_msr(msr, err); 1095} 1096 1097static int xen_write_msr_safe(unsigned int msr, unsigned int low, 1098 unsigned int high) 1099{ 1100 int err = 0; 1101 1102 xen_do_write_msr(msr, low, high, &err); 1103 1104 return err; 1105} 1106 1107static u64 xen_read_msr(unsigned int msr) 1108{ 1109 int err; 1110 1111 return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); 1112} 1113 1114static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) 1115{ 1116 int err; 1117 1118 xen_do_write_msr(msr, low, high, xen_msr_safe ? &err : NULL); 1119} 1120 1121/* This is called once we have the cpu_possible_mask */ 1122void __init xen_setup_vcpu_info_placement(void) 1123{ 1124 int cpu; 1125 1126 for_each_possible_cpu(cpu) { 1127 /* Set up direct vCPU id mapping for PV guests. */ 1128 per_cpu(xen_vcpu_id, cpu) = cpu; 1129 xen_vcpu_setup(cpu); 1130 } 1131 1132 pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct); 1133 pv_ops.irq.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); 1134 pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); 1135 pv_ops.mmu.read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2_direct); 1136} 1137 1138static const struct pv_info xen_info __initconst = { 1139 .extra_user_64bit_cs = FLAT_USER_CS64, 1140 .name = "Xen", 1141}; 1142 1143static const typeof(pv_ops) xen_cpu_ops __initconst = { 1144 .cpu = { 1145 .cpuid = xen_cpuid, 1146 1147 .set_debugreg = xen_set_debugreg, 1148 .get_debugreg = xen_get_debugreg, 1149 1150 .read_cr0 = xen_read_cr0, 1151 .write_cr0 = xen_write_cr0, 1152 1153 .write_cr4 = xen_write_cr4, 1154 1155 .wbinvd = pv_native_wbinvd, 1156 1157 .read_msr = xen_read_msr, 1158 .write_msr = xen_write_msr, 1159 1160 .read_msr_safe = xen_read_msr_safe, 1161 .write_msr_safe = xen_write_msr_safe, 1162 1163 .read_pmc = xen_read_pmc, 1164 1165 .load_tr_desc = paravirt_nop, 1166 .set_ldt = xen_set_ldt, 1167 .load_gdt = xen_load_gdt, 1168 .load_idt = xen_load_idt, 1169 .load_tls = xen_load_tls, 1170 .load_gs_index = xen_load_gs_index, 1171 1172 .alloc_ldt = xen_alloc_ldt, 1173 .free_ldt = xen_free_ldt, 1174 1175 .store_tr = xen_store_tr, 1176 1177 .write_ldt_entry = xen_write_ldt_entry, 1178 .write_gdt_entry = xen_write_gdt_entry, 1179 .write_idt_entry = xen_write_idt_entry, 1180 .load_sp0 = xen_load_sp0, 1181 1182#ifdef CONFIG_X86_IOPL_IOPERM 1183 .invalidate_io_bitmap = xen_invalidate_io_bitmap, 1184 .update_io_bitmap = xen_update_io_bitmap, 1185#endif 1186 .io_delay = xen_io_delay, 1187 1188 .start_context_switch = xen_start_context_switch, 1189 .end_context_switch = xen_end_context_switch, 1190 }, 1191}; 1192 1193static void xen_restart(char *msg) 1194{ 1195 xen_reboot(SHUTDOWN_reboot); 1196} 1197 1198static void xen_machine_halt(void) 1199{ 1200 xen_reboot(SHUTDOWN_poweroff); 1201} 1202 1203static void xen_machine_power_off(void) 1204{ 1205 do_kernel_power_off(); 1206 xen_reboot(SHUTDOWN_poweroff); 1207} 1208 1209static void xen_crash_shutdown(struct pt_regs *regs) 1210{ 1211 xen_reboot(SHUTDOWN_crash); 1212} 1213 1214static const struct machine_ops xen_machine_ops __initconst = { 1215 .restart = xen_restart, 1216 .halt = xen_machine_halt, 1217 .power_off = xen_machine_power_off, 1218 .shutdown = xen_machine_halt, 1219 .crash_shutdown = xen_crash_shutdown, 1220 .emergency_restart = xen_emergency_restart, 1221}; 1222 1223static unsigned char xen_get_nmi_reason(void) 1224{ 1225 unsigned char reason = 0; 1226 1227 /* Construct a value which looks like it came from port 0x61. */ 1228 if (test_bit(_XEN_NMIREASON_io_error, 1229 &HYPERVISOR_shared_info->arch.nmi_reason)) 1230 reason |= NMI_REASON_IOCHK; 1231 if (test_bit(_XEN_NMIREASON_pci_serr, 1232 &HYPERVISOR_shared_info->arch.nmi_reason)) 1233 reason |= NMI_REASON_SERR; 1234 1235 return reason; 1236} 1237 1238static void __init xen_boot_params_init_edd(void) 1239{ 1240#if IS_ENABLED(CONFIG_EDD) 1241 struct xen_platform_op op; 1242 struct edd_info *edd_info; 1243 u32 *mbr_signature; 1244 unsigned nr; 1245 int ret; 1246 1247 edd_info = boot_params.eddbuf; 1248 mbr_signature = boot_params.edd_mbr_sig_buffer; 1249 1250 op.cmd = XENPF_firmware_info; 1251 1252 op.u.firmware_info.type = XEN_FW_DISK_INFO; 1253 for (nr = 0; nr < EDDMAXNR; nr++) { 1254 struct edd_info *info = edd_info + nr; 1255 1256 op.u.firmware_info.index = nr; 1257 info->params.length = sizeof(info->params); 1258 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params, 1259 &info->params); 1260 ret = HYPERVISOR_platform_op(&op); 1261 if (ret) 1262 break; 1263 1264#define C(x) info->x = op.u.firmware_info.u.disk_info.x 1265 C(device); 1266 C(version); 1267 C(interface_support); 1268 C(legacy_max_cylinder); 1269 C(legacy_max_head); 1270 C(legacy_sectors_per_track); 1271#undef C 1272 } 1273 boot_params.eddbuf_entries = nr; 1274 1275 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE; 1276 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) { 1277 op.u.firmware_info.index = nr; 1278 ret = HYPERVISOR_platform_op(&op); 1279 if (ret) 1280 break; 1281 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature; 1282 } 1283 boot_params.edd_mbr_sig_buf_entries = nr; 1284#endif 1285} 1286 1287/* 1288 * Set up the GDT and segment registers for -fstack-protector. Until 1289 * we do this, we have to be careful not to call any stack-protected 1290 * function, which is most of the kernel. 1291 */ 1292static void __init xen_setup_gdt(int cpu) 1293{ 1294 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot; 1295 pv_ops.cpu.load_gdt = xen_load_gdt_boot; 1296 1297 switch_gdt_and_percpu_base(cpu); 1298 1299 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry; 1300 pv_ops.cpu.load_gdt = xen_load_gdt; 1301} 1302 1303static void __init xen_dom0_set_legacy_features(void) 1304{ 1305 x86_platform.legacy.rtc = 1; 1306} 1307 1308static void __init xen_domu_set_legacy_features(void) 1309{ 1310 x86_platform.legacy.rtc = 0; 1311} 1312 1313extern void early_xen_iret_patch(void); 1314 1315/* First C function to be called on Xen boot */ 1316asmlinkage __visible void __init xen_start_kernel(struct start_info *si) 1317{ 1318 struct physdev_set_iopl set_iopl; 1319 unsigned long initrd_start = 0; 1320 int rc; 1321 1322 if (!si) 1323 return; 1324 1325 clear_bss(); 1326 1327 xen_start_info = si; 1328 1329 __text_gen_insn(&early_xen_iret_patch, 1330 JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret, 1331 JMP32_INSN_SIZE); 1332 1333 xen_domain_type = XEN_PV_DOMAIN; 1334 xen_start_flags = xen_start_info->flags; 1335 1336 xen_setup_features(); 1337 1338 /* Install Xen paravirt ops */ 1339 pv_info = xen_info; 1340 pv_ops.cpu = xen_cpu_ops.cpu; 1341 xen_init_irq_ops(); 1342 1343 /* 1344 * Setup xen_vcpu early because it is needed for 1345 * local_irq_disable(), irqs_disabled(), e.g. in printk(). 1346 * 1347 * Don't do the full vcpu_info placement stuff until we have 1348 * the cpu_possible_mask and a non-dummy shared_info. 1349 */ 1350 xen_vcpu_info_reset(0); 1351 1352 x86_platform.get_nmi_reason = xen_get_nmi_reason; 1353 x86_platform.realmode_reserve = x86_init_noop; 1354 x86_platform.realmode_init = x86_init_noop; 1355 1356 x86_init.resources.memory_setup = xen_memory_setup; 1357 x86_init.irqs.intr_mode_select = x86_init_noop; 1358 x86_init.irqs.intr_mode_init = x86_64_probe_apic; 1359 x86_init.oem.arch_setup = xen_arch_setup; 1360 x86_init.oem.banner = xen_banner; 1361 x86_init.hyper.init_platform = xen_pv_init_platform; 1362 x86_init.hyper.guest_late_init = xen_pv_guest_late_init; 1363 1364 /* 1365 * Set up some pagetable state before starting to set any ptes. 1366 */ 1367 1368 xen_setup_machphys_mapping(); 1369 xen_init_mmu_ops(); 1370 1371 /* Prevent unwanted bits from being set in PTEs. */ 1372 __supported_pte_mask &= ~_PAGE_GLOBAL; 1373 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 1374 1375 /* Get mfn list */ 1376 xen_build_dynamic_phys_to_machine(); 1377 1378 /* Work out if we support NX */ 1379 get_cpu_cap(&boot_cpu_data); 1380 x86_configure_nx(); 1381 1382 /* 1383 * Set up kernel GDT and segment registers, mainly so that 1384 * -fstack-protector code can be executed. 1385 */ 1386 xen_setup_gdt(0); 1387 1388 /* Determine virtual and physical address sizes */ 1389 get_cpu_address_sizes(&boot_cpu_data); 1390 1391 /* Let's presume PV guests always boot on vCPU with id 0. */ 1392 per_cpu(xen_vcpu_id, 0) = 0; 1393 1394 idt_setup_early_handler(); 1395 1396 xen_init_capabilities(); 1397 1398 /* 1399 * set up the basic apic ops. 1400 */ 1401 xen_init_apic(); 1402 1403 machine_ops = xen_machine_ops; 1404 1405 /* 1406 * The only reliable way to retain the initial address of the 1407 * percpu gdt_page is to remember it here, so we can go and 1408 * mark it RW later, when the initial percpu area is freed. 1409 */ 1410 xen_initial_gdt = &per_cpu(gdt_page, 0); 1411 1412 xen_smp_init(); 1413 1414#ifdef CONFIG_ACPI_NUMA 1415 /* 1416 * The pages we from Xen are not related to machine pages, so 1417 * any NUMA information the kernel tries to get from ACPI will 1418 * be meaningless. Prevent it from trying. 1419 */ 1420 disable_srat(); 1421#endif 1422 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); 1423 1424 local_irq_disable(); 1425 early_boot_irqs_disabled = true; 1426 1427 xen_raw_console_write("mapping kernel into physical memory\n"); 1428 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, 1429 xen_start_info->nr_pages); 1430 xen_reserve_special_pages(); 1431 1432 /* 1433 * We used to do this in xen_arch_setup, but that is too late 1434 * on AMD were early_cpu_init (run before ->arch_setup()) calls 1435 * early_amd_init which pokes 0xcf8 port. 1436 */ 1437 set_iopl.iopl = 1; 1438 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); 1439 if (rc != 0) 1440 xen_raw_printk("physdev_op failed %d\n", rc); 1441 1442 1443 if (xen_start_info->mod_start) { 1444 if (xen_start_info->flags & SIF_MOD_START_PFN) 1445 initrd_start = PFN_PHYS(xen_start_info->mod_start); 1446 else 1447 initrd_start = __pa(xen_start_info->mod_start); 1448 } 1449 1450 /* Poke various useful things into boot_params */ 1451 boot_params.hdr.type_of_loader = (9 << 4) | 0; 1452 boot_params.hdr.ramdisk_image = initrd_start; 1453 boot_params.hdr.ramdisk_size = xen_start_info->mod_len; 1454 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); 1455 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN; 1456 1457 if (!xen_initial_domain()) { 1458 if (pci_xen) 1459 x86_init.pci.arch_init = pci_xen_init; 1460 x86_platform.set_legacy_features = 1461 xen_domu_set_legacy_features; 1462 } else { 1463 const struct dom0_vga_console_info *info = 1464 (void *)((char *)xen_start_info + 1465 xen_start_info->console.dom0.info_off); 1466 struct xen_platform_op op = { 1467 .cmd = XENPF_firmware_info, 1468 .interface_version = XENPF_INTERFACE_VERSION, 1469 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS, 1470 }; 1471 1472 x86_platform.set_legacy_features = 1473 xen_dom0_set_legacy_features; 1474 xen_init_vga(info, xen_start_info->console.dom0.info_size, 1475 &boot_params.screen_info); 1476 xen_start_info->console.domU.mfn = 0; 1477 xen_start_info->console.domU.evtchn = 0; 1478 1479 if (HYPERVISOR_platform_op(&op) == 0) 1480 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags; 1481 1482 /* Make sure ACS will be enabled */ 1483 pci_request_acs(); 1484 1485 xen_acpi_sleep_register(); 1486 1487 xen_boot_params_init_edd(); 1488 1489#ifdef CONFIG_ACPI 1490 /* 1491 * Disable selecting "Firmware First mode" for correctable 1492 * memory errors, as this is the duty of the hypervisor to 1493 * decide. 1494 */ 1495 acpi_disable_cmcff = 1; 1496#endif 1497 } 1498 1499 xen_add_preferred_consoles(); 1500 1501#ifdef CONFIG_PCI 1502 /* PCI BIOS service won't work from a PV guest. */ 1503 pci_probe &= ~PCI_PROBE_BIOS; 1504#endif 1505 xen_raw_console_write("about to get started...\n"); 1506 1507 /* We need this for printk timestamps */ 1508 xen_setup_runstate_info(0); 1509 1510 xen_efi_init(&boot_params); 1511 1512 /* Start the world */ 1513 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */ 1514 x86_64_start_reservations((char *)__pa_symbol(&boot_params)); 1515} 1516 1517static int xen_cpu_up_prepare_pv(unsigned int cpu) 1518{ 1519 int rc; 1520 1521 if (per_cpu(xen_vcpu, cpu) == NULL) 1522 return -ENODEV; 1523 1524 xen_setup_timer(cpu); 1525 1526 rc = xen_smp_intr_init(cpu); 1527 if (rc) { 1528 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n", 1529 cpu, rc); 1530 return rc; 1531 } 1532 1533 rc = xen_smp_intr_init_pv(cpu); 1534 if (rc) { 1535 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n", 1536 cpu, rc); 1537 return rc; 1538 } 1539 1540 return 0; 1541} 1542 1543static int xen_cpu_dead_pv(unsigned int cpu) 1544{ 1545 xen_smp_intr_free(cpu); 1546 xen_smp_intr_free_pv(cpu); 1547 1548 xen_teardown_timer(cpu); 1549 1550 return 0; 1551} 1552 1553static uint32_t __init xen_platform_pv(void) 1554{ 1555 if (xen_pv_domain()) 1556 return xen_cpuid_base(); 1557 1558 return 0; 1559} 1560 1561const __initconst struct hypervisor_x86 x86_hyper_xen_pv = { 1562 .name = "Xen PV", 1563 .detect = xen_platform_pv, 1564 .type = X86_HYPER_XEN_PV, 1565 .runtime.pin_vcpu = xen_pin_vcpu, 1566 .ignore_nopv = true, 1567}; 1568