1/* 2 * Copyright (C) 1991, 1992 Linus Torvalds 3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs 4 * 5 * Pentium III FXSR, SSE support 6 * Gareth Hughes <gareth@valinux.com>, May 2000 7 */ 8 9/* 10 * Handle hardware traps and faults. 11 */ 12 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15#include <linux/context_tracking.h> 16#include <linux/interrupt.h> 17#include <linux/kallsyms.h> 18#include <linux/kmsan.h> 19#include <linux/spinlock.h> 20#include <linux/kprobes.h> 21#include <linux/uaccess.h> 22#include <linux/kdebug.h> 23#include <linux/kgdb.h> 24#include <linux/kernel.h> 25#include <linux/export.h> 26#include <linux/ptrace.h> 27#include <linux/uprobes.h> 28#include <linux/string.h> 29#include <linux/delay.h> 30#include <linux/errno.h> 31#include <linux/kexec.h> 32#include <linux/sched.h> 33#include <linux/sched/task_stack.h> 34#include <linux/timer.h> 35#include <linux/init.h> 36#include <linux/bug.h> 37#include <linux/nmi.h> 38#include <linux/mm.h> 39#include <linux/smp.h> 40#include <linux/cpu.h> 41#include <linux/io.h> 42#include <linux/hardirq.h> 43#include <linux/atomic.h> 44#include <linux/iommu.h> 45 46#include <asm/stacktrace.h> 47#include <asm/processor.h> 48#include <asm/debugreg.h> 49#include <asm/realmode.h> 50#include <asm/text-patching.h> 51#include <asm/ftrace.h> 52#include <asm/traps.h> 53#include <asm/desc.h> 54#include <asm/fred.h> 55#include <asm/fpu/api.h> 56#include <asm/cpu.h> 57#include <asm/cpu_entry_area.h> 58#include <asm/mce.h> 59#include <asm/fixmap.h> 60#include <asm/mach_traps.h> 61#include <asm/alternative.h> 62#include <asm/fpu/xstate.h> 63#include <asm/vm86.h> 64#include <asm/umip.h> 65#include <asm/insn.h> 66#include <asm/insn-eval.h> 67#include <asm/vdso.h> 68#include <asm/tdx.h> 69#include <asm/cfi.h> 70 71#ifdef CONFIG_X86_64 72#include <asm/x86_init.h> 73#else 74#include <asm/processor-flags.h> 75#include <asm/setup.h> 76#endif 77 78#include <asm/proto.h> 79 80DECLARE_BITMAP(system_vectors, NR_VECTORS); 81 82__always_inline int is_valid_bugaddr(unsigned long addr) 83{ 84 if (addr < TASK_SIZE_MAX) 85 return 0; 86 87 /* 88 * We got #UD, if the text isn't readable we'd have gotten 89 * a different exception. 90 */ 91 return *(unsigned short *)addr == INSN_UD2; 92} 93 94static nokprobe_inline int 95do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str, 96 struct pt_regs *regs, long error_code) 97{ 98 if (v8086_mode(regs)) { 99 /* 100 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. 101 * On nmi (interrupt 2), do_trap should not be called. 102 */ 103 if (trapnr < X86_TRAP_UD) { 104 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, 105 error_code, trapnr)) 106 return 0; 107 } 108 } else if (!user_mode(regs)) { 109 if (fixup_exception(regs, trapnr, error_code, 0)) 110 return 0; 111 112 tsk->thread.error_code = error_code; 113 tsk->thread.trap_nr = trapnr; 114 die(str, regs, error_code); 115 } else { 116 if (fixup_vdso_exception(regs, trapnr, error_code, 0)) 117 return 0; 118 } 119 120 /* 121 * We want error_code and trap_nr set for userspace faults and 122 * kernelspace faults which result in die(), but not 123 * kernelspace faults which are fixed up. die() gives the 124 * process no chance to handle the signal and notice the 125 * kernel fault information, so that won't result in polluting 126 * the information about previously queued, but not yet 127 * delivered, faults. See also exc_general_protection below. 128 */ 129 tsk->thread.error_code = error_code; 130 tsk->thread.trap_nr = trapnr; 131 132 return -1; 133} 134 135static void show_signal(struct task_struct *tsk, int signr, 136 const char *type, const char *desc, 137 struct pt_regs *regs, long error_code) 138{ 139 if (show_unhandled_signals && unhandled_signal(tsk, signr) && 140 printk_ratelimit()) { 141 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx", 142 tsk->comm, task_pid_nr(tsk), type, desc, 143 regs->ip, regs->sp, error_code); 144 print_vma_addr(KERN_CONT " in ", regs->ip); 145 pr_cont("\n"); 146 } 147} 148 149static void 150do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, 151 long error_code, int sicode, void __user *addr) 152{ 153 struct task_struct *tsk = current; 154 155 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) 156 return; 157 158 show_signal(tsk, signr, "trap ", str, regs, error_code); 159 160 if (!sicode) 161 force_sig(signr); 162 else 163 force_sig_fault(signr, sicode, addr); 164} 165NOKPROBE_SYMBOL(do_trap); 166 167static void do_error_trap(struct pt_regs *regs, long error_code, char *str, 168 unsigned long trapnr, int signr, int sicode, void __user *addr) 169{ 170 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); 171 172 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != 173 NOTIFY_STOP) { 174 cond_local_irq_enable(regs); 175 do_trap(trapnr, signr, str, regs, error_code, sicode, addr); 176 cond_local_irq_disable(regs); 177 } 178} 179 180/* 181 * Posix requires to provide the address of the faulting instruction for 182 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t. 183 * 184 * This address is usually regs->ip, but when an uprobe moved the code out 185 * of line then regs->ip points to the XOL code which would confuse 186 * anything which analyzes the fault address vs. the unmodified binary. If 187 * a trap happened in XOL code then uprobe maps regs->ip back to the 188 * original instruction address. 189 */ 190static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs) 191{ 192 return (void __user *)uprobe_get_trap_addr(regs); 193} 194 195DEFINE_IDTENTRY(exc_divide_error) 196{ 197 do_error_trap(regs, 0, "divide error", X86_TRAP_DE, SIGFPE, 198 FPE_INTDIV, error_get_trap_addr(regs)); 199} 200 201DEFINE_IDTENTRY(exc_overflow) 202{ 203 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL); 204} 205 206#ifdef CONFIG_X86_F00F_BUG 207void handle_invalid_op(struct pt_regs *regs) 208#else 209static inline void handle_invalid_op(struct pt_regs *regs) 210#endif 211{ 212 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL, 213 ILL_ILLOPN, error_get_trap_addr(regs)); 214} 215 216static noinstr bool handle_bug(struct pt_regs *regs) 217{ 218 bool handled = false; 219 220 /* 221 * Normally @regs are unpoisoned by irqentry_enter(), but handle_bug() 222 * is a rare case that uses @regs without passing them to 223 * irqentry_enter(). 224 */ 225 kmsan_unpoison_entry_regs(regs); 226 if (!is_valid_bugaddr(regs->ip)) 227 return handled; 228 229 /* 230 * All lies, just get the WARN/BUG out. 231 */ 232 instrumentation_begin(); 233 /* 234 * Since we're emulating a CALL with exceptions, restore the interrupt 235 * state to what it was at the exception site. 236 */ 237 if (regs->flags & X86_EFLAGS_IF) 238 raw_local_irq_enable(); 239 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN || 240 handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) { 241 regs->ip += LEN_UD2; 242 handled = true; 243 } 244 if (regs->flags & X86_EFLAGS_IF) 245 raw_local_irq_disable(); 246 instrumentation_end(); 247 248 return handled; 249} 250 251DEFINE_IDTENTRY_RAW(exc_invalid_op) 252{ 253 irqentry_state_t state; 254 255 /* 256 * We use UD2 as a short encoding for 'CALL __WARN', as such 257 * handle it before exception entry to avoid recursive WARN 258 * in case exception entry is the one triggering WARNs. 259 */ 260 if (!user_mode(regs) && handle_bug(regs)) 261 return; 262 263 state = irqentry_enter(regs); 264 instrumentation_begin(); 265 handle_invalid_op(regs); 266 instrumentation_end(); 267 irqentry_exit(regs, state); 268} 269 270DEFINE_IDTENTRY(exc_coproc_segment_overrun) 271{ 272 do_error_trap(regs, 0, "coprocessor segment overrun", 273 X86_TRAP_OLD_MF, SIGFPE, 0, NULL); 274} 275 276DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss) 277{ 278 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV, 279 0, NULL); 280} 281 282DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present) 283{ 284 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP, 285 SIGBUS, 0, NULL); 286} 287 288DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment) 289{ 290 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS, 291 0, NULL); 292} 293 294DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check) 295{ 296 char *str = "alignment check"; 297 298 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP) 299 return; 300 301 if (!user_mode(regs)) 302 die("Split lock detected\n", regs, error_code); 303 304 local_irq_enable(); 305 306 if (handle_user_split_lock(regs, error_code)) 307 goto out; 308 309 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs, 310 error_code, BUS_ADRALN, NULL); 311 312out: 313 local_irq_disable(); 314} 315 316#ifdef CONFIG_VMAP_STACK 317__visible void __noreturn handle_stack_overflow(struct pt_regs *regs, 318 unsigned long fault_address, 319 struct stack_info *info) 320{ 321 const char *name = stack_type_name(info->type); 322 323 printk(KERN_EMERG "BUG: %s stack guard page was hit at %p (stack is %p..%p)\n", 324 name, (void *)fault_address, info->begin, info->end); 325 326 die("stack guard page", regs, 0); 327 328 /* Be absolutely certain we don't return. */ 329 panic("%s stack guard hit", name); 330} 331#endif 332 333/* 334 * Runs on an IST stack for x86_64 and on a special task stack for x86_32. 335 * 336 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the 337 * SDM's warnings about double faults being unrecoverable, returning works as 338 * expected. Presumably what the SDM actually means is that the CPU may get 339 * the register state wrong on entry, so returning could be a bad idea. 340 * 341 * Various CPU engineers have promised that double faults due to an IRET fault 342 * while the stack is read-only are, in fact, recoverable. 343 * 344 * On x86_32, this is entered through a task gate, and regs are synthesized 345 * from the TSS. Returning is, in principle, okay, but changes to regs will 346 * be lost. If, for some reason, we need to return to a context with modified 347 * regs, the shim code could be adjusted to synchronize the registers. 348 * 349 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs 350 * to be read before doing anything else. 351 */ 352DEFINE_IDTENTRY_DF(exc_double_fault) 353{ 354 static const char str[] = "double fault"; 355 struct task_struct *tsk = current; 356 357#ifdef CONFIG_VMAP_STACK 358 unsigned long address = read_cr2(); 359 struct stack_info info; 360#endif 361 362#ifdef CONFIG_X86_ESPFIX64 363 extern unsigned char native_irq_return_iret[]; 364 365 /* 366 * If IRET takes a non-IST fault on the espfix64 stack, then we 367 * end up promoting it to a doublefault. In that case, take 368 * advantage of the fact that we're not using the normal (TSS.sp0) 369 * stack right now. We can write a fake #GP(0) frame at TSS.sp0 370 * and then modify our own IRET frame so that, when we return, 371 * we land directly at the #GP(0) vector with the stack already 372 * set up according to its expectations. 373 * 374 * The net result is that our #GP handler will think that we 375 * entered from usermode with the bad user context. 376 * 377 * No need for nmi_enter() here because we don't use RCU. 378 */ 379 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY && 380 regs->cs == __KERNEL_CS && 381 regs->ip == (unsigned long)native_irq_return_iret) 382 { 383 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 384 unsigned long *p = (unsigned long *)regs->sp; 385 386 /* 387 * regs->sp points to the failing IRET frame on the 388 * ESPFIX64 stack. Copy it to the entry stack. This fills 389 * in gpregs->ss through gpregs->ip. 390 * 391 */ 392 gpregs->ip = p[0]; 393 gpregs->cs = p[1]; 394 gpregs->flags = p[2]; 395 gpregs->sp = p[3]; 396 gpregs->ss = p[4]; 397 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */ 398 399 /* 400 * Adjust our frame so that we return straight to the #GP 401 * vector with the expected RSP value. This is safe because 402 * we won't enable interrupts or schedule before we invoke 403 * general_protection, so nothing will clobber the stack 404 * frame we just set up. 405 * 406 * We will enter general_protection with kernel GSBASE, 407 * which is what the stub expects, given that the faulting 408 * RIP will be the IRET instruction. 409 */ 410 regs->ip = (unsigned long)asm_exc_general_protection; 411 regs->sp = (unsigned long)&gpregs->orig_ax; 412 413 return; 414 } 415#endif 416 417 irqentry_nmi_enter(regs); 418 instrumentation_begin(); 419 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); 420 421 tsk->thread.error_code = error_code; 422 tsk->thread.trap_nr = X86_TRAP_DF; 423 424#ifdef CONFIG_VMAP_STACK 425 /* 426 * If we overflow the stack into a guard page, the CPU will fail 427 * to deliver #PF and will send #DF instead. Similarly, if we 428 * take any non-IST exception while too close to the bottom of 429 * the stack, the processor will get a page fault while 430 * delivering the exception and will generate a double fault. 431 * 432 * According to the SDM (footnote in 6.15 under "Interrupt 14 - 433 * Page-Fault Exception (#PF): 434 * 435 * Processors update CR2 whenever a page fault is detected. If a 436 * second page fault occurs while an earlier page fault is being 437 * delivered, the faulting linear address of the second fault will 438 * overwrite the contents of CR2 (replacing the previous 439 * address). These updates to CR2 occur even if the page fault 440 * results in a double fault or occurs during the delivery of a 441 * double fault. 442 * 443 * The logic below has a small possibility of incorrectly diagnosing 444 * some errors as stack overflows. For example, if the IDT or GDT 445 * gets corrupted such that #GP delivery fails due to a bad descriptor 446 * causing #GP and we hit this condition while CR2 coincidentally 447 * points to the stack guard page, we'll think we overflowed the 448 * stack. Given that we're going to panic one way or another 449 * if this happens, this isn't necessarily worth fixing. 450 * 451 * If necessary, we could improve the test by only diagnosing 452 * a stack overflow if the saved RSP points within 47 bytes of 453 * the bottom of the stack: if RSP == tsk_stack + 48 and we 454 * take an exception, the stack is already aligned and there 455 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a 456 * possible error code, so a stack overflow would *not* double 457 * fault. With any less space left, exception delivery could 458 * fail, and, as a practical matter, we've overflowed the 459 * stack even if the actual trigger for the double fault was 460 * something else. 461 */ 462 if (get_stack_guard_info((void *)address, &info)) 463 handle_stack_overflow(regs, address, &info); 464#endif 465 466 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code); 467 die("double fault", regs, error_code); 468 panic("Machine halted."); 469 instrumentation_end(); 470} 471 472DEFINE_IDTENTRY(exc_bounds) 473{ 474 if (notify_die(DIE_TRAP, "bounds", regs, 0, 475 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) 476 return; 477 cond_local_irq_enable(regs); 478 479 if (!user_mode(regs)) 480 die("bounds", regs, 0); 481 482 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL); 483 484 cond_local_irq_disable(regs); 485} 486 487enum kernel_gp_hint { 488 GP_NO_HINT, 489 GP_NON_CANONICAL, 490 GP_CANONICAL 491}; 492 493/* 494 * When an uncaught #GP occurs, try to determine the memory address accessed by 495 * the instruction and return that address to the caller. Also, try to figure 496 * out whether any part of the access to that address was non-canonical. 497 */ 498static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, 499 unsigned long *addr) 500{ 501 u8 insn_buf[MAX_INSN_SIZE]; 502 struct insn insn; 503 int ret; 504 505 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip, 506 MAX_INSN_SIZE)) 507 return GP_NO_HINT; 508 509 ret = insn_decode_kernel(&insn, insn_buf); 510 if (ret < 0) 511 return GP_NO_HINT; 512 513 *addr = (unsigned long)insn_get_addr_ref(&insn, regs); 514 if (*addr == -1UL) 515 return GP_NO_HINT; 516 517#ifdef CONFIG_X86_64 518 /* 519 * Check that: 520 * - the operand is not in the kernel half 521 * - the last byte of the operand is not in the user canonical half 522 */ 523 if (*addr < ~__VIRTUAL_MASK && 524 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK) 525 return GP_NON_CANONICAL; 526#endif 527 528 return GP_CANONICAL; 529} 530 531#define GPFSTR "general protection fault" 532 533static bool fixup_iopl_exception(struct pt_regs *regs) 534{ 535 struct thread_struct *t = ¤t->thread; 536 unsigned char byte; 537 unsigned long ip; 538 539 if (!IS_ENABLED(CONFIG_X86_IOPL_IOPERM) || t->iopl_emul != 3) 540 return false; 541 542 if (insn_get_effective_ip(regs, &ip)) 543 return false; 544 545 if (get_user(byte, (const char __user *)ip)) 546 return false; 547 548 if (byte != 0xfa && byte != 0xfb) 549 return false; 550 551 if (!t->iopl_warn && printk_ratelimit()) { 552 pr_err("%s[%d] attempts to use CLI/STI, pretending it's a NOP, ip:%lx", 553 current->comm, task_pid_nr(current), ip); 554 print_vma_addr(KERN_CONT " in ", ip); 555 pr_cont("\n"); 556 t->iopl_warn = 1; 557 } 558 559 regs->ip += 1; 560 return true; 561} 562 563/* 564 * The unprivileged ENQCMD instruction generates #GPs if the 565 * IA32_PASID MSR has not been populated. If possible, populate 566 * the MSR from a PASID previously allocated to the mm. 567 */ 568static bool try_fixup_enqcmd_gp(void) 569{ 570#ifdef CONFIG_ARCH_HAS_CPU_PASID 571 u32 pasid; 572 573 /* 574 * MSR_IA32_PASID is managed using XSAVE. Directly 575 * writing to the MSR is only possible when fpregs 576 * are valid and the fpstate is not. This is 577 * guaranteed when handling a userspace exception 578 * in *before* interrupts are re-enabled. 579 */ 580 lockdep_assert_irqs_disabled(); 581 582 /* 583 * Hardware without ENQCMD will not generate 584 * #GPs that can be fixed up here. 585 */ 586 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) 587 return false; 588 589 /* 590 * If the mm has not been allocated a 591 * PASID, the #GP can not be fixed up. 592 */ 593 if (!mm_valid_pasid(current->mm)) 594 return false; 595 596 pasid = mm_get_enqcmd_pasid(current->mm); 597 598 /* 599 * Did this thread already have its PASID activated? 600 * If so, the #GP must be from something else. 601 */ 602 if (current->pasid_activated) 603 return false; 604 605 wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID); 606 current->pasid_activated = 1; 607 608 return true; 609#else 610 return false; 611#endif 612} 613 614static bool gp_try_fixup_and_notify(struct pt_regs *regs, int trapnr, 615 unsigned long error_code, const char *str, 616 unsigned long address) 617{ 618 if (fixup_exception(regs, trapnr, error_code, address)) 619 return true; 620 621 current->thread.error_code = error_code; 622 current->thread.trap_nr = trapnr; 623 624 /* 625 * To be potentially processing a kprobe fault and to trust the result 626 * from kprobe_running(), we have to be non-preemptible. 627 */ 628 if (!preemptible() && kprobe_running() && 629 kprobe_fault_handler(regs, trapnr)) 630 return true; 631 632 return notify_die(DIE_GPF, str, regs, error_code, trapnr, SIGSEGV) == NOTIFY_STOP; 633} 634 635static void gp_user_force_sig_segv(struct pt_regs *regs, int trapnr, 636 unsigned long error_code, const char *str) 637{ 638 current->thread.error_code = error_code; 639 current->thread.trap_nr = trapnr; 640 show_signal(current, SIGSEGV, "", str, regs, error_code); 641 force_sig(SIGSEGV); 642} 643 644DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) 645{ 646 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR; 647 enum kernel_gp_hint hint = GP_NO_HINT; 648 unsigned long gp_addr; 649 650 if (user_mode(regs) && try_fixup_enqcmd_gp()) 651 return; 652 653 cond_local_irq_enable(regs); 654 655 if (static_cpu_has(X86_FEATURE_UMIP)) { 656 if (user_mode(regs) && fixup_umip_exception(regs)) 657 goto exit; 658 } 659 660 if (v8086_mode(regs)) { 661 local_irq_enable(); 662 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); 663 local_irq_disable(); 664 return; 665 } 666 667 if (user_mode(regs)) { 668 if (fixup_iopl_exception(regs)) 669 goto exit; 670 671 if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0)) 672 goto exit; 673 674 gp_user_force_sig_segv(regs, X86_TRAP_GP, error_code, desc); 675 goto exit; 676 } 677 678 if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc, 0)) 679 goto exit; 680 681 if (error_code) 682 snprintf(desc, sizeof(desc), "segment-related " GPFSTR); 683 else 684 hint = get_kernel_gp_address(regs, &gp_addr); 685 686 if (hint != GP_NO_HINT) 687 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx", 688 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address" 689 : "maybe for address", 690 gp_addr); 691 692 /* 693 * KASAN is interested only in the non-canonical case, clear it 694 * otherwise. 695 */ 696 if (hint != GP_NON_CANONICAL) 697 gp_addr = 0; 698 699 die_addr(desc, regs, error_code, gp_addr); 700 701exit: 702 cond_local_irq_disable(regs); 703} 704 705static bool do_int3(struct pt_regs *regs) 706{ 707 int res; 708 709#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 710 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, 711 SIGTRAP) == NOTIFY_STOP) 712 return true; 713#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 714 715#ifdef CONFIG_KPROBES 716 if (kprobe_int3_handler(regs)) 717 return true; 718#endif 719 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP); 720 721 return res == NOTIFY_STOP; 722} 723NOKPROBE_SYMBOL(do_int3); 724 725static void do_int3_user(struct pt_regs *regs) 726{ 727 if (do_int3(regs)) 728 return; 729 730 cond_local_irq_enable(regs); 731 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL); 732 cond_local_irq_disable(regs); 733} 734 735DEFINE_IDTENTRY_RAW(exc_int3) 736{ 737 /* 738 * poke_int3_handler() is completely self contained code; it does (and 739 * must) *NOT* call out to anything, lest it hits upon yet another 740 * INT3. 741 */ 742 if (poke_int3_handler(regs)) 743 return; 744 745 /* 746 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely() 747 * and therefore can trigger INT3, hence poke_int3_handler() must 748 * be done before. If the entry came from kernel mode, then use 749 * nmi_enter() because the INT3 could have been hit in any context 750 * including NMI. 751 */ 752 if (user_mode(regs)) { 753 irqentry_enter_from_user_mode(regs); 754 instrumentation_begin(); 755 do_int3_user(regs); 756 instrumentation_end(); 757 irqentry_exit_to_user_mode(regs); 758 } else { 759 irqentry_state_t irq_state = irqentry_nmi_enter(regs); 760 761 instrumentation_begin(); 762 if (!do_int3(regs)) 763 die("int3", regs, 0); 764 instrumentation_end(); 765 irqentry_nmi_exit(regs, irq_state); 766 } 767} 768 769#ifdef CONFIG_X86_64 770/* 771 * Help handler running on a per-cpu (IST or entry trampoline) stack 772 * to switch to the normal thread stack if the interrupted code was in 773 * user mode. The actual stack switch is done in entry_64.S 774 */ 775asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs) 776{ 777 struct pt_regs *regs = (struct pt_regs *)current_top_of_stack() - 1; 778 if (regs != eregs) 779 *regs = *eregs; 780 return regs; 781} 782 783#ifdef CONFIG_AMD_MEM_ENCRYPT 784asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *regs) 785{ 786 unsigned long sp, *stack; 787 struct stack_info info; 788 struct pt_regs *regs_ret; 789 790 /* 791 * In the SYSCALL entry path the RSP value comes from user-space - don't 792 * trust it and switch to the current kernel stack 793 */ 794 if (ip_within_syscall_gap(regs)) { 795 sp = current_top_of_stack(); 796 goto sync; 797 } 798 799 /* 800 * From here on the RSP value is trusted. Now check whether entry 801 * happened from a safe stack. Not safe are the entry or unknown stacks, 802 * use the fall-back stack instead in this case. 803 */ 804 sp = regs->sp; 805 stack = (unsigned long *)sp; 806 807 if (!get_stack_info_noinstr(stack, current, &info) || info.type == STACK_TYPE_ENTRY || 808 info.type > STACK_TYPE_EXCEPTION_LAST) 809 sp = __this_cpu_ist_top_va(VC2); 810 811sync: 812 /* 813 * Found a safe stack - switch to it as if the entry didn't happen via 814 * IST stack. The code below only copies pt_regs, the real switch happens 815 * in assembly code. 816 */ 817 sp = ALIGN_DOWN(sp, 8) - sizeof(*regs_ret); 818 819 regs_ret = (struct pt_regs *)sp; 820 *regs_ret = *regs; 821 822 return regs_ret; 823} 824#endif 825 826asmlinkage __visible noinstr struct pt_regs *fixup_bad_iret(struct pt_regs *bad_regs) 827{ 828 struct pt_regs tmp, *new_stack; 829 830 /* 831 * This is called from entry_64.S early in handling a fault 832 * caused by a bad iret to user mode. To handle the fault 833 * correctly, we want to move our stack frame to where it would 834 * be had we entered directly on the entry stack (rather than 835 * just below the IRET frame) and we want to pretend that the 836 * exception came from the IRET target. 837 */ 838 new_stack = (struct pt_regs *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 839 840 /* Copy the IRET target to the temporary storage. */ 841 __memcpy(&tmp.ip, (void *)bad_regs->sp, 5*8); 842 843 /* Copy the remainder of the stack from the current stack. */ 844 __memcpy(&tmp, bad_regs, offsetof(struct pt_regs, ip)); 845 846 /* Update the entry stack */ 847 __memcpy(new_stack, &tmp, sizeof(tmp)); 848 849 BUG_ON(!user_mode(new_stack)); 850 return new_stack; 851} 852#endif 853 854static bool is_sysenter_singlestep(struct pt_regs *regs) 855{ 856 /* 857 * We don't try for precision here. If we're anywhere in the region of 858 * code that can be single-stepped in the SYSENTER entry path, then 859 * assume that this is a useless single-step trap due to SYSENTER 860 * being invoked with TF set. (We don't know in advance exactly 861 * which instructions will be hit because BTF could plausibly 862 * be set.) 863 */ 864#ifdef CONFIG_X86_32 865 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) < 866 (unsigned long)__end_SYSENTER_singlestep_region - 867 (unsigned long)__begin_SYSENTER_singlestep_region; 868#elif defined(CONFIG_IA32_EMULATION) 869 return (regs->ip - (unsigned long)entry_SYSENTER_compat) < 870 (unsigned long)__end_entry_SYSENTER_compat - 871 (unsigned long)entry_SYSENTER_compat; 872#else 873 return false; 874#endif 875} 876 877static __always_inline unsigned long debug_read_clear_dr6(void) 878{ 879 unsigned long dr6; 880 881 /* 882 * The Intel SDM says: 883 * 884 * Certain debug exceptions may clear bits 0-3. The remaining 885 * contents of the DR6 register are never cleared by the 886 * processor. To avoid confusion in identifying debug 887 * exceptions, debug handlers should clear the register before 888 * returning to the interrupted task. 889 * 890 * Keep it simple: clear DR6 immediately. 891 */ 892 get_debugreg(dr6, 6); 893 set_debugreg(DR6_RESERVED, 6); 894 dr6 ^= DR6_RESERVED; /* Flip to positive polarity */ 895 896 return dr6; 897} 898 899/* 900 * Our handling of the processor debug registers is non-trivial. 901 * We do not clear them on entry and exit from the kernel. Therefore 902 * it is possible to get a watchpoint trap here from inside the kernel. 903 * However, the code in ./ptrace.c has ensured that the user can 904 * only set watchpoints on userspace addresses. Therefore the in-kernel 905 * watchpoint trap can only occur in code which is reading/writing 906 * from user space. Such code must not hold kernel locks (since it 907 * can equally take a page fault), therefore it is safe to call 908 * force_sig_info even though that claims and releases locks. 909 * 910 * Code in ./signal.c ensures that the debug control register 911 * is restored before we deliver any signal, and therefore that 912 * user code runs with the correct debug control register even though 913 * we clear it here. 914 * 915 * Being careful here means that we don't have to be as careful in a 916 * lot of more complicated places (task switching can be a bit lazy 917 * about restoring all the debug state, and ptrace doesn't have to 918 * find every occurrence of the TF bit that could be saved away even 919 * by user code) 920 * 921 * May run on IST stack. 922 */ 923 924static bool notify_debug(struct pt_regs *regs, unsigned long *dr6) 925{ 926 /* 927 * Notifiers will clear bits in @dr6 to indicate the event has been 928 * consumed - hw_breakpoint_handler(), single_stop_cont(). 929 * 930 * Notifiers will set bits in @virtual_dr6 to indicate the desire 931 * for signals - ptrace_triggered(), kgdb_hw_overflow_handler(). 932 */ 933 if (notify_die(DIE_DEBUG, "debug", regs, (long)dr6, 0, SIGTRAP) == NOTIFY_STOP) 934 return true; 935 936 return false; 937} 938 939static noinstr void exc_debug_kernel(struct pt_regs *regs, unsigned long dr6) 940{ 941 /* 942 * Disable breakpoints during exception handling; recursive exceptions 943 * are exceedingly 'fun'. 944 * 945 * Since this function is NOKPROBE, and that also applies to 946 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a 947 * HW_BREAKPOINT_W on our stack) 948 * 949 * Entry text is excluded for HW_BP_X and cpu_entry_area, which 950 * includes the entry stack is excluded for everything. 951 * 952 * For FRED, nested #DB should just work fine. But when a watchpoint or 953 * breakpoint is set in the code path which is executed by #DB handler, 954 * it results in an endless recursion and stack overflow. Thus we stay 955 * with the IDT approach, i.e., save DR7 and disable #DB. 956 */ 957 unsigned long dr7 = local_db_save(); 958 irqentry_state_t irq_state = irqentry_nmi_enter(regs); 959 instrumentation_begin(); 960 961 /* 962 * If something gets miswired and we end up here for a user mode 963 * #DB, we will malfunction. 964 */ 965 WARN_ON_ONCE(user_mode(regs)); 966 967 if (test_thread_flag(TIF_BLOCKSTEP)) { 968 /* 969 * The SDM says "The processor clears the BTF flag when it 970 * generates a debug exception." but PTRACE_BLOCKSTEP requested 971 * it for userspace, but we just took a kernel #DB, so re-set 972 * BTF. 973 */ 974 unsigned long debugctl; 975 976 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 977 debugctl |= DEBUGCTLMSR_BTF; 978 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 979 } 980 981 /* 982 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a 983 * watchpoint at the same time then that will still be handled. 984 */ 985 if (!cpu_feature_enabled(X86_FEATURE_FRED) && 986 (dr6 & DR_STEP) && is_sysenter_singlestep(regs)) 987 dr6 &= ~DR_STEP; 988 989 /* 990 * The kernel doesn't use INT1 991 */ 992 if (!dr6) 993 goto out; 994 995 if (notify_debug(regs, &dr6)) 996 goto out; 997 998 /* 999 * The kernel doesn't use TF single-step outside of: 1000 * 1001 * - Kprobes, consumed through kprobe_debug_handler() 1002 * - KGDB, consumed through notify_debug() 1003 * 1004 * So if we get here with DR_STEP set, something is wonky. 1005 * 1006 * A known way to trigger this is through QEMU's GDB stub, 1007 * which leaks #DB into the guest and causes IST recursion. 1008 */ 1009 if (WARN_ON_ONCE(dr6 & DR_STEP)) 1010 regs->flags &= ~X86_EFLAGS_TF; 1011out: 1012 instrumentation_end(); 1013 irqentry_nmi_exit(regs, irq_state); 1014 1015 local_db_restore(dr7); 1016} 1017 1018static noinstr void exc_debug_user(struct pt_regs *regs, unsigned long dr6) 1019{ 1020 bool icebp; 1021 1022 /* 1023 * If something gets miswired and we end up here for a kernel mode 1024 * #DB, we will malfunction. 1025 */ 1026 WARN_ON_ONCE(!user_mode(regs)); 1027 1028 /* 1029 * NB: We can't easily clear DR7 here because 1030 * irqentry_exit_to_usermode() can invoke ptrace, schedule, access 1031 * user memory, etc. This means that a recursive #DB is possible. If 1032 * this happens, that #DB will hit exc_debug_kernel() and clear DR7. 1033 * Since we're not on the IST stack right now, everything will be 1034 * fine. 1035 */ 1036 1037 irqentry_enter_from_user_mode(regs); 1038 instrumentation_begin(); 1039 1040 /* 1041 * Start the virtual/ptrace DR6 value with just the DR_STEP mask 1042 * of the real DR6. ptrace_triggered() will set the DR_TRAPn bits. 1043 * 1044 * Userspace expects DR_STEP to be visible in ptrace_get_debugreg(6) 1045 * even if it is not the result of PTRACE_SINGLESTEP. 1046 */ 1047 current->thread.virtual_dr6 = (dr6 & DR_STEP); 1048 1049 /* 1050 * The SDM says "The processor clears the BTF flag when it 1051 * generates a debug exception." Clear TIF_BLOCKSTEP to keep 1052 * TIF_BLOCKSTEP in sync with the hardware BTF flag. 1053 */ 1054 clear_thread_flag(TIF_BLOCKSTEP); 1055 1056 /* 1057 * If dr6 has no reason to give us about the origin of this trap, 1058 * then it's very likely the result of an icebp/int01 trap. 1059 * User wants a sigtrap for that. 1060 */ 1061 icebp = !dr6; 1062 1063 if (notify_debug(regs, &dr6)) 1064 goto out; 1065 1066 /* It's safe to allow irq's after DR6 has been saved */ 1067 local_irq_enable(); 1068 1069 if (v8086_mode(regs)) { 1070 handle_vm86_trap((struct kernel_vm86_regs *)regs, 0, X86_TRAP_DB); 1071 goto out_irq; 1072 } 1073 1074 /* #DB for bus lock can only be triggered from userspace. */ 1075 if (dr6 & DR_BUS_LOCK) 1076 handle_bus_lock(regs); 1077 1078 /* Add the virtual_dr6 bits for signals. */ 1079 dr6 |= current->thread.virtual_dr6; 1080 if (dr6 & (DR_STEP | DR_TRAP_BITS) || icebp) 1081 send_sigtrap(regs, 0, get_si_code(dr6)); 1082 1083out_irq: 1084 local_irq_disable(); 1085out: 1086 instrumentation_end(); 1087 irqentry_exit_to_user_mode(regs); 1088} 1089 1090#ifdef CONFIG_X86_64 1091/* IST stack entry */ 1092DEFINE_IDTENTRY_DEBUG(exc_debug) 1093{ 1094 exc_debug_kernel(regs, debug_read_clear_dr6()); 1095} 1096 1097/* User entry, runs on regular task stack */ 1098DEFINE_IDTENTRY_DEBUG_USER(exc_debug) 1099{ 1100 exc_debug_user(regs, debug_read_clear_dr6()); 1101} 1102 1103#ifdef CONFIG_X86_FRED 1104/* 1105 * When occurred on different ring level, i.e., from user or kernel 1106 * context, #DB needs to be handled on different stack: User #DB on 1107 * current task stack, while kernel #DB on a dedicated stack. 1108 * 1109 * This is exactly how FRED event delivery invokes an exception 1110 * handler: ring 3 event on level 0 stack, i.e., current task stack; 1111 * ring 0 event on the #DB dedicated stack specified in the 1112 * IA32_FRED_STKLVLS MSR. So unlike IDT, the FRED debug exception 1113 * entry stub doesn't do stack switch. 1114 */ 1115DEFINE_FREDENTRY_DEBUG(exc_debug) 1116{ 1117 /* 1118 * FRED #DB stores DR6 on the stack in the format which 1119 * debug_read_clear_dr6() returns for the IDT entry points. 1120 */ 1121 unsigned long dr6 = fred_event_data(regs); 1122 1123 if (user_mode(regs)) 1124 exc_debug_user(regs, dr6); 1125 else 1126 exc_debug_kernel(regs, dr6); 1127} 1128#endif /* CONFIG_X86_FRED */ 1129 1130#else 1131/* 32 bit does not have separate entry points. */ 1132DEFINE_IDTENTRY_RAW(exc_debug) 1133{ 1134 unsigned long dr6 = debug_read_clear_dr6(); 1135 1136 if (user_mode(regs)) 1137 exc_debug_user(regs, dr6); 1138 else 1139 exc_debug_kernel(regs, dr6); 1140} 1141#endif 1142 1143/* 1144 * Note that we play around with the 'TS' bit in an attempt to get 1145 * the correct behaviour even in the presence of the asynchronous 1146 * IRQ13 behaviour 1147 */ 1148static void math_error(struct pt_regs *regs, int trapnr) 1149{ 1150 struct task_struct *task = current; 1151 struct fpu *fpu = &task->thread.fpu; 1152 int si_code; 1153 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : 1154 "simd exception"; 1155 1156 cond_local_irq_enable(regs); 1157 1158 if (!user_mode(regs)) { 1159 if (fixup_exception(regs, trapnr, 0, 0)) 1160 goto exit; 1161 1162 task->thread.error_code = 0; 1163 task->thread.trap_nr = trapnr; 1164 1165 if (notify_die(DIE_TRAP, str, regs, 0, trapnr, 1166 SIGFPE) != NOTIFY_STOP) 1167 die(str, regs, 0); 1168 goto exit; 1169 } 1170 1171 /* 1172 * Synchronize the FPU register state to the memory register state 1173 * if necessary. This allows the exception handler to inspect it. 1174 */ 1175 fpu_sync_fpstate(fpu); 1176 1177 task->thread.trap_nr = trapnr; 1178 task->thread.error_code = 0; 1179 1180 si_code = fpu__exception_code(fpu, trapnr); 1181 /* Retry when we get spurious exceptions: */ 1182 if (!si_code) 1183 goto exit; 1184 1185 if (fixup_vdso_exception(regs, trapnr, 0, 0)) 1186 goto exit; 1187 1188 force_sig_fault(SIGFPE, si_code, 1189 (void __user *)uprobe_get_trap_addr(regs)); 1190exit: 1191 cond_local_irq_disable(regs); 1192} 1193 1194DEFINE_IDTENTRY(exc_coprocessor_error) 1195{ 1196 math_error(regs, X86_TRAP_MF); 1197} 1198 1199DEFINE_IDTENTRY(exc_simd_coprocessor_error) 1200{ 1201 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) { 1202 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */ 1203 if (!static_cpu_has(X86_FEATURE_XMM)) { 1204 __exc_general_protection(regs, 0); 1205 return; 1206 } 1207 } 1208 math_error(regs, X86_TRAP_XF); 1209} 1210 1211DEFINE_IDTENTRY(exc_spurious_interrupt_bug) 1212{ 1213 /* 1214 * This addresses a Pentium Pro Erratum: 1215 * 1216 * PROBLEM: If the APIC subsystem is configured in mixed mode with 1217 * Virtual Wire mode implemented through the local APIC, an 1218 * interrupt vector of 0Fh (Intel reserved encoding) may be 1219 * generated by the local APIC (Int 15). This vector may be 1220 * generated upon receipt of a spurious interrupt (an interrupt 1221 * which is removed before the system receives the INTA sequence) 1222 * instead of the programmed 8259 spurious interrupt vector. 1223 * 1224 * IMPLICATION: The spurious interrupt vector programmed in the 1225 * 8259 is normally handled by an operating system's spurious 1226 * interrupt handler. However, a vector of 0Fh is unknown to some 1227 * operating systems, which would crash if this erratum occurred. 1228 * 1229 * In theory this could be limited to 32bit, but the handler is not 1230 * hurting and who knows which other CPUs suffer from this. 1231 */ 1232} 1233 1234static bool handle_xfd_event(struct pt_regs *regs) 1235{ 1236 u64 xfd_err; 1237 int err; 1238 1239 if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD)) 1240 return false; 1241 1242 rdmsrl(MSR_IA32_XFD_ERR, xfd_err); 1243 if (!xfd_err) 1244 return false; 1245 1246 wrmsrl(MSR_IA32_XFD_ERR, 0); 1247 1248 /* Die if that happens in kernel space */ 1249 if (WARN_ON(!user_mode(regs))) 1250 return false; 1251 1252 local_irq_enable(); 1253 1254 err = xfd_enable_feature(xfd_err); 1255 1256 switch (err) { 1257 case -EPERM: 1258 force_sig_fault(SIGILL, ILL_ILLOPC, error_get_trap_addr(regs)); 1259 break; 1260 case -EFAULT: 1261 force_sig(SIGSEGV); 1262 break; 1263 } 1264 1265 local_irq_disable(); 1266 return true; 1267} 1268 1269DEFINE_IDTENTRY(exc_device_not_available) 1270{ 1271 unsigned long cr0 = read_cr0(); 1272 1273 if (handle_xfd_event(regs)) 1274 return; 1275 1276#ifdef CONFIG_MATH_EMULATION 1277 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) { 1278 struct math_emu_info info = { }; 1279 1280 cond_local_irq_enable(regs); 1281 1282 info.regs = regs; 1283 math_emulate(&info); 1284 1285 cond_local_irq_disable(regs); 1286 return; 1287 } 1288#endif 1289 1290 /* This should not happen. */ 1291 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) { 1292 /* Try to fix it up and carry on. */ 1293 write_cr0(cr0 & ~X86_CR0_TS); 1294 } else { 1295 /* 1296 * Something terrible happened, and we're better off trying 1297 * to kill the task than getting stuck in a never-ending 1298 * loop of #NM faults. 1299 */ 1300 die("unexpected #NM exception", regs, 0); 1301 } 1302} 1303 1304#ifdef CONFIG_INTEL_TDX_GUEST 1305 1306#define VE_FAULT_STR "VE fault" 1307 1308static void ve_raise_fault(struct pt_regs *regs, long error_code, 1309 unsigned long address) 1310{ 1311 if (user_mode(regs)) { 1312 gp_user_force_sig_segv(regs, X86_TRAP_VE, error_code, VE_FAULT_STR); 1313 return; 1314 } 1315 1316 if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code, 1317 VE_FAULT_STR, address)) { 1318 return; 1319 } 1320 1321 die_addr(VE_FAULT_STR, regs, error_code, address); 1322} 1323 1324/* 1325 * Virtualization Exceptions (#VE) are delivered to TDX guests due to 1326 * specific guest actions which may happen in either user space or the 1327 * kernel: 1328 * 1329 * * Specific instructions (WBINVD, for example) 1330 * * Specific MSR accesses 1331 * * Specific CPUID leaf accesses 1332 * * Access to specific guest physical addresses 1333 * 1334 * In the settings that Linux will run in, virtualization exceptions are 1335 * never generated on accesses to normal, TD-private memory that has been 1336 * accepted (by BIOS or with tdx_enc_status_changed()). 1337 * 1338 * Syscall entry code has a critical window where the kernel stack is not 1339 * yet set up. Any exception in this window leads to hard to debug issues 1340 * and can be exploited for privilege escalation. Exceptions in the NMI 1341 * entry code also cause issues. Returning from the exception handler with 1342 * IRET will re-enable NMIs and nested NMI will corrupt the NMI stack. 1343 * 1344 * For these reasons, the kernel avoids #VEs during the syscall gap and 1345 * the NMI entry code. Entry code paths do not access TD-shared memory, 1346 * MMIO regions, use #VE triggering MSRs, instructions, or CPUID leaves 1347 * that might generate #VE. VMM can remove memory from TD at any point, 1348 * but access to unaccepted (or missing) private memory leads to VM 1349 * termination, not to #VE. 1350 * 1351 * Similarly to page faults and breakpoints, #VEs are allowed in NMI 1352 * handlers once the kernel is ready to deal with nested NMIs. 1353 * 1354 * During #VE delivery, all interrupts, including NMIs, are blocked until 1355 * TDGETVEINFO is called. It prevents #VE nesting until the kernel reads 1356 * the VE info. 1357 * 1358 * If a guest kernel action which would normally cause a #VE occurs in 1359 * the interrupt-disabled region before TDGETVEINFO, a #DF (fault 1360 * exception) is delivered to the guest which will result in an oops. 1361 * 1362 * The entry code has been audited carefully for following these expectations. 1363 * Changes in the entry code have to be audited for correctness vs. this 1364 * aspect. Similarly to #PF, #VE in these places will expose kernel to 1365 * privilege escalation or may lead to random crashes. 1366 */ 1367DEFINE_IDTENTRY(exc_virtualization_exception) 1368{ 1369 struct ve_info ve; 1370 1371 /* 1372 * NMIs/Machine-checks/Interrupts will be in a disabled state 1373 * till TDGETVEINFO TDCALL is executed. This ensures that VE 1374 * info cannot be overwritten by a nested #VE. 1375 */ 1376 tdx_get_ve_info(&ve); 1377 1378 cond_local_irq_enable(regs); 1379 1380 /* 1381 * If tdx_handle_virt_exception() could not process 1382 * it successfully, treat it as #GP(0) and handle it. 1383 */ 1384 if (!tdx_handle_virt_exception(regs, &ve)) 1385 ve_raise_fault(regs, 0, ve.gla); 1386 1387 cond_local_irq_disable(regs); 1388} 1389 1390#endif 1391 1392#ifdef CONFIG_X86_32 1393DEFINE_IDTENTRY_SW(iret_error) 1394{ 1395 local_irq_enable(); 1396 if (notify_die(DIE_TRAP, "iret exception", regs, 0, 1397 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { 1398 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0, 1399 ILL_BADSTK, (void __user *)NULL); 1400 } 1401 local_irq_disable(); 1402} 1403#endif 1404 1405/* Do not enable FRED by default yet. */ 1406static bool enable_fred __ro_after_init = false; 1407 1408#ifdef CONFIG_X86_FRED 1409static int __init fred_setup(char *str) 1410{ 1411 if (!str) 1412 return -EINVAL; 1413 1414 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 1415 return 0; 1416 1417 if (!strcmp(str, "on")) 1418 enable_fred = true; 1419 else if (!strcmp(str, "off")) 1420 enable_fred = false; 1421 else 1422 pr_warn("invalid FRED option: 'fred=%s'\n", str); 1423 return 0; 1424} 1425early_param("fred", fred_setup); 1426#endif 1427 1428void __init trap_init(void) 1429{ 1430 if (cpu_feature_enabled(X86_FEATURE_FRED) && !enable_fred) 1431 setup_clear_cpu_cap(X86_FEATURE_FRED); 1432 1433 /* Init cpu_entry_area before IST entries are set up */ 1434 setup_cpu_entry_areas(); 1435 1436 /* Init GHCB memory pages when running as an SEV-ES guest */ 1437 sev_es_init_vc_handling(); 1438 1439 /* Initialize TSS before setting up traps so ISTs work */ 1440 cpu_init_exception_handling(); 1441 1442 /* Setup traps as cpu_init() might #GP */ 1443 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 1444 idt_setup_traps(); 1445 1446 cpu_init(); 1447} 1448