1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef ARCH_X86_CPU_H
3#define ARCH_X86_CPU_H
4
5#include <asm/cpu.h>
6#include <asm/topology.h>
7
8#include "topology.h"
9
10/* attempt to consolidate cpu attributes */
11struct cpu_dev {
12	const char	*c_vendor;
13
14	/* some have two possibilities for cpuid string */
15	const char	*c_ident[2];
16
17	void            (*c_early_init)(struct cpuinfo_x86 *);
18	void		(*c_bsp_init)(struct cpuinfo_x86 *);
19	void		(*c_init)(struct cpuinfo_x86 *);
20	void		(*c_identify)(struct cpuinfo_x86 *);
21	void		(*c_detect_tlb)(struct cpuinfo_x86 *);
22	int		c_x86_vendor;
23#ifdef CONFIG_X86_32
24	/* Optional vendor specific routine to obtain the cache size. */
25	unsigned int	(*legacy_cache_size)(struct cpuinfo_x86 *,
26					     unsigned int);
27
28	/* Family/stepping-based lookup table for model names. */
29	struct legacy_cpu_model_info {
30		int		family;
31		const char	*model_names[16];
32	}		legacy_models[5];
33#endif
34};
35
36struct _tlb_table {
37	unsigned char descriptor;
38	char tlb_type;
39	unsigned int entries;
40	/* unsigned int ways; */
41	char info[128];
42};
43
44#define cpu_dev_register(cpu_devX) \
45	static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
46	__section(".x86_cpu_dev.init") = \
47	&cpu_devX;
48
49extern const struct cpu_dev *const __x86_cpu_dev_start[],
50			    *const __x86_cpu_dev_end[];
51
52#ifdef CONFIG_CPU_SUP_INTEL
53enum tsx_ctrl_states {
54	TSX_CTRL_ENABLE,
55	TSX_CTRL_DISABLE,
56	TSX_CTRL_RTM_ALWAYS_ABORT,
57	TSX_CTRL_NOT_SUPPORTED,
58};
59
60extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
61
62extern void __init tsx_init(void);
63void tsx_ap_init(void);
64#else
65static inline void tsx_init(void) { }
66static inline void tsx_ap_init(void) { }
67#endif /* CONFIG_CPU_SUP_INTEL */
68
69extern void init_spectral_chicken(struct cpuinfo_x86 *c);
70
71extern void get_cpu_cap(struct cpuinfo_x86 *c);
72extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
73extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
74extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
75extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
76extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
77extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
78
79extern void check_null_seg_clears_base(struct cpuinfo_x86 *c);
80
81void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id);
82void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c);
83
84unsigned int aperfmperf_get_khz(int cpu);
85void cpu_select_mitigations(void);
86
87extern void x86_spec_ctrl_setup_ap(void);
88extern void update_srbds_msr(void);
89extern void update_gds_msr(void);
90
91extern enum spectre_v2_mitigation spectre_v2_enabled;
92
93static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
94{
95	return mode == SPECTRE_V2_EIBRS ||
96	       mode == SPECTRE_V2_EIBRS_RETPOLINE ||
97	       mode == SPECTRE_V2_EIBRS_LFENCE;
98}
99
100#endif /* ARCH_X86_CPU_H */
101