1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * x86 TSC related functions 4 */ 5#ifndef _ASM_X86_TSC_H 6#define _ASM_X86_TSC_H 7 8#include <asm/cpufeature.h> 9#include <asm/processor.h> 10#include <asm/msr.h> 11 12/* 13 * Standard way to access the cycle counter. 14 */ 15typedef unsigned long long cycles_t; 16 17extern unsigned int cpu_khz; 18extern unsigned int tsc_khz; 19 20extern void disable_TSC(void); 21 22static inline cycles_t get_cycles(void) 23{ 24 if (!IS_ENABLED(CONFIG_X86_TSC) && 25 !cpu_feature_enabled(X86_FEATURE_TSC)) 26 return 0; 27 return rdtsc(); 28} 29#define get_cycles get_cycles 30 31extern struct system_counterval_t convert_art_to_tsc(u64 art); 32extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns); 33 34extern void tsc_early_init(void); 35extern void tsc_init(void); 36extern void mark_tsc_unstable(char *reason); 37extern int unsynchronized_tsc(void); 38extern int check_tsc_unstable(void); 39extern void mark_tsc_async_resets(char *reason); 40extern unsigned long native_calibrate_cpu_early(void); 41extern unsigned long native_calibrate_tsc(void); 42extern unsigned long long native_sched_clock_from_tsc(u64 tsc); 43 44extern int tsc_clocksource_reliable; 45#ifdef CONFIG_X86_TSC 46extern bool tsc_async_resets; 47#else 48# define tsc_async_resets false 49#endif 50 51/* 52 * Boot-time check whether the TSCs are synchronized across 53 * all CPUs/cores: 54 */ 55#ifdef CONFIG_X86_TSC 56extern bool tsc_store_and_check_tsc_adjust(bool bootcpu); 57extern void tsc_verify_tsc_adjust(bool resume); 58extern void check_tsc_sync_target(void); 59#else 60static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return false; } 61static inline void tsc_verify_tsc_adjust(bool resume) { } 62static inline void check_tsc_sync_target(void) { } 63#endif 64 65extern int notsc_setup(char *); 66extern void tsc_save_sched_clock_state(void); 67extern void tsc_restore_sched_clock_state(void); 68 69unsigned long cpu_khz_from_msr(void); 70 71#endif /* _ASM_X86_TSC_H */ 72