1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_GART_H
3#define _ASM_X86_GART_H
4
5#include <asm/e820/api.h>
6
7extern void set_up_gart_resume(u32, u32);
8
9extern int fallback_aper_order;
10extern int fallback_aper_force;
11extern int fix_aperture;
12
13/* PTE bits. */
14#define GPTE_VALID	1
15#define GPTE_COHERENT	2
16
17/* Aperture control register bits. */
18#define GARTEN		(1<<0)
19#define DISGARTCPU	(1<<4)
20#define DISGARTIO	(1<<5)
21#define DISTLBWALKPRB	(1<<6)
22
23/* GART cache control register bits. */
24#define INVGART		(1<<0)
25#define GARTPTEERR	(1<<1)
26
27/* K8 On-cpu GART registers */
28#define AMD64_GARTAPERTURECTL	0x90
29#define AMD64_GARTAPERTUREBASE	0x94
30#define AMD64_GARTTABLEBASE	0x98
31#define AMD64_GARTCACHECTL	0x9c
32
33#ifdef CONFIG_GART_IOMMU
34extern int gart_iommu_aperture;
35extern int gart_iommu_aperture_allowed;
36extern int gart_iommu_aperture_disabled;
37
38extern void early_gart_iommu_check(void);
39extern int gart_iommu_init(void);
40extern void __init gart_parse_options(char *);
41void gart_iommu_hole_init(void);
42
43#else
44#define gart_iommu_aperture            0
45#define gart_iommu_aperture_allowed    0
46#define gart_iommu_aperture_disabled   1
47
48static inline void early_gart_iommu_check(void)
49{
50}
51static inline void gart_parse_options(char *options)
52{
53}
54static inline void gart_iommu_hole_init(void)
55{
56}
57#endif
58
59extern int agp_amd64_init(void);
60
61static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
62{
63	u32 ctl;
64
65	/*
66	 * Don't enable translation but enable GART IO and CPU accesses.
67	 * Also, set DISTLBWALKPRB since GART tables memory is UC.
68	 */
69	ctl = order << 1;
70
71	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
72}
73
74static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
75{
76	u32 tmp, ctl;
77
78	/* address of the mappings table */
79	addr >>= 12;
80	tmp = (u32) addr<<4;
81	tmp &= ~0xf;
82	pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
83
84	/* Enable GART translation for this hammer. */
85	pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
86	ctl |= GARTEN | DISTLBWALKPRB;
87	ctl &= ~(DISGARTCPU | DISGARTIO);
88	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
89}
90
91static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
92{
93	if (!aper_base)
94		return 0;
95
96	if (aper_base + aper_size > 0x100000000ULL) {
97		printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
98		return 0;
99	}
100	if (e820__mapped_any(aper_base, aper_base + aper_size, E820_TYPE_RAM)) {
101		printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
102		return 0;
103	}
104	if (aper_size < min_size) {
105		printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
106				 aper_size>>20, min_size>>20);
107		return 0;
108	}
109
110	return 1;
111}
112
113#endif /* _ASM_X86_GART_H */
114