1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_APICDEF_H 3#define _ASM_X86_APICDEF_H 4 5#include <linux/bits.h> 6 7/* 8 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 9 * 10 * Alan Cox <Alan.Cox@linux.org>, 1995. 11 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 12 */ 13 14#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 15#define APIC_DEFAULT_PHYS_BASE 0xfee00000 16 17/* 18 * This is the IO-APIC register space as specified 19 * by Intel docs: 20 */ 21#define IO_APIC_SLOT_SIZE 1024 22 23#define APIC_DELIVERY_MODE_FIXED 0 24#define APIC_DELIVERY_MODE_LOWESTPRIO 1 25#define APIC_DELIVERY_MODE_SMI 2 26#define APIC_DELIVERY_MODE_NMI 4 27#define APIC_DELIVERY_MODE_INIT 5 28#define APIC_DELIVERY_MODE_EXTINT 7 29 30#define APIC_ID 0x20 31 32#define APIC_LVR 0x30 33#define APIC_LVR_MASK 0xFF00FF 34#define APIC_LVR_DIRECTED_EOI (1 << 24) 35#define GET_APIC_VERSION(x) ((x) & 0xFFu) 36#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 37#ifdef CONFIG_X86_32 38# define APIC_INTEGRATED(x) ((x) & 0xF0u) 39#else 40# define APIC_INTEGRATED(x) (1) 41#endif 42#define APIC_XAPIC(x) ((x) >= 0x14) 43#define APIC_EXT_SPACE(x) ((x) & 0x80000000) 44#define APIC_TASKPRI 0x80 45#define APIC_TPRI_MASK 0xFFu 46#define APIC_ARBPRI 0x90 47#define APIC_ARBPRI_MASK 0xFFu 48#define APIC_PROCPRI 0xA0 49#define APIC_EOI 0xB0 50#define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */ 51#define APIC_RRR 0xC0 52#define APIC_LDR 0xD0 53#define APIC_LDR_MASK (0xFFu << 24) 54#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 55#define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 56#define APIC_ALL_CPUS 0xFFu 57#define APIC_DFR 0xE0 58#define APIC_DFR_CLUSTER 0x0FFFFFFFul 59#define APIC_DFR_FLAT 0xFFFFFFFFul 60#define APIC_SPIV 0xF0 61#define APIC_SPIV_DIRECTED_EOI (1 << 12) 62#define APIC_SPIV_FOCUS_DISABLED (1 << 9) 63#define APIC_SPIV_APIC_ENABLED (1 << 8) 64#define APIC_ISR 0x100 65#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 66#define APIC_TMR 0x180 67#define APIC_IRR 0x200 68#define APIC_ESR 0x280 69#define APIC_ESR_SEND_CS 0x00001 70#define APIC_ESR_RECV_CS 0x00002 71#define APIC_ESR_SEND_ACC 0x00004 72#define APIC_ESR_RECV_ACC 0x00008 73#define APIC_ESR_SENDILL 0x00020 74#define APIC_ESR_RECVILL 0x00040 75#define APIC_ESR_ILLREGA 0x00080 76#define APIC_LVTCMCI 0x2f0 77#define APIC_ICR 0x300 78#define APIC_DEST_SELF 0x40000 79#define APIC_DEST_ALLINC 0x80000 80#define APIC_DEST_ALLBUT 0xC0000 81#define APIC_ICR_RR_MASK 0x30000 82#define APIC_ICR_RR_INVALID 0x00000 83#define APIC_ICR_RR_INPROG 0x10000 84#define APIC_ICR_RR_VALID 0x20000 85#define APIC_INT_LEVELTRIG 0x08000 86#define APIC_INT_ASSERT 0x04000 87#define APIC_ICR_BUSY 0x01000 88#define APIC_DEST_LOGICAL 0x00800 89#define APIC_DEST_PHYSICAL 0x00000 90#define APIC_DM_FIXED 0x00000 91#define APIC_DM_FIXED_MASK 0x00700 92#define APIC_DM_LOWEST 0x00100 93#define APIC_DM_SMI 0x00200 94#define APIC_DM_REMRD 0x00300 95#define APIC_DM_NMI 0x00400 96#define APIC_DM_INIT 0x00500 97#define APIC_DM_STARTUP 0x00600 98#define APIC_DM_EXTINT 0x00700 99#define APIC_VECTOR_MASK 0x000FF 100#define APIC_ICR2 0x310 101#define GET_XAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 102#define SET_XAPIC_DEST_FIELD(x) ((x) << 24) 103#define APIC_LVTT 0x320 104#define APIC_LVTTHMR 0x330 105#define APIC_LVTPC 0x340 106#define APIC_LVT0 0x350 107#define APIC_LVT_TIMER_ONESHOT (0 << 17) 108#define APIC_LVT_TIMER_PERIODIC (1 << 17) 109#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) 110#define APIC_LVT_MASKED (1 << 16) 111#define APIC_LVT_LEVEL_TRIGGER (1 << 15) 112#define APIC_LVT_REMOTE_IRR (1 << 14) 113#define APIC_INPUT_POLARITY (1 << 13) 114#define APIC_SEND_PENDING (1 << 12) 115#define APIC_MODE_MASK 0x700 116#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 117#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 118#define APIC_MODE_FIXED 0x0 119#define APIC_MODE_NMI 0x4 120#define APIC_MODE_EXTINT 0x7 121#define APIC_LVT1 0x360 122#define APIC_LVTERR 0x370 123#define APIC_TMICT 0x380 124#define APIC_TMCCT 0x390 125#define APIC_TDCR 0x3E0 126#define APIC_SELF_IPI 0x3F0 127#define APIC_TDR_DIV_TMBASE (1 << 2) 128#define APIC_TDR_DIV_1 0xB 129#define APIC_TDR_DIV_2 0x0 130#define APIC_TDR_DIV_4 0x1 131#define APIC_TDR_DIV_8 0x2 132#define APIC_TDR_DIV_16 0x3 133#define APIC_TDR_DIV_32 0x8 134#define APIC_TDR_DIV_64 0x9 135#define APIC_TDR_DIV_128 0xA 136#define APIC_EFEAT 0x400 137#define APIC_ECTRL 0x410 138#define APIC_EILVTn(n) (0x500 + 0x10 * n) 139#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 140#define APIC_EILVT_NR_AMD_10H 4 141#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H 142#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 143#define APIC_EILVT_MSG_FIX 0x0 144#define APIC_EILVT_MSG_SMI 0x2 145#define APIC_EILVT_MSG_NMI 0x4 146#define APIC_EILVT_MSG_EXT 0x7 147#define APIC_EILVT_MASKED (1 << 16) 148 149#define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 150#define APIC_BASE_MSR 0x800 151#define APIC_X2APIC_ID_MSR 0x802 152#define XAPIC_ENABLE BIT(11) 153#define X2APIC_ENABLE BIT(10) 154 155#ifdef CONFIG_X86_32 156# define MAX_IO_APICS 64 157# define MAX_LOCAL_APIC 256 158#else 159# define MAX_IO_APICS 128 160# define MAX_LOCAL_APIC 32768 161#endif 162 163/* 164 * All x86-64 systems are xAPIC compatible. 165 * In the following, "apicid" is a physical APIC ID. 166 */ 167#define XAPIC_DEST_CPUS_SHIFT 4 168#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) 169#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) 170#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) 171#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) 172#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) 173#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) 174 175#ifdef CONFIG_X86_32 176 #define BAD_APICID 0xFFu 177#else 178 #define BAD_APICID 0xFFFFu 179#endif 180 181#endif /* _ASM_X86_APICDEF_H */ 182