1// SPDX-License-Identifier: GPL-2.0 2/* 3 * leon_pci_grpci2.c: GRPCI2 Host PCI driver 4 * 5 * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom 6 * 7 */ 8 9#include <linux/kernel.h> 10#include <linux/pci.h> 11#include <linux/slab.h> 12#include <linux/delay.h> 13#include <linux/export.h> 14#include <linux/of.h> 15#include <linux/platform_device.h> 16 17#include <asm/io.h> 18#include <asm/leon.h> 19#include <asm/vaddrs.h> 20#include <asm/sections.h> 21#include <asm/leon_pci.h> 22 23#include "irq.h" 24 25struct grpci2_barcfg { 26 unsigned long pciadr; /* PCI Space Address */ 27 unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */ 28}; 29 30/* Device Node Configuration options: 31 * - barcfgs : Custom Configuration of Host's 6 target BARs 32 * - irq_mask : Limit which PCI interrupts are enabled 33 * - do_reset : Force PCI Reset on startup 34 * 35 * barcfgs 36 * ======= 37 * 38 * Optional custom Target BAR configuration (see struct grpci2_barcfg). All 39 * addresses are physical. Array always contains 6 elements (len=2*4*6 bytes) 40 * 41 * -1 means not configured (let host driver do default setup). 42 * 43 * [i*2+0] = PCI Address of BAR[i] on target interface 44 * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address 45 * 46 * 47 * irq_mask 48 * ======== 49 * 50 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default 51 * all are enabled. Use this when PCI interrupt pins are floating on PCB. 52 * int, len=4. 53 * bit0 = PCI INTA# 54 * bit1 = PCI INTB# 55 * bit2 = PCI INTC# 56 * bit3 = PCI INTD# 57 * 58 * 59 * reset 60 * ===== 61 * 62 * Force PCI reset on startup. int, len=4 63 */ 64 65/* Enable Debugging Configuration Space Access */ 66#undef GRPCI2_DEBUG_CFGACCESS 67 68/* 69 * GRPCI2 APB Register MAP 70 */ 71struct grpci2_regs { 72 unsigned int ctrl; /* 0x00 Control */ 73 unsigned int sts_cap; /* 0x04 Status / Capabilities */ 74 int res1; /* 0x08 */ 75 unsigned int io_map; /* 0x0C I/O Map address */ 76 unsigned int dma_ctrl; /* 0x10 DMA */ 77 unsigned int dma_bdbase; /* 0x14 DMA */ 78 int res2[2]; /* 0x18 */ 79 unsigned int bars[6]; /* 0x20 read-only PCI BARs */ 80 int res3[2]; /* 0x38 */ 81 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */ 82 83 /* PCI Trace Buffer Registers (OPTIONAL) */ 84 unsigned int t_ctrl; /* 0x80 */ 85 unsigned int t_cnt; /* 0x84 */ 86 unsigned int t_adpat; /* 0x88 */ 87 unsigned int t_admask; /* 0x8C */ 88 unsigned int t_sigpat; /* 0x90 */ 89 unsigned int t_sigmask; /* 0x94 */ 90 unsigned int t_adstate; /* 0x98 */ 91 unsigned int t_sigstate; /* 0x9C */ 92}; 93 94#define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a)))) 95#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a))) 96 97#define CTRL_BUS_BIT 16 98 99#define CTRL_RESET (1<<31) 100#define CTRL_SI (1<<27) 101#define CTRL_PE (1<<26) 102#define CTRL_EI (1<<25) 103#define CTRL_ER (1<<24) 104#define CTRL_BUS (0xff<<CTRL_BUS_BIT) 105#define CTRL_HOSTINT 0xf 106 107#define STS_HOST_BIT 31 108#define STS_MST_BIT 30 109#define STS_TAR_BIT 29 110#define STS_DMA_BIT 28 111#define STS_DI_BIT 27 112#define STS_HI_BIT 26 113#define STS_IRQMODE_BIT 24 114#define STS_TRACE_BIT 23 115#define STS_CFGERRVALID_BIT 20 116#define STS_CFGERR_BIT 19 117#define STS_INTTYPE_BIT 12 118#define STS_INTSTS_BIT 8 119#define STS_FDEPTH_BIT 2 120#define STS_FNUM_BIT 0 121 122#define STS_HOST (1<<STS_HOST_BIT) 123#define STS_MST (1<<STS_MST_BIT) 124#define STS_TAR (1<<STS_TAR_BIT) 125#define STS_DMA (1<<STS_DMA_BIT) 126#define STS_DI (1<<STS_DI_BIT) 127#define STS_HI (1<<STS_HI_BIT) 128#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT) 129#define STS_TRACE (1<<STS_TRACE_BIT) 130#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT) 131#define STS_CFGERR (1<<STS_CFGERR_BIT) 132#define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT) 133#define STS_INTSTS (0xf<<STS_INTSTS_BIT) 134#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT) 135#define STS_FNUM (0x3<<STS_FNUM_BIT) 136 137#define STS_ISYSERR (1<<17) 138#define STS_IDMA (1<<16) 139#define STS_IDMAERR (1<<15) 140#define STS_IMSTABRT (1<<14) 141#define STS_ITGTABRT (1<<13) 142#define STS_IPARERR (1<<12) 143 144#define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR) 145 146struct grpci2_bd_chan { 147 unsigned int ctrl; /* 0x00 DMA Control */ 148 unsigned int nchan; /* 0x04 Next DMA Channel Address */ 149 unsigned int nbd; /* 0x08 Next Data Descriptor in chan */ 150 unsigned int res; /* 0x0C Reserved */ 151}; 152 153#define BD_CHAN_EN 0x80000000 154#define BD_CHAN_TYPE 0x00300000 155#define BD_CHAN_BDCNT 0x0000ffff 156#define BD_CHAN_EN_BIT 31 157#define BD_CHAN_TYPE_BIT 20 158#define BD_CHAN_BDCNT_BIT 0 159 160struct grpci2_bd_data { 161 unsigned int ctrl; /* 0x00 DMA Data Control */ 162 unsigned int pci_adr; /* 0x04 PCI Start Address */ 163 unsigned int ahb_adr; /* 0x08 AHB Start address */ 164 unsigned int next; /* 0x0C Next Data Descriptor in chan */ 165}; 166 167#define BD_DATA_EN 0x80000000 168#define BD_DATA_IE 0x40000000 169#define BD_DATA_DR 0x20000000 170#define BD_DATA_TYPE 0x00300000 171#define BD_DATA_ER 0x00080000 172#define BD_DATA_LEN 0x0000ffff 173#define BD_DATA_EN_BIT 31 174#define BD_DATA_IE_BIT 30 175#define BD_DATA_DR_BIT 29 176#define BD_DATA_TYPE_BIT 20 177#define BD_DATA_ER_BIT 19 178#define BD_DATA_LEN_BIT 0 179 180/* GRPCI2 Capability */ 181struct grpci2_cap_first { 182 unsigned int ctrl; 183 unsigned int pci2ahb_map[6]; 184 unsigned int ext2ahb_map; 185 unsigned int io_map; 186 unsigned int pcibar_size[6]; 187}; 188#define CAP9_CTRL_OFS 0 189#define CAP9_BAR_OFS 0x4 190#define CAP9_IOMAP_OFS 0x20 191#define CAP9_BARSIZE_OFS 0x24 192 193#define TGT 256 194 195struct grpci2_priv { 196 struct leon_pci_info info; /* must be on top of this structure */ 197 struct grpci2_regs __iomem *regs; 198 char irq; 199 char irq_mode; /* IRQ Mode from CAPSTS REG */ 200 char bt_enabled; 201 char do_reset; 202 char irq_mask; 203 u32 pciid; /* PCI ID of Host */ 204 unsigned char irq_map[4]; 205 206 /* Virtual IRQ numbers */ 207 unsigned int virq_err; 208 unsigned int virq_dma; 209 210 /* AHB PCI Windows */ 211 unsigned long pci_area; /* MEMORY */ 212 unsigned long pci_area_end; 213 unsigned long pci_io; /* I/O */ 214 unsigned long pci_conf; /* CONFIGURATION */ 215 unsigned long pci_conf_end; 216 unsigned long pci_io_va; 217 218 struct grpci2_barcfg tgtbars[6]; 219}; 220 221static DEFINE_SPINLOCK(grpci2_dev_lock); 222static struct grpci2_priv *grpci2priv; 223 224static int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 225{ 226 struct grpci2_priv *priv = dev->bus->sysdata; 227 int irq_group; 228 229 /* Use default IRQ decoding on PCI BUS0 according slot numbering */ 230 irq_group = slot & 0x3; 231 pin = ((pin - 1) + irq_group) & 0x3; 232 233 return priv->irq_map[pin]; 234} 235 236static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus, 237 unsigned int devfn, int where, u32 *val) 238{ 239 unsigned int *pci_conf; 240 unsigned long flags; 241 u32 tmp; 242 243 if (where & 0x3) 244 return -EINVAL; 245 246 if (bus == 0) { 247 devfn += (0x8 * 6); /* start at AD16=Device0 */ 248 } else if (bus == TGT) { 249 bus = 0; 250 devfn = 0; /* special case: bridge controller itself */ 251 } 252 253 /* Select bus */ 254 spin_lock_irqsave(&grpci2_dev_lock, flags); 255 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) | 256 (bus << 16)); 257 spin_unlock_irqrestore(&grpci2_dev_lock, flags); 258 259 /* clear old status */ 260 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID)); 261 262 pci_conf = (unsigned int *) (priv->pci_conf | 263 (devfn << 8) | (where & 0xfc)); 264 tmp = LEON3_BYPASS_LOAD_PA(pci_conf); 265 266 /* Wait until GRPCI2 signals that CFG access is done, it should be 267 * done instantaneously unless a DMA operation is ongoing... 268 */ 269 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0) 270 ; 271 272 if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) { 273 *val = 0xffffffff; 274 } else { 275 /* Bus always little endian (unaffected by byte-swapping) */ 276 *val = swab32(tmp); 277 } 278 279 return 0; 280} 281 282static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus, 283 unsigned int devfn, int where, u32 *val) 284{ 285 u32 v; 286 int ret; 287 288 if (where & 0x1) 289 return -EINVAL; 290 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v); 291 *val = 0xffff & (v >> (8 * (where & 0x3))); 292 return ret; 293} 294 295static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus, 296 unsigned int devfn, int where, u32 *val) 297{ 298 u32 v; 299 int ret; 300 301 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v); 302 *val = 0xff & (v >> (8 * (where & 3))); 303 304 return ret; 305} 306 307static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus, 308 unsigned int devfn, int where, u32 val) 309{ 310 unsigned int *pci_conf; 311 unsigned long flags; 312 313 if (where & 0x3) 314 return -EINVAL; 315 316 if (bus == 0) { 317 devfn += (0x8 * 6); /* start at AD16=Device0 */ 318 } else if (bus == TGT) { 319 bus = 0; 320 devfn = 0; /* special case: bridge controller itself */ 321 } 322 323 /* Select bus */ 324 spin_lock_irqsave(&grpci2_dev_lock, flags); 325 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) | 326 (bus << 16)); 327 spin_unlock_irqrestore(&grpci2_dev_lock, flags); 328 329 /* clear old status */ 330 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID)); 331 332 pci_conf = (unsigned int *) (priv->pci_conf | 333 (devfn << 8) | (where & 0xfc)); 334 LEON3_BYPASS_STORE_PA(pci_conf, swab32(val)); 335 336 /* Wait until GRPCI2 signals that CFG access is done, it should be 337 * done instantaneously unless a DMA operation is ongoing... 338 */ 339 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0) 340 ; 341 342 return 0; 343} 344 345static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus, 346 unsigned int devfn, int where, u32 val) 347{ 348 int ret; 349 u32 v; 350 351 if (where & 0x1) 352 return -EINVAL; 353 ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v); 354 if (ret) 355 return ret; 356 v = (v & ~(0xffff << (8 * (where & 0x3)))) | 357 ((0xffff & val) << (8 * (where & 0x3))); 358 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v); 359} 360 361static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus, 362 unsigned int devfn, int where, u32 val) 363{ 364 int ret; 365 u32 v; 366 367 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v); 368 if (ret != 0) 369 return ret; 370 v = (v & ~(0xff << (8 * (where & 0x3)))) | 371 ((0xff & val) << (8 * (where & 0x3))); 372 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v); 373} 374 375/* Read from Configuration Space. When entering here the PCI layer has taken 376 * the pci_lock spinlock and IRQ is off. 377 */ 378static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn, 379 int where, int size, u32 *val) 380{ 381 struct grpci2_priv *priv = grpci2priv; 382 unsigned int busno = bus->number; 383 int ret; 384 385 if (PCI_SLOT(devfn) > 15 || busno > 255) { 386 *val = ~0; 387 return 0; 388 } 389 390 switch (size) { 391 case 1: 392 ret = grpci2_cfg_r8(priv, busno, devfn, where, val); 393 break; 394 case 2: 395 ret = grpci2_cfg_r16(priv, busno, devfn, where, val); 396 break; 397 case 4: 398 ret = grpci2_cfg_r32(priv, busno, devfn, where, val); 399 break; 400 default: 401 ret = -EINVAL; 402 break; 403 } 404 405#ifdef GRPCI2_DEBUG_CFGACCESS 406 printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x " 407 "size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, 408 *val, size); 409#endif 410 411 return ret; 412} 413 414/* Write to Configuration Space. When entering here the PCI layer has taken 415 * the pci_lock spinlock and IRQ is off. 416 */ 417static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn, 418 int where, int size, u32 val) 419{ 420 struct grpci2_priv *priv = grpci2priv; 421 unsigned int busno = bus->number; 422 423 if (PCI_SLOT(devfn) > 15 || busno > 255) 424 return 0; 425 426#ifdef GRPCI2_DEBUG_CFGACCESS 427 printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d " 428 "val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), 429 where, size, val); 430#endif 431 432 switch (size) { 433 default: 434 return -EINVAL; 435 case 1: 436 return grpci2_cfg_w8(priv, busno, devfn, where, val); 437 case 2: 438 return grpci2_cfg_w16(priv, busno, devfn, where, val); 439 case 4: 440 return grpci2_cfg_w32(priv, busno, devfn, where, val); 441 } 442} 443 444static struct pci_ops grpci2_ops = { 445 .read = grpci2_read_config, 446 .write = grpci2_write_config, 447}; 448 449/* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration 450 * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller 451 * this is not needed and the standard IRQ controller can be used. 452 */ 453 454static void grpci2_mask_irq(struct irq_data *data) 455{ 456 unsigned long flags; 457 unsigned int irqidx; 458 struct grpci2_priv *priv = grpci2priv; 459 460 irqidx = (unsigned int)data->chip_data - 1; 461 if (irqidx > 3) /* only mask PCI interrupts here */ 462 return; 463 464 spin_lock_irqsave(&grpci2_dev_lock, flags); 465 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx)); 466 spin_unlock_irqrestore(&grpci2_dev_lock, flags); 467} 468 469static void grpci2_unmask_irq(struct irq_data *data) 470{ 471 unsigned long flags; 472 unsigned int irqidx; 473 struct grpci2_priv *priv = grpci2priv; 474 475 irqidx = (unsigned int)data->chip_data - 1; 476 if (irqidx > 3) /* only unmask PCI interrupts here */ 477 return; 478 479 spin_lock_irqsave(&grpci2_dev_lock, flags); 480 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx)); 481 spin_unlock_irqrestore(&grpci2_dev_lock, flags); 482} 483 484static unsigned int grpci2_startup_irq(struct irq_data *data) 485{ 486 grpci2_unmask_irq(data); 487 return 0; 488} 489 490static void grpci2_shutdown_irq(struct irq_data *data) 491{ 492 grpci2_mask_irq(data); 493} 494 495static struct irq_chip grpci2_irq = { 496 .name = "grpci2", 497 .irq_startup = grpci2_startup_irq, 498 .irq_shutdown = grpci2_shutdown_irq, 499 .irq_mask = grpci2_mask_irq, 500 .irq_unmask = grpci2_unmask_irq, 501}; 502 503/* Handle one or multiple IRQs from the PCI core */ 504static void grpci2_pci_flow_irq(struct irq_desc *desc) 505{ 506 struct grpci2_priv *priv = grpci2priv; 507 int i, ack = 0; 508 unsigned int ctrl, sts_cap, pci_ints; 509 510 ctrl = REGLOAD(priv->regs->ctrl); 511 sts_cap = REGLOAD(priv->regs->sts_cap); 512 513 /* Error Interrupt? */ 514 if (sts_cap & STS_ERR_IRQ) { 515 generic_handle_irq(priv->virq_err); 516 ack = 1; 517 } 518 519 /* PCI Interrupt? */ 520 pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT; 521 if (pci_ints) { 522 /* Call respective PCI Interrupt handler */ 523 for (i = 0; i < 4; i++) { 524 if (pci_ints & (1 << i)) 525 generic_handle_irq(priv->irq_map[i]); 526 } 527 ack = 1; 528 } 529 530 /* 531 * Decode DMA Interrupt only when shared with Err and PCI INTX#, when 532 * the DMA is a unique IRQ the DMA interrupts doesn't end up here, they 533 * goes directly to DMA ISR. 534 */ 535 if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) { 536 generic_handle_irq(priv->virq_dma); 537 ack = 1; 538 } 539 540 /* 541 * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ 542 * Controller, this must be done after IRQ sources have been handled to 543 * avoid double IRQ generation 544 */ 545 if (ack) 546 desc->irq_data.chip->irq_eoi(&desc->irq_data); 547} 548 549/* Create a virtual IRQ */ 550static unsigned int grpci2_build_device_irq(unsigned int irq) 551{ 552 unsigned int virq = 0, pil; 553 554 pil = 1 << 8; 555 virq = irq_alloc(irq, pil); 556 if (virq == 0) 557 goto out; 558 559 irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq, 560 "pcilvl"); 561 irq_set_chip_data(virq, (void *)irq); 562 563out: 564 return virq; 565} 566 567static void grpci2_hw_init(struct grpci2_priv *priv) 568{ 569 u32 ahbadr, pciadr, bar_sz, capptr, io_map, data; 570 struct grpci2_regs __iomem *regs = priv->regs; 571 int i; 572 struct grpci2_barcfg *barcfg = priv->tgtbars; 573 574 /* Reset any earlier setup */ 575 if (priv->do_reset) { 576 printk(KERN_INFO "GRPCI2: Resetting PCI bus\n"); 577 REGSTORE(regs->ctrl, CTRL_RESET); 578 ssleep(1); /* Wait for boards to settle */ 579 } 580 REGSTORE(regs->ctrl, 0); 581 REGSTORE(regs->sts_cap, ~0); /* Clear Status */ 582 REGSTORE(regs->dma_ctrl, 0); 583 REGSTORE(regs->dma_bdbase, 0); 584 585 /* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */ 586 REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff); 587 588 /* set 1:1 mapping between AHB -> PCI memory space, for all Masters 589 * Each AHB master has its own mapping registers. Max 16 AHB masters. 590 */ 591 for (i = 0; i < 16; i++) 592 REGSTORE(regs->ahbmst_map[i], priv->pci_area); 593 594 /* Get the GRPCI2 Host PCI ID */ 595 grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid); 596 597 /* Get address to first (always defined) capability structure */ 598 grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr); 599 600 /* Enable/Disable Byte twisting */ 601 grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map); 602 io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0); 603 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map); 604 605 /* Setup the Host's PCI Target BARs for other peripherals to access, 606 * and do DMA to the host's memory. The target BARs can be sized and 607 * enabled individually. 608 * 609 * User may set custom target BARs, but default is: 610 * The first BARs is used to map kernel low (DMA is part of normal 611 * region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the 612 * PCI bus, the other BARs are disabled. We assume that the first BAR 613 * is always available. 614 */ 615 for (i = 0; i < 6; i++) { 616 if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) { 617 /* Target BARs must have the proper alignment */ 618 ahbadr = barcfg[i].ahbadr; 619 pciadr = barcfg[i].pciadr; 620 bar_sz = ((pciadr - 1) & ~pciadr) + 1; 621 } else { 622 if (i == 0) { 623 /* Map main memory */ 624 bar_sz = 0xf0000008; /* 256MB prefetchable */ 625 ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN( 626 (unsigned long) &_end)); 627 pciadr = ahbadr; 628 } else { 629 bar_sz = 0; 630 ahbadr = 0; 631 pciadr = 0; 632 } 633 } 634 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4, 635 bar_sz); 636 grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr); 637 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr); 638 printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n", 639 i, pciadr, ahbadr); 640 } 641 642 /* set as bus master and enable pci memory responses */ 643 grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data); 644 data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 645 grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data); 646 647 /* Enable Error respone (CPU-TRAP) on illegal memory access. */ 648 REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE); 649} 650 651static irqreturn_t grpci2_jump_interrupt(int irq, void *arg) 652{ 653 printk(KERN_ERR "GRPCI2: Jump IRQ happened\n"); 654 return IRQ_NONE; 655} 656 657/* Handle GRPCI2 Error Interrupt */ 658static irqreturn_t grpci2_err_interrupt(int irq, void *arg) 659{ 660 struct grpci2_priv *priv = arg; 661 struct grpci2_regs __iomem *regs = priv->regs; 662 unsigned int status; 663 664 status = REGLOAD(regs->sts_cap); 665 if ((status & STS_ERR_IRQ) == 0) 666 return IRQ_NONE; 667 668 if (status & STS_IPARERR) 669 printk(KERN_ERR "GRPCI2: Parity Error\n"); 670 671 if (status & STS_ITGTABRT) 672 printk(KERN_ERR "GRPCI2: Target Abort\n"); 673 674 if (status & STS_IMSTABRT) 675 printk(KERN_ERR "GRPCI2: Master Abort\n"); 676 677 if (status & STS_ISYSERR) 678 printk(KERN_ERR "GRPCI2: System Error\n"); 679 680 /* Clear handled INT TYPE IRQs */ 681 REGSTORE(regs->sts_cap, status & STS_ERR_IRQ); 682 683 return IRQ_HANDLED; 684} 685 686static int grpci2_of_probe(struct platform_device *ofdev) 687{ 688 struct grpci2_regs __iomem *regs; 689 struct grpci2_priv *priv; 690 int err, i, len; 691 const int *tmp; 692 unsigned int capability; 693 694 if (grpci2priv) { 695 printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n"); 696 return -ENODEV; 697 } 698 699 if (ofdev->num_resources < 3) { 700 printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n"); 701 return -EIO; 702 } 703 704 /* Find Device Address */ 705 regs = of_ioremap(&ofdev->resource[0], 0, 706 resource_size(&ofdev->resource[0]), 707 "grlib-grpci2 regs"); 708 if (regs == NULL) { 709 printk(KERN_ERR "GRPCI2: ioremap failed\n"); 710 return -EIO; 711 } 712 713 /* 714 * Check that we're in Host Slot and that we can act as a Host Bridge 715 * and not only as target. 716 */ 717 capability = REGLOAD(regs->sts_cap); 718 if ((capability & STS_HOST) || !(capability & STS_MST)) { 719 printk(KERN_INFO "GRPCI2: not in host system slot\n"); 720 err = -EIO; 721 goto err1; 722 } 723 724 priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL); 725 if (grpci2priv == NULL) { 726 err = -ENOMEM; 727 goto err1; 728 } 729 priv->regs = regs; 730 priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */ 731 priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT; 732 733 printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq); 734 735 /* Byte twisting should be made configurable from kernel command line */ 736 priv->bt_enabled = 1; 737 738 /* Let user do custom Target BAR assignment */ 739 tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len); 740 if (tmp && (len == 2*4*6)) 741 memcpy(priv->tgtbars, tmp, 2*4*6); 742 else 743 memset(priv->tgtbars, -1, 2*4*6); 744 745 /* Limit IRQ unmasking in irq_mode 2 and 3 */ 746 tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len); 747 if (tmp && (len == 4)) 748 priv->do_reset = *tmp; 749 else 750 priv->irq_mask = 0xf; 751 752 /* Optional PCI reset. Force PCI reset on startup */ 753 tmp = of_get_property(ofdev->dev.of_node, "reset", &len); 754 if (tmp && (len == 4)) 755 priv->do_reset = *tmp; 756 else 757 priv->do_reset = 0; 758 759 /* Find PCI Memory, I/O and Configuration Space Windows */ 760 priv->pci_area = ofdev->resource[1].start; 761 priv->pci_area_end = ofdev->resource[1].end+1; 762 priv->pci_io = ofdev->resource[2].start; 763 priv->pci_conf = ofdev->resource[2].start + 0x10000; 764 priv->pci_conf_end = priv->pci_conf + 0x10000; 765 priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000); 766 if (!priv->pci_io_va) { 767 err = -EIO; 768 goto err2; 769 } 770 771 printk(KERN_INFO 772 "GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n" 773 " I/O SPACE [0x%08lx - 0x%08lx]\n" 774 " CONFIG SPACE [0x%08lx - 0x%08lx]\n", 775 priv->pci_area, priv->pci_area_end-1, 776 priv->pci_io, priv->pci_conf-1, 777 priv->pci_conf, priv->pci_conf_end-1); 778 779 /* 780 * I/O Space resources in I/O Window mapped into Virtual Adr Space 781 * We never use low 4KB because some devices seem have problems using 782 * address 0. 783 */ 784 memset(&priv->info.io_space, 0, sizeof(struct resource)); 785 priv->info.io_space.name = "GRPCI2 PCI I/O Space"; 786 priv->info.io_space.start = priv->pci_io_va + 0x1000; 787 priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1; 788 priv->info.io_space.flags = IORESOURCE_IO; 789 790 /* 791 * GRPCI2 has no prefetchable memory, map everything as 792 * non-prefetchable memory 793 */ 794 memset(&priv->info.mem_space, 0, sizeof(struct resource)); 795 priv->info.mem_space.name = "GRPCI2 PCI MEM Space"; 796 priv->info.mem_space.start = priv->pci_area; 797 priv->info.mem_space.end = priv->pci_area_end - 1; 798 priv->info.mem_space.flags = IORESOURCE_MEM; 799 800 if (request_resource(&iomem_resource, &priv->info.mem_space) < 0) 801 goto err3; 802 if (request_resource(&ioport_resource, &priv->info.io_space) < 0) 803 goto err4; 804 805 /* setup maximum supported PCI buses */ 806 priv->info.busn.name = "GRPCI2 busn"; 807 priv->info.busn.start = 0; 808 priv->info.busn.end = 255; 809 810 grpci2_hw_init(priv); 811 812 /* 813 * Get PCI Interrupt to System IRQ mapping and setup IRQ handling 814 * Error IRQ always on PCI INTA. 815 */ 816 if (priv->irq_mode < 2) { 817 /* All PCI interrupts are shared using the same system IRQ */ 818 leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq, 819 "pcilvl", 0); 820 821 priv->irq_map[0] = grpci2_build_device_irq(1); 822 priv->irq_map[1] = grpci2_build_device_irq(2); 823 priv->irq_map[2] = grpci2_build_device_irq(3); 824 priv->irq_map[3] = grpci2_build_device_irq(4); 825 826 priv->virq_err = grpci2_build_device_irq(5); 827 if (priv->irq_mode & 1) 828 priv->virq_dma = ofdev->archdata.irqs[1]; 829 else 830 priv->virq_dma = grpci2_build_device_irq(6); 831 832 /* Enable IRQs on LEON IRQ controller */ 833 err = request_irq(priv->irq, grpci2_jump_interrupt, 0, 834 "GRPCI2_JUMP", priv); 835 if (err) 836 printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n"); 837 } else { 838 /* All PCI interrupts have an unique IRQ interrupt */ 839 for (i = 0; i < 4; i++) { 840 /* Make LEON IRQ layer handle level IRQ by acking */ 841 leon_update_virq_handling(ofdev->archdata.irqs[i], 842 handle_fasteoi_irq, "pcilvl", 843 1); 844 priv->irq_map[i] = ofdev->archdata.irqs[i]; 845 } 846 priv->virq_err = priv->irq_map[0]; 847 if (priv->irq_mode & 1) 848 priv->virq_dma = ofdev->archdata.irqs[4]; 849 else 850 priv->virq_dma = priv->irq_map[0]; 851 852 /* Unmask all PCI interrupts, request_irq will not do that */ 853 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf)); 854 } 855 856 /* Setup IRQ handler for non-configuration space access errors */ 857 err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED, 858 "GRPCI2_ERR", priv); 859 if (err) { 860 printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err); 861 goto err5; 862 } 863 864 /* 865 * Enable Error Interrupts. PCI interrupts are unmasked once request_irq 866 * is called by the PCI Device drivers 867 */ 868 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI); 869 870 /* Init common layer and scan buses */ 871 priv->info.ops = &grpci2_ops; 872 priv->info.map_irq = grpci2_map_irq; 873 leon_pci_init(ofdev, &priv->info); 874 875 return 0; 876 877err5: 878 release_resource(&priv->info.io_space); 879err4: 880 release_resource(&priv->info.mem_space); 881err3: 882 err = -ENOMEM; 883 iounmap((void __iomem *)priv->pci_io_va); 884err2: 885 kfree(priv); 886err1: 887 of_iounmap(&ofdev->resource[0], regs, 888 resource_size(&ofdev->resource[0])); 889 return err; 890} 891 892static const struct of_device_id grpci2_of_match[] = { 893 { 894 .name = "GAISLER_GRPCI2", 895 }, 896 { 897 .name = "01_07c", 898 }, 899 {}, 900}; 901 902static struct platform_driver grpci2_of_driver = { 903 .driver = { 904 .name = "grpci2", 905 .of_match_table = grpci2_of_match, 906 }, 907 .probe = grpci2_of_probe, 908}; 909 910static int __init grpci2_init(void) 911{ 912 return platform_driver_register(&grpci2_of_driver); 913} 914 915subsys_initcall(grpci2_init); 916