1// SPDX-License-Identifier: GPL-2.0-only 2/* chmc.c: Driver for UltraSPARC-III memory controller. 3 * 4 * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net) 5 */ 6 7#include <linux/module.h> 8#include <linux/kernel.h> 9#include <linux/types.h> 10#include <linux/slab.h> 11#include <linux/list.h> 12#include <linux/string.h> 13#include <linux/sched.h> 14#include <linux/smp.h> 15#include <linux/errno.h> 16#include <linux/init.h> 17#include <linux/of.h> 18#include <linux/of_platform.h> 19#include <linux/platform_device.h> 20#include <asm/spitfire.h> 21#include <asm/chmctrl.h> 22#include <asm/cpudata.h> 23#include <asm/oplib.h> 24#include <asm/prom.h> 25#include <asm/head.h> 26#include <asm/io.h> 27#include <asm/memctrl.h> 28 29#define DRV_MODULE_NAME "chmc" 30#define PFX DRV_MODULE_NAME ": " 31#define DRV_MODULE_VERSION "0.2" 32 33MODULE_AUTHOR("David S. Miller <davem@davemloft.net>"); 34MODULE_DESCRIPTION("UltraSPARC-III memory controller driver"); 35MODULE_LICENSE("GPL"); 36MODULE_VERSION(DRV_MODULE_VERSION); 37 38static int mc_type; 39#define MC_TYPE_SAFARI 1 40#define MC_TYPE_JBUS 2 41 42static dimm_printer_t us3mc_dimm_printer; 43 44#define CHMCTRL_NDGRPS 2 45#define CHMCTRL_NDIMMS 4 46 47#define CHMC_DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS) 48 49/* OBP memory-layout property format. */ 50struct chmc_obp_map { 51 unsigned char dimm_map[144]; 52 unsigned char pin_map[576]; 53}; 54 55#define DIMM_LABEL_SZ 8 56 57struct chmc_obp_mem_layout { 58 /* One max 8-byte string label per DIMM. Usually 59 * this matches the label on the motherboard where 60 * that DIMM resides. 61 */ 62 char dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ]; 63 64 /* If symmetric use map[0], else it is 65 * asymmetric and map[1] should be used. 66 */ 67 char symmetric; 68 69 struct chmc_obp_map map[2]; 70}; 71 72#define CHMCTRL_NBANKS 4 73 74struct chmc_bank_info { 75 struct chmc *p; 76 int bank_id; 77 78 u64 raw_reg; 79 int valid; 80 int uk; 81 int um; 82 int lk; 83 int lm; 84 int interleave; 85 unsigned long base; 86 unsigned long size; 87}; 88 89struct chmc { 90 struct list_head list; 91 int portid; 92 93 struct chmc_obp_mem_layout layout_prop; 94 int layout_size; 95 96 void __iomem *regs; 97 98 u64 timing_control1; 99 u64 timing_control2; 100 u64 timing_control3; 101 u64 timing_control4; 102 u64 memaddr_control; 103 104 struct chmc_bank_info logical_banks[CHMCTRL_NBANKS]; 105}; 106 107#define JBUSMC_REGS_SIZE 8 108 109#define JB_MC_REG1_DIMM2_BANK3 0x8000000000000000UL 110#define JB_MC_REG1_DIMM1_BANK1 0x4000000000000000UL 111#define JB_MC_REG1_DIMM2_BANK2 0x2000000000000000UL 112#define JB_MC_REG1_DIMM1_BANK0 0x1000000000000000UL 113#define JB_MC_REG1_XOR 0x0000010000000000UL 114#define JB_MC_REG1_ADDR_GEN_2 0x000000e000000000UL 115#define JB_MC_REG1_ADDR_GEN_2_SHIFT 37 116#define JB_MC_REG1_ADDR_GEN_1 0x0000001c00000000UL 117#define JB_MC_REG1_ADDR_GEN_1_SHIFT 34 118#define JB_MC_REG1_INTERLEAVE 0x0000000001800000UL 119#define JB_MC_REG1_INTERLEAVE_SHIFT 23 120#define JB_MC_REG1_DIMM2_PTYPE 0x0000000000200000UL 121#define JB_MC_REG1_DIMM2_PTYPE_SHIFT 21 122#define JB_MC_REG1_DIMM1_PTYPE 0x0000000000100000UL 123#define JB_MC_REG1_DIMM1_PTYPE_SHIFT 20 124 125#define PART_TYPE_X8 0 126#define PART_TYPE_X4 1 127 128#define INTERLEAVE_NONE 0 129#define INTERLEAVE_SAME 1 130#define INTERLEAVE_INTERNAL 2 131#define INTERLEAVE_BOTH 3 132 133#define ADDR_GEN_128MB 0 134#define ADDR_GEN_256MB 1 135#define ADDR_GEN_512MB 2 136#define ADDR_GEN_1GB 3 137 138#define JB_NUM_DIMM_GROUPS 2 139#define JB_NUM_DIMMS_PER_GROUP 2 140#define JB_NUM_DIMMS (JB_NUM_DIMM_GROUPS * JB_NUM_DIMMS_PER_GROUP) 141 142struct jbusmc_obp_map { 143 unsigned char dimm_map[18]; 144 unsigned char pin_map[144]; 145}; 146 147struct jbusmc_obp_mem_layout { 148 /* One max 8-byte string label per DIMM. Usually 149 * this matches the label on the motherboard where 150 * that DIMM resides. 151 */ 152 char dimm_labels[JB_NUM_DIMMS][DIMM_LABEL_SZ]; 153 154 /* If symmetric use map[0], else it is 155 * asymmetric and map[1] should be used. 156 */ 157 char symmetric; 158 159 struct jbusmc_obp_map map; 160 161 char _pad; 162}; 163 164struct jbusmc_dimm_group { 165 struct jbusmc *controller; 166 int index; 167 u64 base_addr; 168 u64 size; 169}; 170 171struct jbusmc { 172 void __iomem *regs; 173 u64 mc_reg_1; 174 u32 portid; 175 struct jbusmc_obp_mem_layout layout; 176 int layout_len; 177 int num_dimm_groups; 178 struct jbusmc_dimm_group dimm_groups[JB_NUM_DIMM_GROUPS]; 179 struct list_head list; 180}; 181 182static DEFINE_SPINLOCK(mctrl_list_lock); 183static LIST_HEAD(mctrl_list); 184 185static void mc_list_add(struct list_head *list) 186{ 187 spin_lock(&mctrl_list_lock); 188 list_add(list, &mctrl_list); 189 spin_unlock(&mctrl_list_lock); 190} 191 192static void mc_list_del(struct list_head *list) 193{ 194 spin_lock(&mctrl_list_lock); 195 list_del_init(list); 196 spin_unlock(&mctrl_list_lock); 197} 198 199#define SYNDROME_MIN -1 200#define SYNDROME_MAX 144 201 202/* Covert syndrome code into the way the bits are positioned 203 * on the bus. 204 */ 205static int syndrome_to_qword_code(int syndrome_code) 206{ 207 if (syndrome_code < 128) 208 syndrome_code += 16; 209 else if (syndrome_code < 128 + 9) 210 syndrome_code -= (128 - 7); 211 else if (syndrome_code < (128 + 9 + 3)) 212 syndrome_code -= (128 + 9 - 4); 213 else 214 syndrome_code -= (128 + 9 + 3); 215 return syndrome_code; 216} 217 218/* All this magic has to do with how a cache line comes over the wire 219 * on Safari and JBUS. A 64-bit line comes over in 1 or more quadword 220 * cycles, each of which transmit ECC/MTAG info as well as the actual 221 * data. 222 */ 223#define L2_LINE_SIZE 64 224#define L2_LINE_ADDR_MSK (L2_LINE_SIZE - 1) 225#define QW_PER_LINE 4 226#define QW_BYTES (L2_LINE_SIZE / QW_PER_LINE) 227#define QW_BITS 144 228#define SAFARI_LAST_BIT (576 - 1) 229#define JBUS_LAST_BIT (144 - 1) 230 231static void get_pin_and_dimm_str(int syndrome_code, unsigned long paddr, 232 int *pin_p, char **dimm_str_p, void *_prop, 233 int base_dimm_offset) 234{ 235 int qword_code = syndrome_to_qword_code(syndrome_code); 236 int cache_line_offset; 237 int offset_inverse; 238 int dimm_map_index; 239 int map_val; 240 241 if (mc_type == MC_TYPE_JBUS) { 242 struct jbusmc_obp_mem_layout *p = _prop; 243 244 /* JBUS */ 245 cache_line_offset = qword_code; 246 offset_inverse = (JBUS_LAST_BIT - cache_line_offset); 247 dimm_map_index = offset_inverse / 8; 248 map_val = p->map.dimm_map[dimm_map_index]; 249 map_val = ((map_val >> ((7 - (offset_inverse & 7)))) & 1); 250 *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val]; 251 *pin_p = p->map.pin_map[cache_line_offset]; 252 } else { 253 struct chmc_obp_mem_layout *p = _prop; 254 struct chmc_obp_map *mp; 255 int qword; 256 257 /* Safari */ 258 if (p->symmetric) 259 mp = &p->map[0]; 260 else 261 mp = &p->map[1]; 262 263 qword = (paddr & L2_LINE_ADDR_MSK) / QW_BYTES; 264 cache_line_offset = ((3 - qword) * QW_BITS) + qword_code; 265 offset_inverse = (SAFARI_LAST_BIT - cache_line_offset); 266 dimm_map_index = offset_inverse >> 2; 267 map_val = mp->dimm_map[dimm_map_index]; 268 map_val = ((map_val >> ((3 - (offset_inverse & 3)) << 1)) & 0x3); 269 *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val]; 270 *pin_p = mp->pin_map[cache_line_offset]; 271 } 272} 273 274static struct jbusmc_dimm_group *jbusmc_find_dimm_group(unsigned long phys_addr) 275{ 276 struct jbusmc *p; 277 278 list_for_each_entry(p, &mctrl_list, list) { 279 int i; 280 281 for (i = 0; i < p->num_dimm_groups; i++) { 282 struct jbusmc_dimm_group *dp = &p->dimm_groups[i]; 283 284 if (phys_addr < dp->base_addr || 285 (dp->base_addr + dp->size) <= phys_addr) 286 continue; 287 288 return dp; 289 } 290 } 291 return NULL; 292} 293 294static int jbusmc_print_dimm(int syndrome_code, 295 unsigned long phys_addr, 296 char *buf, int buflen) 297{ 298 struct jbusmc_obp_mem_layout *prop; 299 struct jbusmc_dimm_group *dp; 300 struct jbusmc *p; 301 int first_dimm; 302 303 dp = jbusmc_find_dimm_group(phys_addr); 304 if (dp == NULL || 305 syndrome_code < SYNDROME_MIN || 306 syndrome_code > SYNDROME_MAX) { 307 buf[0] = '?'; 308 buf[1] = '?'; 309 buf[2] = '?'; 310 buf[3] = '\0'; 311 return 0; 312 } 313 p = dp->controller; 314 prop = &p->layout; 315 316 first_dimm = dp->index * JB_NUM_DIMMS_PER_GROUP; 317 318 if (syndrome_code != SYNDROME_MIN) { 319 char *dimm_str; 320 int pin; 321 322 get_pin_and_dimm_str(syndrome_code, phys_addr, &pin, 323 &dimm_str, prop, first_dimm); 324 sprintf(buf, "%s, pin %3d", dimm_str, pin); 325 } else { 326 int dimm; 327 328 /* Multi-bit error, we just dump out all the 329 * dimm labels associated with this dimm group. 330 */ 331 for (dimm = 0; dimm < JB_NUM_DIMMS_PER_GROUP; dimm++) { 332 sprintf(buf, "%s ", 333 prop->dimm_labels[first_dimm + dimm]); 334 buf += strlen(buf); 335 } 336 } 337 338 return 0; 339} 340 341static u64 jbusmc_dimm_group_size(u64 base, 342 const struct linux_prom64_registers *mem_regs, 343 int num_mem_regs) 344{ 345 u64 max = base + (8UL * 1024 * 1024 * 1024); 346 u64 max_seen = base; 347 int i; 348 349 for (i = 0; i < num_mem_regs; i++) { 350 const struct linux_prom64_registers *ent; 351 u64 this_base; 352 u64 this_end; 353 354 ent = &mem_regs[i]; 355 this_base = ent->phys_addr; 356 this_end = this_base + ent->reg_size; 357 if (base < this_base || base >= this_end) 358 continue; 359 if (this_end > max) 360 this_end = max; 361 if (this_end > max_seen) 362 max_seen = this_end; 363 } 364 365 return max_seen - base; 366} 367 368static void jbusmc_construct_one_dimm_group(struct jbusmc *p, 369 unsigned long index, 370 const struct linux_prom64_registers *mem_regs, 371 int num_mem_regs) 372{ 373 struct jbusmc_dimm_group *dp = &p->dimm_groups[index]; 374 375 dp->controller = p; 376 dp->index = index; 377 378 dp->base_addr = (p->portid * (64UL * 1024 * 1024 * 1024)); 379 dp->base_addr += (index * (8UL * 1024 * 1024 * 1024)); 380 dp->size = jbusmc_dimm_group_size(dp->base_addr, mem_regs, num_mem_regs); 381} 382 383static void jbusmc_construct_dimm_groups(struct jbusmc *p, 384 const struct linux_prom64_registers *mem_regs, 385 int num_mem_regs) 386{ 387 if (p->mc_reg_1 & JB_MC_REG1_DIMM1_BANK0) { 388 jbusmc_construct_one_dimm_group(p, 0, mem_regs, num_mem_regs); 389 p->num_dimm_groups++; 390 } 391 if (p->mc_reg_1 & JB_MC_REG1_DIMM2_BANK2) { 392 jbusmc_construct_one_dimm_group(p, 1, mem_regs, num_mem_regs); 393 p->num_dimm_groups++; 394 } 395} 396 397static int jbusmc_probe(struct platform_device *op) 398{ 399 const struct linux_prom64_registers *mem_regs; 400 struct device_node *mem_node; 401 int err, len, num_mem_regs; 402 struct jbusmc *p; 403 const u32 *prop; 404 const void *ml; 405 406 err = -ENODEV; 407 mem_node = of_find_node_by_path("/memory"); 408 if (!mem_node) { 409 printk(KERN_ERR PFX "Cannot find /memory node.\n"); 410 goto out; 411 } 412 mem_regs = of_get_property(mem_node, "reg", &len); 413 if (!mem_regs) { 414 printk(KERN_ERR PFX "Cannot get reg property of /memory node.\n"); 415 goto out; 416 } 417 num_mem_regs = len / sizeof(*mem_regs); 418 419 err = -ENOMEM; 420 p = kzalloc(sizeof(*p), GFP_KERNEL); 421 if (!p) { 422 printk(KERN_ERR PFX "Cannot allocate struct jbusmc.\n"); 423 goto out; 424 } 425 426 INIT_LIST_HEAD(&p->list); 427 428 err = -ENODEV; 429 prop = of_get_property(op->dev.of_node, "portid", &len); 430 if (!prop || len != 4) { 431 printk(KERN_ERR PFX "Cannot find portid.\n"); 432 goto out_free; 433 } 434 435 p->portid = *prop; 436 437 prop = of_get_property(op->dev.of_node, "memory-control-register-1", &len); 438 if (!prop || len != 8) { 439 printk(KERN_ERR PFX "Cannot get memory control register 1.\n"); 440 goto out_free; 441 } 442 443 p->mc_reg_1 = ((u64)prop[0] << 32) | (u64) prop[1]; 444 445 err = -ENOMEM; 446 p->regs = of_ioremap(&op->resource[0], 0, JBUSMC_REGS_SIZE, "jbusmc"); 447 if (!p->regs) { 448 printk(KERN_ERR PFX "Cannot map jbusmc regs.\n"); 449 goto out_free; 450 } 451 452 err = -ENODEV; 453 ml = of_get_property(op->dev.of_node, "memory-layout", &p->layout_len); 454 if (!ml) { 455 printk(KERN_ERR PFX "Cannot get memory layout property.\n"); 456 goto out_iounmap; 457 } 458 if (p->layout_len > sizeof(p->layout)) { 459 printk(KERN_ERR PFX "Unexpected memory-layout size %d\n", 460 p->layout_len); 461 goto out_iounmap; 462 } 463 memcpy(&p->layout, ml, p->layout_len); 464 465 jbusmc_construct_dimm_groups(p, mem_regs, num_mem_regs); 466 467 mc_list_add(&p->list); 468 469 printk(KERN_INFO PFX "UltraSPARC-IIIi memory controller at %pOF\n", 470 op->dev.of_node); 471 472 dev_set_drvdata(&op->dev, p); 473 474 err = 0; 475 476out: 477 return err; 478 479out_iounmap: 480 of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE); 481 482out_free: 483 kfree(p); 484 goto out; 485} 486 487/* Does BANK decode PHYS_ADDR? */ 488static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr) 489{ 490 unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT; 491 unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT; 492 493 /* Bank must be enabled to match. */ 494 if (bp->valid == 0) 495 return 0; 496 497 /* Would BANK match upper bits? */ 498 upper_bits ^= bp->um; /* What bits are different? */ 499 upper_bits = ~upper_bits; /* Invert. */ 500 upper_bits |= bp->uk; /* What bits don't matter for matching? */ 501 upper_bits = ~upper_bits; /* Invert. */ 502 503 if (upper_bits) 504 return 0; 505 506 /* Would BANK match lower bits? */ 507 lower_bits ^= bp->lm; /* What bits are different? */ 508 lower_bits = ~lower_bits; /* Invert. */ 509 lower_bits |= bp->lk; /* What bits don't matter for matching? */ 510 lower_bits = ~lower_bits; /* Invert. */ 511 512 if (lower_bits) 513 return 0; 514 515 /* I always knew you'd be the one. */ 516 return 1; 517} 518 519/* Given PHYS_ADDR, search memory controller banks for a match. */ 520static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr) 521{ 522 struct chmc *p; 523 524 list_for_each_entry(p, &mctrl_list, list) { 525 int bank_no; 526 527 for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) { 528 struct chmc_bank_info *bp; 529 530 bp = &p->logical_banks[bank_no]; 531 if (chmc_bank_match(bp, phys_addr)) 532 return bp; 533 } 534 } 535 536 return NULL; 537} 538 539/* This is the main purpose of this driver. */ 540static int chmc_print_dimm(int syndrome_code, 541 unsigned long phys_addr, 542 char *buf, int buflen) 543{ 544 struct chmc_bank_info *bp; 545 struct chmc_obp_mem_layout *prop; 546 int bank_in_controller, first_dimm; 547 548 bp = chmc_find_bank(phys_addr); 549 if (bp == NULL || 550 syndrome_code < SYNDROME_MIN || 551 syndrome_code > SYNDROME_MAX) { 552 buf[0] = '?'; 553 buf[1] = '?'; 554 buf[2] = '?'; 555 buf[3] = '\0'; 556 return 0; 557 } 558 559 prop = &bp->p->layout_prop; 560 bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1); 561 first_dimm = (bank_in_controller & (CHMCTRL_NDGRPS - 1)); 562 first_dimm *= CHMCTRL_NDIMMS; 563 564 if (syndrome_code != SYNDROME_MIN) { 565 char *dimm_str; 566 int pin; 567 568 get_pin_and_dimm_str(syndrome_code, phys_addr, &pin, 569 &dimm_str, prop, first_dimm); 570 sprintf(buf, "%s, pin %3d", dimm_str, pin); 571 } else { 572 int dimm; 573 574 /* Multi-bit error, we just dump out all the 575 * dimm labels associated with this bank. 576 */ 577 for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) { 578 sprintf(buf, "%s ", 579 prop->dimm_labels[first_dimm + dimm]); 580 buf += strlen(buf); 581 } 582 } 583 return 0; 584} 585 586/* Accessing the registers is slightly complicated. If you want 587 * to get at the memory controller which is on the same processor 588 * the code is executing, you must use special ASI load/store else 589 * you go through the global mapping. 590 */ 591static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset) 592{ 593 unsigned long ret, this_cpu; 594 595 preempt_disable(); 596 597 this_cpu = real_hard_smp_processor_id(); 598 599 if (p->portid == this_cpu) { 600 __asm__ __volatile__("ldxa [%1] %2, %0" 601 : "=r" (ret) 602 : "r" (offset), "i" (ASI_MCU_CTRL_REG)); 603 } else { 604 __asm__ __volatile__("ldxa [%1] %2, %0" 605 : "=r" (ret) 606 : "r" (p->regs + offset), 607 "i" (ASI_PHYS_BYPASS_EC_E)); 608 } 609 610 preempt_enable(); 611 612 return ret; 613} 614 615#if 0 /* currently unused */ 616static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val) 617{ 618 if (p->portid == smp_processor_id()) { 619 __asm__ __volatile__("stxa %0, [%1] %2" 620 : : "r" (val), 621 "r" (offset), "i" (ASI_MCU_CTRL_REG)); 622 } else { 623 __asm__ __volatile__("ldxa %0, [%1] %2" 624 : : "r" (val), 625 "r" (p->regs + offset), 626 "i" (ASI_PHYS_BYPASS_EC_E)); 627 } 628} 629#endif 630 631static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val) 632{ 633 struct chmc_bank_info *bp = &p->logical_banks[which_bank]; 634 635 bp->p = p; 636 bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank; 637 bp->raw_reg = val; 638 bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT; 639 bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT; 640 bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT; 641 bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT; 642 bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT; 643 644 bp->base = (bp->um); 645 bp->base &= ~(bp->uk); 646 bp->base <<= PA_UPPER_BITS_SHIFT; 647 648 switch(bp->lk) { 649 case 0xf: 650 default: 651 bp->interleave = 1; 652 break; 653 654 case 0xe: 655 bp->interleave = 2; 656 break; 657 658 case 0xc: 659 bp->interleave = 4; 660 break; 661 662 case 0x8: 663 bp->interleave = 8; 664 break; 665 666 case 0x0: 667 bp->interleave = 16; 668 break; 669 } 670 671 /* UK[10] is reserved, and UK[11] is not set for the SDRAM 672 * bank size definition. 673 */ 674 bp->size = (((unsigned long)bp->uk & 675 ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT; 676 bp->size /= bp->interleave; 677} 678 679static void chmc_fetch_decode_regs(struct chmc *p) 680{ 681 if (p->layout_size == 0) 682 return; 683 684 chmc_interpret_one_decode_reg(p, 0, 685 chmc_read_mcreg(p, CHMCTRL_DECODE1)); 686 chmc_interpret_one_decode_reg(p, 1, 687 chmc_read_mcreg(p, CHMCTRL_DECODE2)); 688 chmc_interpret_one_decode_reg(p, 2, 689 chmc_read_mcreg(p, CHMCTRL_DECODE3)); 690 chmc_interpret_one_decode_reg(p, 3, 691 chmc_read_mcreg(p, CHMCTRL_DECODE4)); 692} 693 694static int chmc_probe(struct platform_device *op) 695{ 696 struct device_node *dp = op->dev.of_node; 697 unsigned long ver; 698 const void *pval; 699 int len, portid; 700 struct chmc *p; 701 int err; 702 703 err = -ENODEV; 704 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 705 if ((ver >> 32UL) == __JALAPENO_ID || 706 (ver >> 32UL) == __SERRANO_ID) 707 goto out; 708 709 portid = of_getintprop_default(dp, "portid", -1); 710 if (portid == -1) 711 goto out; 712 713 pval = of_get_property(dp, "memory-layout", &len); 714 if (pval && len > sizeof(p->layout_prop)) { 715 printk(KERN_ERR PFX "Unexpected memory-layout property " 716 "size %d.\n", len); 717 goto out; 718 } 719 720 err = -ENOMEM; 721 p = kzalloc(sizeof(*p), GFP_KERNEL); 722 if (!p) { 723 printk(KERN_ERR PFX "Could not allocate struct chmc.\n"); 724 goto out; 725 } 726 727 p->portid = portid; 728 p->layout_size = len; 729 if (!pval) 730 p->layout_size = 0; 731 else 732 memcpy(&p->layout_prop, pval, len); 733 734 p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc"); 735 if (!p->regs) { 736 printk(KERN_ERR PFX "Could not map registers.\n"); 737 goto out_free; 738 } 739 740 if (p->layout_size != 0UL) { 741 p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1); 742 p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2); 743 p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3); 744 p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4); 745 p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL); 746 } 747 748 chmc_fetch_decode_regs(p); 749 750 mc_list_add(&p->list); 751 752 printk(KERN_INFO PFX "UltraSPARC-III memory controller at %pOF [%s]\n", 753 dp, 754 (p->layout_size ? "ACTIVE" : "INACTIVE")); 755 756 dev_set_drvdata(&op->dev, p); 757 758 err = 0; 759 760out: 761 return err; 762 763out_free: 764 kfree(p); 765 goto out; 766} 767 768static int us3mc_probe(struct platform_device *op) 769{ 770 if (mc_type == MC_TYPE_SAFARI) 771 return chmc_probe(op); 772 else if (mc_type == MC_TYPE_JBUS) 773 return jbusmc_probe(op); 774 return -ENODEV; 775} 776 777static void chmc_destroy(struct platform_device *op, struct chmc *p) 778{ 779 list_del(&p->list); 780 of_iounmap(&op->resource[0], p->regs, 0x48); 781 kfree(p); 782} 783 784static void jbusmc_destroy(struct platform_device *op, struct jbusmc *p) 785{ 786 mc_list_del(&p->list); 787 of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE); 788 kfree(p); 789} 790 791static int us3mc_remove(struct platform_device *op) 792{ 793 void *p = dev_get_drvdata(&op->dev); 794 795 if (p) { 796 if (mc_type == MC_TYPE_SAFARI) 797 chmc_destroy(op, p); 798 else if (mc_type == MC_TYPE_JBUS) 799 jbusmc_destroy(op, p); 800 } 801 return 0; 802} 803 804static const struct of_device_id us3mc_match[] = { 805 { 806 .name = "memory-controller", 807 }, 808 {}, 809}; 810MODULE_DEVICE_TABLE(of, us3mc_match); 811 812static struct platform_driver us3mc_driver = { 813 .driver = { 814 .name = "us3mc", 815 .of_match_table = us3mc_match, 816 }, 817 .probe = us3mc_probe, 818 .remove = us3mc_remove, 819}; 820 821static inline bool us3mc_platform(void) 822{ 823 if (tlb_type == cheetah || tlb_type == cheetah_plus) 824 return true; 825 return false; 826} 827 828static int __init us3mc_init(void) 829{ 830 unsigned long ver; 831 int ret; 832 833 if (!us3mc_platform()) 834 return -ENODEV; 835 836 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 837 if ((ver >> 32UL) == __JALAPENO_ID || 838 (ver >> 32UL) == __SERRANO_ID) { 839 mc_type = MC_TYPE_JBUS; 840 us3mc_dimm_printer = jbusmc_print_dimm; 841 } else { 842 mc_type = MC_TYPE_SAFARI; 843 us3mc_dimm_printer = chmc_print_dimm; 844 } 845 846 ret = register_dimm_printer(us3mc_dimm_printer); 847 848 if (!ret) { 849 ret = platform_driver_register(&us3mc_driver); 850 if (ret) 851 unregister_dimm_printer(us3mc_dimm_printer); 852 } 853 return ret; 854} 855 856static void __exit us3mc_cleanup(void) 857{ 858 if (us3mc_platform()) { 859 unregister_dimm_printer(us3mc_dimm_printer); 860 platform_driver_unregister(&us3mc_driver); 861 } 862} 863 864module_init(us3mc_init); 865module_exit(us3mc_cleanup); 866