1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup
4 *
5 *  Copyright (C) 2006  Paul Mundt
6 *  Copyright (C) 2006  Jamie Lenehan
7 */
8#include <linux/platform_device.h>
9#include <linux/init.h>
10#include <linux/serial.h>
11#include <linux/io.h>
12#include <linux/sh_timer.h>
13#include <linux/sh_intc.h>
14#include <linux/serial_sci.h>
15#include <generated/machtypes.h>
16#include <asm/platform_early.h>
17
18static struct resource rtc_resources[] = {
19	[0] = {
20		.start	= 0xffc80000,
21		.end	= 0xffc80000 + 0x58 - 1,
22		.flags	= IORESOURCE_IO,
23	},
24	[1] = {
25		/* Shared Period/Carry/Alarm IRQ */
26		.start	= evt2irq(0x480),
27		.flags	= IORESOURCE_IRQ,
28	},
29};
30
31static struct platform_device rtc_device = {
32	.name		= "sh-rtc",
33	.id		= -1,
34	.num_resources	= ARRAY_SIZE(rtc_resources),
35	.resource	= rtc_resources,
36};
37
38static struct plat_sci_port sci_platform_data = {
39	.type		= PORT_SCI,
40};
41
42static struct resource sci_resources[] = {
43	DEFINE_RES_MEM(0xffe00000, 0x20),
44	DEFINE_RES_IRQ(evt2irq(0x4e0)),
45};
46
47static struct platform_device sci_device = {
48	.name		= "sh-sci",
49	.id		= 0,
50	.resource	= sci_resources,
51	.num_resources	= ARRAY_SIZE(sci_resources),
52	.dev		= {
53		.platform_data	= &sci_platform_data,
54	},
55};
56
57static struct plat_sci_port scif_platform_data = {
58	.scscr		= SCSCR_REIE,
59	.type		= PORT_SCIF,
60};
61
62static struct resource scif_resources[] = {
63	DEFINE_RES_MEM(0xffe80000, 0x100),
64	DEFINE_RES_IRQ(evt2irq(0x700)),
65};
66
67static struct platform_device scif_device = {
68	.name		= "sh-sci",
69	.id		= 1,
70	.resource	= scif_resources,
71	.num_resources	= ARRAY_SIZE(scif_resources),
72	.dev		= {
73		.platform_data	= &scif_platform_data,
74	},
75};
76
77static struct sh_timer_config tmu0_platform_data = {
78	.channels_mask = 7,
79};
80
81static struct resource tmu0_resources[] = {
82	DEFINE_RES_MEM(0xffd80000, 0x30),
83	DEFINE_RES_IRQ(evt2irq(0x400)),
84	DEFINE_RES_IRQ(evt2irq(0x420)),
85	DEFINE_RES_IRQ(evt2irq(0x440)),
86};
87
88static struct platform_device tmu0_device = {
89	.name		= "sh-tmu",
90	.id		= 0,
91	.dev = {
92		.platform_data	= &tmu0_platform_data,
93	},
94	.resource	= tmu0_resources,
95	.num_resources	= ARRAY_SIZE(tmu0_resources),
96};
97
98/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
99#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
100	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
101	defined(CONFIG_CPU_SUBTYPE_SH7751R)
102
103static struct sh_timer_config tmu1_platform_data = {
104	.channels_mask = 3,
105};
106
107static struct resource tmu1_resources[] = {
108	DEFINE_RES_MEM(0xfe100000, 0x20),
109	DEFINE_RES_IRQ(evt2irq(0xb00)),
110	DEFINE_RES_IRQ(evt2irq(0xb80)),
111};
112
113static struct platform_device tmu1_device = {
114	.name		= "sh-tmu",
115	.id		= 1,
116	.dev = {
117		.platform_data	= &tmu1_platform_data,
118	},
119	.resource	= tmu1_resources,
120	.num_resources	= ARRAY_SIZE(tmu1_resources),
121};
122
123#endif
124
125static struct platform_device *sh7750_devices[] __initdata = {
126	&rtc_device,
127	&tmu0_device,
128#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
129	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
130	defined(CONFIG_CPU_SUBTYPE_SH7751R)
131	&tmu1_device,
132#endif
133};
134
135static int __init sh7750_devices_setup(void)
136{
137	if (mach_is_rts7751r2d()) {
138		platform_device_register(&scif_device);
139	} else {
140		platform_device_register(&sci_device);
141		platform_device_register(&scif_device);
142	}
143
144	return platform_add_devices(sh7750_devices,
145				    ARRAY_SIZE(sh7750_devices));
146}
147arch_initcall(sh7750_devices_setup);
148
149static struct platform_device *sh7750_early_devices[] __initdata = {
150	&tmu0_device,
151#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
152	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
153	defined(CONFIG_CPU_SUBTYPE_SH7751R)
154	&tmu1_device,
155#endif
156};
157
158void __init plat_early_device_setup(void)
159{
160	struct platform_device *dev[1];
161
162	if (mach_is_rts7751r2d()) {
163		scif_platform_data.scscr |= SCSCR_CKE1;
164		dev[0] = &scif_device;
165		sh_early_platform_add_devices(dev, 1);
166	} else {
167		dev[0] = &sci_device;
168		sh_early_platform_add_devices(dev, 1);
169		dev[0] = &scif_device;
170		sh_early_platform_add_devices(dev, 1);
171	}
172
173	sh_early_platform_add_devices(sh7750_early_devices,
174				   ARRAY_SIZE(sh7750_early_devices));
175}
176
177enum {
178	UNUSED = 0,
179
180	/* interrupt sources */
181	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
182	HUDI, GPIOI, DMAC,
183	PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
184	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
185	TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
186
187	/* interrupt groups */
188	PCIC1,
189};
190
191static struct intc_vect vectors[] __initdata = {
192	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
193	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
194	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
195	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
196	INTC_VECT(RTC, 0x4c0),
197	INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
198	INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
199	INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
200	INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
201	INTC_VECT(WDT, 0x560),
202	INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
203};
204
205static struct intc_prio_reg prio_registers[] __initdata = {
206	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
207	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
208	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
209	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
210	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
211						 TMU4, TMU3,
212						 PCIC1, PCIC0_PCISERR } },
213};
214
215static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
216			 NULL, prio_registers, NULL);
217
218/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
219#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
220	defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
221	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
222	defined(CONFIG_CPU_SUBTYPE_SH7091)
223static struct intc_vect vectors_dma4[] __initdata = {
224	INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
225	INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
226	INTC_VECT(DMAC, 0x6c0),
227};
228
229static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
230			 vectors_dma4, NULL,
231			 NULL, prio_registers, NULL);
232#endif
233
234/* SH7750R and SH7751R both have 8-channel DMA controllers */
235#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
236static struct intc_vect vectors_dma8[] __initdata = {
237	INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
238	INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
239	INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
240	INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
241	INTC_VECT(DMAC, 0x6c0),
242};
243
244static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
245			 vectors_dma8, NULL,
246			 NULL, prio_registers, NULL);
247#endif
248
249/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
250#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
251	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
252	defined(CONFIG_CPU_SUBTYPE_SH7751R)
253static struct intc_vect vectors_tmu34[] __initdata = {
254	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
255};
256
257static struct intc_mask_reg mask_registers[] __initdata = {
258	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
259	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260	    0, 0, 0, 0, 0, 0, TMU4, TMU3,
261	    PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
262	    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
263	    PCIC1_PCIDMA3, PCIC0_PCISERR } },
264};
265
266static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
267			 vectors_tmu34, NULL,
268			 mask_registers, prio_registers, NULL);
269#endif
270
271/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
272static struct intc_vect vectors_irlm[] __initdata = {
273	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
274	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
275};
276
277static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
278			 NULL, prio_registers, NULL);
279
280/* SH7751 and SH7751R both have PCI */
281#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
282static struct intc_vect vectors_pci[] __initdata = {
283	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
284	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
285	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
286	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
287};
288
289static struct intc_group groups_pci[] __initdata = {
290	INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
291		   PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
292};
293
294static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
295			 mask_registers, prio_registers, NULL);
296#endif
297
298#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
299	defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
300	defined(CONFIG_CPU_SUBTYPE_SH7091)
301void __init plat_irq_setup(void)
302{
303	/*
304	 * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
305	 * see below..
306	 */
307	register_intc_controller(&intc_desc);
308	register_intc_controller(&intc_desc_dma4);
309}
310#endif
311
312#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
313void __init plat_irq_setup(void)
314{
315	register_intc_controller(&intc_desc);
316	register_intc_controller(&intc_desc_dma8);
317	register_intc_controller(&intc_desc_tmu34);
318}
319#endif
320
321#if defined(CONFIG_CPU_SUBTYPE_SH7751)
322void __init plat_irq_setup(void)
323{
324	register_intc_controller(&intc_desc);
325	register_intc_controller(&intc_desc_dma4);
326	register_intc_controller(&intc_desc_tmu34);
327	register_intc_controller(&intc_desc_pci);
328}
329#endif
330
331#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
332void __init plat_irq_setup(void)
333{
334	register_intc_controller(&intc_desc);
335	register_intc_controller(&intc_desc_dma8);
336	register_intc_controller(&intc_desc_tmu34);
337	register_intc_controller(&intc_desc_pci);
338}
339#endif
340
341#define INTC_ICR	0xffd00000UL
342#define INTC_ICR_IRLM   (1<<7)
343
344void __init plat_irq_setup_pins(int mode)
345{
346#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
347	BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
348	return;
349#endif
350
351	switch (mode) {
352	case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
353		__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
354		register_intc_controller(&intc_desc_irlm);
355		break;
356	default:
357		BUG();
358	}
359}
360