1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709 4 * 5 * Copyright (C) 2007 Magnus Damm 6 * Copyright (C) 2009 Paul Mundt 7 * 8 * Based on setup-sh7709.c 9 * 10 * Copyright (C) 2006 Paul Mundt 11 */ 12#include <linux/init.h> 13#include <linux/io.h> 14#include <linux/irq.h> 15#include <linux/platform_device.h> 16#include <linux/serial.h> 17#include <linux/serial_sci.h> 18#include <linux/sh_timer.h> 19#include <linux/sh_intc.h> 20#include <cpu/serial.h> 21#include <asm/platform_early.h> 22 23enum { 24 UNUSED = 0, 25 26 /* interrupt sources */ 27 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 28 PINT07, PINT815, 29 DMAC, SCIF0, SCIF2, SCI, ADC_ADI, 30 LCDC, PCC0, PCC1, 31 TMU0, TMU1, TMU2, 32 RTC, WDT, REF, 33}; 34 35static struct intc_vect vectors[] __initdata = { 36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 39 INTC_VECT(RTC, 0x4c0), 40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500), 41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540), 42 INTC_VECT(WDT, 0x560), 43 INTC_VECT(REF, 0x580), 44 INTC_VECT(REF, 0x5a0), 45#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 46 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 47 defined(CONFIG_CPU_SUBTYPE_SH7709) 48 /* IRQ0->5 are handled in setup-sh3.c */ 49 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820), 50 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860), 51 INTC_VECT(ADC_ADI, 0x980), 52 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920), 53 INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960), 54#endif 55#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 56 defined(CONFIG_CPU_SUBTYPE_SH7709) 57 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 58 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), 59 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), 60#endif 61#if defined(CONFIG_CPU_SUBTYPE_SH7707) 62 INTC_VECT(LCDC, 0x9a0), 63 INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0), 64#endif 65}; 66 67static struct intc_prio_reg prio_registers[] __initdata = { 68 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 69 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, 70#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 71 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 72 defined(CONFIG_CPU_SUBTYPE_SH7709) 73 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 74 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 75 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } }, 76#endif 77#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 78 defined(CONFIG_CPU_SUBTYPE_SH7709) 79 { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } }, 80 { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } }, 81#endif 82#if defined(CONFIG_CPU_SUBTYPE_SH7707) 83 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } }, 84#endif 85}; 86 87static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL, 88 NULL, prio_registers, NULL); 89 90static struct resource rtc_resources[] = { 91 [0] = { 92 .start = 0xfffffec0, 93 .end = 0xfffffec0 + 0x1e, 94 .flags = IORESOURCE_IO, 95 }, 96 [1] = { 97 .start = evt2irq(0x480), 98 .flags = IORESOURCE_IRQ, 99 }, 100}; 101 102static struct platform_device rtc_device = { 103 .name = "sh-rtc", 104 .id = -1, 105 .num_resources = ARRAY_SIZE(rtc_resources), 106 .resource = rtc_resources, 107}; 108 109static struct plat_sci_port scif0_platform_data = { 110 .type = PORT_SCI, 111 .ops = &sh770x_sci_port_ops, 112}; 113 114static struct resource scif0_resources[] = { 115 DEFINE_RES_MEM(0xfffffe80, 0x10), 116 DEFINE_RES_IRQ(evt2irq(0x4e0)), 117}; 118 119static struct platform_device scif0_device = { 120 .name = "sh-sci", 121 .id = 0, 122 .resource = scif0_resources, 123 .num_resources = ARRAY_SIZE(scif0_resources), 124 .dev = { 125 .platform_data = &scif0_platform_data, 126 }, 127}; 128#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 129 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 130 defined(CONFIG_CPU_SUBTYPE_SH7709) 131static struct plat_sci_port scif1_platform_data = { 132 .type = PORT_SCIF, 133 .ops = &sh770x_sci_port_ops, 134 .regtype = SCIx_SH3_SCIF_REGTYPE, 135}; 136 137static struct resource scif1_resources[] = { 138 DEFINE_RES_MEM(0xa4000150, 0x10), 139 DEFINE_RES_IRQ(evt2irq(0x900)), 140}; 141 142static struct platform_device scif1_device = { 143 .name = "sh-sci", 144 .id = 1, 145 .resource = scif1_resources, 146 .num_resources = ARRAY_SIZE(scif1_resources), 147 .dev = { 148 .platform_data = &scif1_platform_data, 149 }, 150}; 151#endif 152#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 153 defined(CONFIG_CPU_SUBTYPE_SH7709) 154static struct plat_sci_port scif2_platform_data = { 155 .type = PORT_IRDA, 156 .ops = &sh770x_sci_port_ops, 157}; 158 159static struct resource scif2_resources[] = { 160 DEFINE_RES_MEM(0xa4000140, 0x10), 161 DEFINE_RES_IRQ(evt2irq(0x880)), 162}; 163 164static struct platform_device scif2_device = { 165 .name = "sh-sci", 166 .id = 2, 167 .resource = scif2_resources, 168 .num_resources = ARRAY_SIZE(scif2_resources), 169 .dev = { 170 .platform_data = &scif2_platform_data, 171 }, 172}; 173#endif 174 175static struct sh_timer_config tmu0_platform_data = { 176 .channels_mask = 7, 177}; 178 179static struct resource tmu0_resources[] = { 180 DEFINE_RES_MEM(0xfffffe90, 0x2c), 181 DEFINE_RES_IRQ(evt2irq(0x400)), 182 DEFINE_RES_IRQ(evt2irq(0x420)), 183 DEFINE_RES_IRQ(evt2irq(0x440)), 184}; 185 186static struct platform_device tmu0_device = { 187 .name = "sh-tmu-sh3", 188 .id = 0, 189 .dev = { 190 .platform_data = &tmu0_platform_data, 191 }, 192 .resource = tmu0_resources, 193 .num_resources = ARRAY_SIZE(tmu0_resources), 194}; 195 196static struct platform_device *sh770x_devices[] __initdata = { 197 &scif0_device, 198#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 199 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 200 defined(CONFIG_CPU_SUBTYPE_SH7709) 201 &scif1_device, 202#endif 203#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 204 defined(CONFIG_CPU_SUBTYPE_SH7709) 205 &scif2_device, 206#endif 207 &tmu0_device, 208 &rtc_device, 209}; 210 211static int __init sh770x_devices_setup(void) 212{ 213 return platform_add_devices(sh770x_devices, 214 ARRAY_SIZE(sh770x_devices)); 215} 216arch_initcall(sh770x_devices_setup); 217 218static struct platform_device *sh770x_early_devices[] __initdata = { 219 &scif0_device, 220#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 221 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 222 defined(CONFIG_CPU_SUBTYPE_SH7709) 223 &scif1_device, 224#endif 225#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 226 defined(CONFIG_CPU_SUBTYPE_SH7709) 227 &scif2_device, 228#endif 229 &tmu0_device, 230}; 231 232void __init plat_early_device_setup(void) 233{ 234 sh_early_platform_add_devices(sh770x_early_devices, 235 ARRAY_SIZE(sh770x_early_devices)); 236} 237 238void __init plat_irq_setup(void) 239{ 240 register_intc_controller(&intc_desc); 241#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 242 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 243 defined(CONFIG_CPU_SUBTYPE_SH7709) 244 plat_irq_setup_sh3(); 245#endif 246} 247